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freedreno/a4xx: add stencil texturing support
Copied from a5xx, should be identical. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Rob Clark <robdclark@gmail.com>
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@ -180,7 +180,7 @@ GL 4.3, GLSL 4.30 -- all DONE: i965/gen8+, nvc0, radeonsi
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GL_ARB_robust_buffer_access_behavior DONE (i965)
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GL_ARB_shader_image_size DONE (freedreno/a5xx, i965, r600, softpipe)
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GL_ARB_shader_storage_buffer_object DONE (freedreno/a5xx, i965, softpipe)
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GL_ARB_stencil_texturing DONE (freedreno/a5xx, i965/hsw+, nv50, r600, llvmpipe, softpipe, swr)
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GL_ARB_stencil_texturing DONE (freedreno, i965/hsw+, nv50, r600, llvmpipe, softpipe, swr)
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GL_ARB_texture_buffer_range DONE (freedreno, nv50, i965, r600, llvmpipe)
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GL_ARB_texture_query_levels DONE (all drivers that support GLSL 1.30)
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GL_ARB_texture_storage_multisample DONE (all drivers that support GL_ARB_texture_multisample)
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@ -203,7 +203,7 @@ GL 4.4, GLSL 4.40 -- all DONE: i965/gen8+, nvc0, radeonsi
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GL_ARB_multi_bind DONE (all drivers)
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GL_ARB_query_buffer_object DONE (i965/hsw+)
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GL_ARB_texture_mirror_clamp_to_edge DONE (i965, nv50, r600, llvmpipe, softpipe, swr)
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GL_ARB_texture_stencil8 DONE (freedreno/a5xx, i965/hsw+, nv50, r600, llvmpipe, softpipe, swr)
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GL_ARB_texture_stencil8 DONE (freedreno, i965/hsw+, nv50, r600, llvmpipe, softpipe, swr)
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GL_ARB_vertex_type_10f_11f_11f_rev DONE (i965, nv50, r600, llvmpipe, softpipe, swr)
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GL 4.5, GLSL 4.50 -- all DONE: nvc0, radeonsi
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@ -252,7 +252,7 @@ GLES3.1, GLSL ES 3.1 -- all DONE: i965/hsw+, nvc0, radeonsi
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GL_ARB_shader_storage_buffer_object DONE (freedreno/a5xx, i965/gen7+, softpipe)
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GL_ARB_shading_language_packing DONE (all drivers)
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GL_ARB_separate_shader_objects DONE (all drivers)
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GL_ARB_stencil_texturing DONE (freedreno/a5xx, nv50, r600, llvmpipe, softpipe, swr)
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GL_ARB_stencil_texturing DONE (freedreno, nv50, r600, llvmpipe, softpipe, swr)
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GL_ARB_texture_multisample (Multisample textures) DONE (i965/gen7+, nv50, r600, llvmpipe, softpipe)
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GL_ARB_texture_storage_multisample DONE (all drivers that support GL_ARB_texture_multisample)
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GL_ARB_vertex_attrib_binding DONE (all drivers)
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@ -190,6 +190,8 @@ emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
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OUT_RING(ring, view->texconst3);
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if (view->base.texture) {
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struct fd_resource *rsc = fd_resource(view->base.texture);
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if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
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rsc = rsc->stencil;
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OUT_RELOC(ring, rsc->bo, view->offset, view->texconst4, 0);
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} else {
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OUT_RING(ring, 0x00000000);
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@ -211,10 +211,13 @@ static struct fd4_format formats[PIPE_FORMAT_COUNT] = {
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VT(R11G11B10_FLOAT, 11_11_10_FLOAT, R11G11B10_FLOAT, WZYX),
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_T(R9G9B9E5_FLOAT, 9_9_9_E5_FLOAT, NONE, WZYX),
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_T(Z24X8_UNORM, X8Z24_UNORM, R8G8B8A8_UNORM, WZYX),
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_T(Z24_UNORM_S8_UINT, X8Z24_UNORM, R8G8B8A8_UNORM, WZYX),
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_T(Z32_FLOAT, 32_FLOAT, R8G8B8A8_UNORM, WZYX),
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_T(Z32_FLOAT_S8X24_UINT, 32_FLOAT,R8G8B8A8_UNORM, WZYX),
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_T(Z16_UNORM, 16_UNORM, R8G8_UNORM, WZYX),
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_T(Z24X8_UNORM, X8Z24_UNORM, R8G8B8A8_UNORM, WZYX),
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_T(X24S8_UINT, 8_8_8_8_UINT, R8G8B8A8_UINT, XYZW),
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_T(Z24_UNORM_S8_UINT, X8Z24_UNORM, R8G8B8A8_UNORM, WZYX),
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_T(Z32_FLOAT, 32_FLOAT, R8G8B8A8_UNORM, WZYX),
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_T(Z32_FLOAT_S8X24_UINT, 32_FLOAT, R8G8B8A8_UNORM, WZYX),
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_T(X32_S8X24_UINT, 8_UINT, R8_UINT, WZYX),
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/* 48-bit */
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V_(R16G16B16_UNORM, 16_16_16_UNORM, NONE, WZYX),
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@ -224,12 +224,18 @@ fd4_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
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{
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struct fd4_pipe_sampler_view *so = CALLOC_STRUCT(fd4_pipe_sampler_view);
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struct fd_resource *rsc = fd_resource(prsc);
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enum pipe_format format = cso->format;
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unsigned lvl, layers;
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uint32_t sz2 = 0;
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if (!so)
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return NULL;
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if (format == PIPE_FORMAT_X32_S8X24_UINT) {
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rsc = rsc->stencil;
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format = rsc->base.b.format;
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}
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so->base = *cso;
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pipe_reference(NULL, &prsc->reference);
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so->base.texture = prsc;
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@ -238,25 +244,25 @@ fd4_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
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so->texconst0 =
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A4XX_TEX_CONST_0_TYPE(tex_type(cso->target)) |
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A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(cso->format)) |
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fd4_tex_swiz(cso->format, cso->swizzle_r, cso->swizzle_g,
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A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(format)) |
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fd4_tex_swiz(format, cso->swizzle_r, cso->swizzle_g,
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cso->swizzle_b, cso->swizzle_a);
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if (util_format_is_srgb(cso->format)) {
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if (use_astc_srgb_workaround(pctx, cso->format))
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if (util_format_is_srgb(format)) {
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if (use_astc_srgb_workaround(pctx, format))
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so->astc_srgb = true;
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so->texconst0 |= A4XX_TEX_CONST_0_SRGB;
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}
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if (cso->target == PIPE_BUFFER) {
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unsigned elements = cso->u.buf.size / util_format_get_blocksize(cso->format);
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unsigned elements = cso->u.buf.size / util_format_get_blocksize(format);
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lvl = 0;
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so->texconst1 =
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A4XX_TEX_CONST_1_WIDTH(elements) |
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A4XX_TEX_CONST_1_HEIGHT(1);
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so->texconst2 =
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A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(cso->format)) |
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A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(format)) |
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A4XX_TEX_CONST_2_PITCH(elements * rsc->cpp);
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so->offset = cso->u.buf.offset;
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} else {
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@ -271,13 +277,25 @@ fd4_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
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A4XX_TEX_CONST_1_WIDTH(u_minify(prsc->width0, lvl)) |
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A4XX_TEX_CONST_1_HEIGHT(u_minify(prsc->height0, lvl));
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so->texconst2 =
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A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(cso->format)) |
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A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(format)) |
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A4XX_TEX_CONST_2_PITCH(
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util_format_get_nblocksx(
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cso->format, rsc->slices[lvl].pitch) * rsc->cpp);
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format, rsc->slices[lvl].pitch) * rsc->cpp);
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so->offset = fd_resource_offset(rsc, lvl, cso->u.tex.first_layer);
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}
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/* NOTE: since we sample z24s8 using 8888_UINT format, the swizzle
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* we get isn't quite right. Use SWAP(XYZW) as a cheap and cheerful
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* way to re-arrange things so stencil component is where the swiz
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* expects.
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*
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* Note that gallium expects stencil sampler to return (s,s,s,s)
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* which isn't quite true. To make that happen we'd have to massage
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* the swizzle. But in practice only the .x component is used.
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*/
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if (format == PIPE_FORMAT_X24S8_UINT)
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so->texconst2 |= A4XX_TEX_CONST_2_SWAP(XYZW);
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switch (cso->target) {
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case PIPE_TEXTURE_1D_ARRAY:
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case PIPE_TEXTURE_2D_ARRAY:
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