there's no requirement in the spec that the geometry for resolves must match,
only that the geometry must be positive (i.e., no flipped extents)
this avoids major perf issues for scaled resolves
cc: mesa-stable
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18364>
(cherry picked from commit 513fcb793600056b421b5528325d192e7e23a328)
void clears are intended to be the first clear applied to a surface,
so ensure that these don't clobber any scissored clears
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18627>
(cherry picked from commit 13a19ad90c4ea15aa169b31a8566d962a9970232)
this has to adjust using dest size, not hardcoded as uint32
Fixes: 5a95c6b328 ("zink: rewrite atomic ssbo intrinsics as atomic derefs")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18144>
(cherry picked from commit 99a4a9c6ff09f4a326341432ca75f18ddcdc0bf8)
since the transition to UINT pipe cap, this no longer needs to be
restricted to appease gallium
fixes#7103
cc: mesa-stable
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18144>
(cherry picked from commit 96be036a6b521e45785f0ff53d983116c1f4db1d)
If we override with gnu99 here, we effectively down-grade from C11,
meaning we can no longer assume static_assert support.
Fixes: 45fb815a75 ("util: implement STATIC_ASSERT using c++11 / c11 primitives")
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Suggested-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18611>
(cherry picked from commit a9f3e011e5f14af4ac4ccd6e581b6ec7cd8b8554)
these come in as yoffset, but the constant data must use 0 since the sampler
view is created with the offset
cc: mesa-stable
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18118>
(cherry picked from commit cd07a0002f10869136aa61e59f9bbcdb02d1a2d6)
Some ASICs with gfx9 use compute rings for render.
Fixes: 983223de5d - ac/gpu_info: use the kernel-reported
GFX IP version to set gfx_level
-v2: update merge requests num
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18553>
(cherry picked from commit fe8e18c7824b35ac83a6c0da50d4b01728675bb0)
The logic was inverted, we don't need aligned for later gens.
Fixes: 60912f1ebd ("freedreno: we don't need aligned vbo's")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18605>
(cherry picked from commit 2664d59aeec72da8608611860ab6a9e2d944922a)
if the swapchain image is acquired in a different cmdbuf than it gets
presented with, the acquire semaphore will have already been submitted
by this point, and the swapchain should be flagged as such
cc: mesa-stable
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18557>
(cherry picked from commit db192c08837300fe7017195effe047379c69dd96)
We don't know how many descriptors will actually be valid, which could
lead to preloading descriptors out-of-bounds of the descriptor size.
This was leading to GPU hangs on some tests once we enabled inline
uniforms.
Fixes: d9fcf5de55 ("turnip: Enable nonuniform descriptor indexing")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17960>
(cherry picked from commit 15f3274ea6150ee1b778b9e891269692496cab19)
`kill` changes which fibers are active, thus reodering instructions
which depend on which fibers are active - is wrong.
The issue was hidden because only `ballot(true)` is translated to movmsk
immidiately, while others are passed as MACRO and don't properly
take part in ir3_sched (which does the reordering).
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7162
Fixes CTS test (on gen3+):
dEQP-VK.spirv_assembly.instruction.terminate_invocation.terminate.subgroup_ballot
Fixes: b1b80c06a7
("ir3: Implement nir subgroup intrinsics")
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18413>
(cherry picked from commit 33e60798e144c6638343486371462e5522f3afd4)
The first argument is the name of the library, and the second argument
is the list of files; those two got a bit mixed up.
Fixes: 1ae8018a6a ("meson: Add support for the vc4 driver.")
Fixes: 4f3e380fa0 ("meson: Add support for the vc5 driver.")
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18593>
(cherry picked from commit 5bfca00d318e8fdbe6914fc358d24af983086f15)
This can be very slow on dGPU.
I tried a different version that would allocate a full row
and then do a single memcpy per row but the performance
was similar so I kept the simple version.
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18484>
(cherry picked from commit a5b1a811053eef74e8e0353ebbe2bb9c68e5c26b)
This is so dumb. Panfrost port of d98b82a103 ("iris/cs: take buffer offsets
into account for CL")
Fixes buffer.sub_buffers_read_write
Fixes: 80b90a0f2b ("panfrost: Implement panfrost_set_global_binding")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Suggested-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18560>
(cherry picked from commit b4dd1b8916d95576fb7277e96f1c3a1e5afc126d)
OpenGL 3.0 requires RGTC support, and until we have emulation in place,
we should document that requirement.
Fixes: d50e8554b9 ("zink: add feature-documentation")
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18549>
(cherry picked from commit 3454ff21e59446a5371bb85749707d3a1cec9805)
From the Vulkan spec 1.3.227:
"If pipelineStageCreationFeedbackCount is not 0,
pPipelineStageCreationFeedbacks must be a valid pointer to an
array of pipelineStageCreationFeedbackCount
VkPipelineCreationFeedback structures."
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18513>
(cherry picked from commit 28af93ace7b4a5d7dfd1cbfa6ab14ffcb86ad6ba)
Similar to how other I/O info is cleared at the beginning
of gather_info we should also clear the cross-invocation
mesh shader output mask.
Fixes: 112a856813
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18464>
(cherry picked from commit e58a5cca0293ab10ec327debf85175901d027478)
For in-fence handling, dri2 has this below sequence in a row:
1. create_fence_fd: import external fence fd
2. fence_server_sync: import the pipe fence into the driver ctx
3. fence_reference: deref the created pipe fence
Before this change, zink pushed the wrapped external semaphore to the
wait semaphores of the next batch but the followed fence_reference will
destroy the imported semaphore immediately. Instead of extending the
lifecycle of the pipe fence throughout the batch state, we can simply
transfer the semaphore ownership to the batch and destroy it upon batch
reset.
Fixes: 32597e116d ("zink: implement GL semaphores")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18453>
(cherry picked from commit 6d1e214238276e86e979cebef7eb4c8982a357ea)
This change fixes below:
1. Dup the fence fd, otherwise, since external semaphore import takes
the ownership of the fd, non-Vulkan part touches the fd leading to
undefined behavior. This can be hit on implementations that defer
the processing of the passed fd.
2. Use VK_SEMAPHORE_IMPORT_TEMPORARY_BIT for importing since that's
required for SYNC_FD handle type because of its copy transference.
Meanwhile, doing temporary import for opaque fd is fine in this path.
Fixes: 32597e116d ("zink: implement GL semaphores")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18453>
(cherry picked from commit c1b827d6a25527ae61dd0c102c5cc3f6e42dc90a)
this ensures types which consume more than 1 slot are effectively tagged
so that the next stage inputs are also assigned properly
fixes:
spec@arb_enhanced_layouts@execution@component-layout@vs-fs-array-dvec3
cc: mesa-stable
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18444>
(cherry picked from commit a0f6fecc6afeccc8e149ab31769df8b5225faa16)
The change didn't make any sense. `s` will always be
`NV50_SHADER_STAGE_COMPUTE`, because it's used to loop over all shader
stages. And the TSC cache on the compute side is already flushed in
`nv50_compute_validate_samplers`.
Fixes spurious `CACHE_ERROR` dmesg messages.
Fixes: ba6ba8c990 ("nv50: adapt texture and constbuf paths for compute shaders")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18382>
(cherry picked from commit 54709efd5e34a06ef8d518fe7635f6ae345bef40)
When an OP_UNION def takes part in a vector source e.g. for a tex
instruction we failed to clean up the OP_UNION instruction as rep() points
towards the coalesced value instead.
This fixes a regression on nv50 moving to NIR, but also potentially issues
with nvc0.
The main reason this is common in nv50 is, that we lower OP_SLCT to a set,
predicated movs and a union.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6406
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7117
Cc: mesa-stable
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18377>
(cherry picked from commit b23b94fbc9201368398823ccdc633cf1fa60127c)
The kernel driver has a range of valid priority values that can
be supplied to it, submitting any priority value outside these
bounds will result in `-EINVAL`. To avoid this, the priority
value is now clamped to the range that the kernel supports.
Fixes: 0c6fbfca0c91ef012e8ab767a317c07f1f6dc5e6
Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18389>
(cherry picked from commit c82249aa6891e43398cc8d62d552869495292b31)
Some claims of corruption, modifier-less Mesa already doesn't do
it. Since these modifiers have no purpose besides being displayed
lets just disable in Mesa.
Cc: mesa-stable
Tested-by: Michel Dänzer <mdaenzer@redhat.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18140>
(cherry picked from commit ae7532e0cce8b5987335aadda712f1dc3f8ad5e3)
Going to be a bad time if they disagree, which is bound to happen
sometimes. Not asserting and stuff tends to be a better experience
than crashing.
Cc: mesa-stable
Tested-by: Michel Dänzer <mdaenzer@redhat.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18140>
(cherry picked from commit af4b656817700ddcd4a26fdbf19a7b6dbbcd7738)
This fixes a buffer corruption bug with glMultiDrawElementsEXT(): the
offset for the source index buffer is reset for each draw_multi slot,
copying only the first `dr` values to each slot's index buffer.
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18189>
(cherry picked from commit b830091cb6c0414f3a875d48e5c625101327e02f)
If a glMultiDrawElementsEXT() call doesn't fit into a single slot, the
same pipe_resource pointer is copied into all following slots, the
completion of each will decrement the reference counter; however, it
was never incremented for all but the first slot.
This fixes a use-after-free bug with glMultiDrawElementsEXT().
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18189>
(cherry picked from commit 0a0fb7cbc63d66977c148c3f5fd86de8e879f1ab)
The only reason why we didn't notice before is because ANV always
re-emits all scissors and viewports if the count changes.
Fixes: fcedb1250b ("vulkan: Add a common data structure for dynamic states")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18160>
(cherry picked from commit 6ffbb1abdb26faf341383cbc6bd337a04151711e)
If an instruction has multiple destinations and *any* of them are needed by
helper invocations, we should keep helper invocations alive. This is a bug fix.
Consider the GLSL:
first = texture(sampler, ...);
float res = texture(sampler, vec2(first.y)).x + first.x;
Corresponding to the IR:
first = ...
x, y, z, w = SPLIT first
second = TEX y, y
x', y', z', w' = SPLIT second
FADD res, x, x'
Here, x is not required by helper invocations (the coordinates to TEX) while y
is required. If we only look at only the first destinations, we incorrectly
decide that first is not required and fail to set the .skip bit, leading to
incorrect results.
Fixes: 5febeae58e ("pan/bi: Emit collect and split")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
(cherry picked from commit d0aaf52602341705a915d85fe295341de0744bd2)
...with dual source blending. Fixes shaders/dolphin/smg.1.shader_test
There are more IR sources than Valhall machine sources here.
Fixes: b48933d641 ("pan/va: Include BLEND for va_swap_12")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
(cherry picked from commit b5a6375f546c8a74fb81a70db6819f0281e3292e)
The GLSL code sequence:
texture2D(tex0, u_coords) + texture2D(tex1, u_coords)
will be optimized to
TEXC_DUAL tex0/tex1, u_coords, #texture_descriptor
If this optimization happens after lowering FAU, the resulting TEXC instruction
is unschedulable: both the uniform and the constant descriptor fight for the
same FAU slot.
However, if this optimization happens before lowering FAU, then the FAU lowering
will move the descriptor into a register, complicating the dual texturing fixup
in RA.
To fix this interaction, fuse dual texturing before lowering FAU and keep
texture descriptors as constants when lowering FAU of TEXC.
Fixes scheduling failure in piglit drawoverhead -test 3 with uniform reordering.
Fixes: a4d3a29647 ("pan/bi: Enable dual texture fusing pass")
Fixes: 6b2eda6b72 ("pan/bi: Reorder pushed uniforms to avoid moves")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18378>
(cherry picked from commit c5b9a01feaa6e46827a8af003767d561d5c22fec)
Tests, softpipe or AMD drivers don't depend on it directly
Fixes: 3955dd07 ("meson/gallium: Add an option to not use LLVM for gallium draw module")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6817
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17675>
(cherry picked from commit f23dbcd6420188ba447e3fc50cf316dc20fb4114)
this is not valid for vertex inputs or fragment outputs
cc: mesa-stable
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18365>
(cherry picked from commit da1a3ed2ead1633b9ba7170b3e1fb4c08fa8dc2b)
these are supposed to be for dmabuf handling, so checking for mutable
swapchain is both pointless and wrong
Fixes: 28ee911ad67 ("zink: handle mutable swapchain images with dmabuf")
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18358>
(cherry picked from commit cd00a36d479ba0bda2a86f7d822c0dc4f93bcbb0)
This reverts commit 6f25d45877, replacing it
with GLSL_PRECISION_MEDIUM. The previous commit ended up not being the
right approach, as it affected only nir vars for spirv phis and not other
nir vars, and we want a tool that does both. The new
nir_lower_mediump_vars pass can do that for you.
No fossil-db change for my angle fossils run on radv.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18259>
(cherry picked from commit e1588cdf9ecc26c51ae0df3a380e1ac781e41941)
This is a counterpart to the previous commit. When we have multiple
depth attachments, in the secondary we currently don't disable LRZ and
so we may need a valid LRZ fast-clear base.
Fixes: 4b5f0d98 ("tu: Overhaul LRZ, implement on-GPU dir tracking and LRZ fast-clear")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18369>
(cherry picked from commit f640661e541bb2b300b1432f5e6a6e575353c3f5)
In
dEQP-VK.renderpass.dedicated_allocation.attachment_allocation.input_output.94
we have the following:
- There is more than one subpass, but only one depth attachment.
- The first subpass doesn't use depth.
- The subpass that does use depth has a draw call in a secondary.
We wouldn't hit the case where there's more than one depth attachment,
but because tu_begin_resumed_renderpass() only looked at the first
subpass it wouldn't find the depth attachment and would leave LRZ
invalid and thus a NULL LRZ fast-clear base. Then
tu_begin_secondary_cmdbuf() would leave LRZ enabled and the draw would
have LRZ enabled, leading to a hang.
Fix this by making tu_begin_resumed_renderpass() match
tu_begin_renderpass() with how it finds the depth attachment.
Fixes: 4b5f0d98 ("tu: Overhaul LRZ, implement on-GPU dir tracking and LRZ fast-clear")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18369>
(cherry picked from commit bf09a5881b7d4fb7b11a7cc92513807ab00a7a47)
It supports VS, TES and GS.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18345>
(cherry picked from commit 047738daa75ecdf3be4e4f648fd0fa25474f7026)
When a vec4 register only uses constant value of ignore
swizzles then emit zero as register ID.
Optimizing the register use in instructions that support this type
of swizzle may lead to the situation that the RA doesn't see the
register ID, because it is actually irreleant, in this case return
zero as register ID to avoid that the assembler uselessly reports
a high requirement for registers based on a stale register ID.
Fixes: 79ca456b48
r600/sfn: rewrite NIR backend
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18343>
(cherry picked from commit ed294e08635c4fea4f9a6afcf253691458c415e2)
Fixes misrendering on front with mesa demos
Cc: mesa-stable
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18360>
(cherry picked from commit 91dcadf95690c658b34b20cf5dbf77f79c1cf297)
The third source exists logically but not architecturally. We still need to
print it. Caught by the assertion.
Fixes: 0ee24c46e0 ("pan/mdg: Only print 2 sources for ALU")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18338>
(cherry picked from commit 6fed6161876681920b0d2c59cb7413d7c43fda45)
Otherwise the transfer from the host might not be finished
when we try to read the data.
v2: always wait before readback, but also keep the wait after
a possible readback, Itherwise TF fails in the CI.
Fixes: e87186fc67
virgl: add virgl_resource_transfer_prepare
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18243>
(cherry picked from commit 6e2b01e5b806b3b0ec9df896f4ddc842a54f4fa6)
This is to make vtest happy.
Fixes: 9c5a7ffbd8a ("venus: fix external memory ext filtering")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18331>
(cherry picked from commit 0e0e5d1f204fc7c10a8686fe77cc1c9c0fef54f5)
We've already allocated the pipe resource, so we ought to free it
before returning.
Fixes: d8a38edc48 ("crocus: fail resource allocation properly.")
Fixes: f3630548f1 ("crocus: initial gallium driver for Intel gfx 4-7")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18311>
(cherry picked from commit 6c7916b7f665db7f5af929ed0f64206d70fccc56)
This was effectively removed in bb3545a6, but the field wasn't deleted,
leaving it there to troll people. screen->aperture_bytes is 0? What?
Fixes: bb3545a6ee ("intel: Store the aperture size in devinfo.")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Mark Janes markjanes@swizzler.org
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18311>
(cherry picked from commit 6a1f7e623f776a8b4c0d4f43736469143b4f37ef)
With this helgrind doesn't report any races in this code.
Cc: mesa-stable
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10752>
(cherry picked from commit 35d28251d1328d258da74756ef8eb2cc4ea80eba)
At the moment the context uses the screens object, but in order to fix
threading without having to lock too much we will have to allocate those
objects per context later.
Cc: mesa-stable
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10752>
(cherry picked from commit 607a9e1fd23afcc0095b029b71b2cb89c537f9fb)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17991>
(cherry picked from commit 290df958703a30cb6d69aff2f8899a06a098ce20)
If task redistribution is enabled, then some mesh shaders read
garbage from task payload.
It may be a hardware bug, or it may be our bug. Who knows :(
This change will probably negatively affect performance of task
shader-enabled workloads on multi-slice GPUs, because mesh shaders
will be executed only on the slice where task shader was spawned.
Fixes: ef04caea9b ("anv: Implement Mesh Shading pipeline")
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16197>
(cherry picked from commit 4eaecd79657f0cd99f6536fd55a7a14958d6624b)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: 3fba5bb9cc ("aco: implement 16-bit vertex fetches with tbuffer_load_format_d16_*")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18225>
(cherry picked from commit 32608444484edaa68223dbd738f3a7850d5bd924)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: b366fef091 ("radv: optimize the number of loaded components for VS inputs in NIR")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18225>
(cherry picked from commit 9ae13a9bd39e6b71ae0748d1cca598dce13f6306)
These probably don't work.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18225>
(cherry picked from commit 82f9e40851cbff803f2550f37f1d2b863fbc6d88)
The following sequence would be broken if we don't re-emit viewports.
vkCmdSetViewport()
VkCmdBindPipeline(negative_one_to_one = false)
vkCmdDraw()
VkCmdBindPipeline(negative_one_to_one = true)
vkCmdDraw()
Found by inspection.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18245>
(cherry picked from commit 64045fcf7ce3fed6bbc08441cb16c3ca5c76c795)
It can be useful not just to create functions, but also being able to
call them. This adds the spirv_builder-helper for this.
Cc: mesa-stable
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18244>
(cherry picked from commit 47d67912bdf27aa11bcd097142d98016a4ca9874)
This type will be reused later on, so let's have the name describe what
is *is*, not what it's *used for*.
Cc: mesa-stable
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18244>
(cherry picked from commit 41dfed6e1235de20eb55f9c445ffe36673cea5b3)
Ref: bspec 53655
Fixes: d399c3e861 ("intel/dev: Add device info for ADL-S")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17569>
(cherry picked from commit f4c44444adfb93740363ba6f424ab5f9e673b470)
Ref: bspec 53655
Fixes: d399c3e861 ("intel/dev: Add device info for ADL-S")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17569>
(cherry picked from commit 6ca37aabfbb04a066d3d440aad3181c087fe3c6d)
When NIR is not explicitely enabled we still support TGSI.
Fixes: 33765aa92a
r600/sfn: Enable NIR for pre RG hardware
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
(cherry picked from commit 90f99369aeccf2a52495319930ff23b8ffa2a691)
When SSBO instructions use constant address values the address loading
is immediately ready, scheduling the address loads early increases
the register pressure, so force a new instruction block to work around
this problem.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6975
Fixes: 79ca456b48
r600/sfn: rewrite NIR backend
v2: do handling in shader block to be thread save (hinted to by Filip)
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
(cherry picked from commit c81fe5b235c0204e9f77d13411004a3307aa6301)
Limit the number of tested instructions and the number of
ready instructions that might be taken into account.
This reduces the time needed to run the scheduler significantly.
Fixes: 79ca456b48
r600/sfn: rewrite NIR backend
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
(cherry picked from commit 1f5dccb76057666ff810d889a38e057b078f2448)
Export instructions allow burst writes, so it makes send to try
to allocate consecutive registers, but for ring writes we don't
schedule the outputs correctly to exploit this, so for now
don't mark these instructions as export to let the RA restart
picking colors.
When the scheduler starts to emit the ring writes in the right order
to allow for bust writes we might revisit this.
This fixes
spec@glsl-1.50@execution@variable-indexing@gs-output-array-vec4-index-wr
Fixes: 79ca456b48
r600/sfn: rewrite NIR backend
Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6975
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
(cherry picked from commit fd71cd0b6a068ce4f0187b26d4527c3e1b6dee86)
Fixes: 069f3869ac3a140898224c8c37d5b3b6349361a4
r600/sfn: Fix color outputs when color0 writes all
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
(cherry picked from commit 3a0f085837bd605dd5fbd52e4cf934995193e689)
Linear PE has already shown to have some rough corner cases in the hardware
and also has performance implications. Add a debug option to allow to disable
the feature, so users can more easily check if some issue is caused by this
feature.
CC: mesa-stable #22.2
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18232>
(cherry picked from commit 43eb5e777e4b64fe1b143822ae8aaf709eaad42f)
When linear rendering is used together with TS, the color tiles must be fully
contained in a single row of pixels. When wrapping around to the next row
TS gets confused and records wrong tile status information, leading to visual
corruption when the surface is resolved/decompressed.
The corruption can be fixed by increasing the stride alignment for linear
render targets, but that would break some existing use-cases, as some display
engines used together with Vivante GPUs currently don't support strides that
don't match the horizontal display resolution.
For now only enable linear PE rendering when the surface is properly aligned
already. This allows to use the optimization in a lot of common use-cases, but
falls back to the proven tiled rendering with subsequent resolve into linear
for the problematic cases.
CC: mesa-stable #22.2
Fixes: 53445284a4 ("etnaviv: add linear PE support")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18232>
(cherry picked from commit ea8fc9592c16ce137d58a27be8f30f530efcc524)
Conflicts:
src/gallium/drivers/etnaviv/etnaviv_surface.c
The decision whether to use fast clear aka TS currently checks for two
feature bits: FAST_CEAR and MC20. We check for MC20, as TS on MC1.0 bypasses
the memory offset and we don't have any way to fixup the GPU address to
account for that. It could be done with some support of the kernel driver,
but then GPUs with MC1.0 are very rare to find these days, so not sure if we
are ever going to bother with that.
Instead of checking two separate feature bits to determine if TS can be used,
mask out the FAST_CLEAR bit from the features when MC20 isn't present. This
way we only have to check for a single feature bit.
CC: mesa-stable #22.2
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18232>
(cherry picked from commit 09953d7b75524022b5f1e9bfa8264adcfd8691a1)
If we have modifiers, we can use those to convey the tiling of exported
resources. If we have the deprecated i915 GET/SET_TILING uAPI, we can
use that to convey the tiling.
If we have neither, then we have to fall back to linear.
Fixes: e658835436 ("iris/bufmgr: Do not use map_gtt or use set/get_tiling on DG1")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6938
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18240>
(cherry picked from commit 71ace23fa7ccb27eb4455e38f9254bac5c5b7f86)
Sync fd fence export implies a payload reset operation, and application
can immediately do another submission with the same fence after export.
Concurrent use of the same feedback slot is incorrect. Keeping a list of
feedback slots for sync_fd external fence is a bit over designed given
those fences are usually not checked or waited by the app, but will hand
off the ownership via sync fd to an external client.
Fixes: d7f2e6c8d0 ("venus: add fence feedback")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
(cherry picked from commit 5457f4c0a497484eca1ecf91af8114f95435c023)
ARB_sparse_buffer does not require sparse buffer size to be
page aligned. So we need to align it before VM ops as KMD
will check whether it's aligned and return EINVAL if not.
Fixes: 667da4eaed ("winsys/amdgpu: sparse buffer creation / destruction / commitment")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7104
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18206>
(cherry picked from commit 4fc9125ca28bf0b721a18fe8608c693d794d5cab)
These would only have worked in GCC and Clang, which so far wasn't an
issue, but let's clean it up anyway.
Cc: mesa-stable
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18190>
(cherry picked from commit c66622de3af4efc3717131c55a54b408bc7faade)
With the following SEND instruction :
send(1) nullUD nullUD g0UD 0x4200c504 a0.1<0>UD
This instruction although valid but somewhat nonsensical (SEND message
to write at offset contained in NULL register), triggers an error in
the validator.
The restriction is that we cannot have overlapping sources. The
validator not checking the type of register incorrectly thinks that
the null register (offset 0) is the same as g0.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17555>
(cherry picked from commit 3c6fa2703dad46a5026cc3993224feff0f106745)
tcs_out_lds_offsets is not sure to be 16 byte aligned, it's
calculated like this:
num_patches * patch_vertices * lshs_vertex_stride
num_patches and patch_vertices are not sure to be any value aligned,
lshs_vertex_stride is added one extra dword, so it's only 4 byte
aligned.
This may cause problem even before we switch to nir tess output
lower when write tess factor before read tail of input. But it's
more likely to cause problem after we switch to nir tess output
lower because the main body won't eliminate the low 4bit offset
but epilog will, so they use different offset to read/write tess
factor.
Fixes: 7598bfd768 ("radeonsi: replace llvm tcs output with nir lower pass")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7083
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18174>
(cherry picked from commit ff7c59672fd59c94792b26f7131eb86e57d4b8f4)
For AMD we kinda have some modifiers with a max size ... (Which is
really a compositor/kms issue, but getting them to try kinda falls
into the unsolved "how to allocate/what pitch to use" bucket, so
we solve it on the allocating side)
Cc: mesa-stable
Tested-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Joshua Ashton <joshua@froggi.es>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18139>
(cherry picked from commit bb2a44432400f6c7613905eceb14c6544687ed1f)
In a99e85db9e, we added a dup into iris_screen_create(). Apparently
some android code paths must be hitting iris_screen_create() without
calling iris_drm_screen_create(). After a99e85db9e, the code paths
that do hit iris_drm_screen_create() will now dup the fd twice, but
iris_screen_destroy() will only close 1 of these fds.
Fixes: a99e85db9e ("iris:Duplicate DRM fd internally instead of reuse.")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18020>
(cherry picked from commit e9f40e42de6b47e036d603296ecb5facb384eb0c)
We did not handle the operation with data size < 4. It works fine on
all other messages (global/shared). The initial commit was just too
restrictive.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 1e242785c3 ("intel/fs: Implement load/store_scratch on XeHP")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16964>
(cherry picked from commit 3c78e94ff345fda6314e7644873d960c0ee97dc5)
The selection of the internal opcode to deal with load_scratch is
incorrect.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c643979228 ("intel/fs: Choose memory message type based on bit size")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16964>
(cherry picked from commit 46a13404c07acdb0412121a6ff55fdbcd5bfea5c)
Even with dynamic rendering, you have to bind both aspects of the image
if the image contains both depth and stencil. One day, we may see this
restriction lifted but that will require deeper driver surgery into the
way we handle depth/stencil layouts.
Fixes: 42db590006 ("radv: convert the meta blit 2d path to dynamic rendering")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18084>
(cherry picked from commit 76b8b854a514bc515ddba47f4fbbf6ea80bcf0f2)
When setting -Dshader-cache=disabled the build fails due
no member named 'disk_cache' in 'struct anv_physical_device'
Signed-off-by: sjfricke <spencerfricke@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Fixes: 7f1e8230 ("anv: Switch to the new common pipeline cache")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18181>
(cherry picked from commit c49e328e4f41d4a2503045a0bb8bfaf65d4cde61)
We use/delete this fence unconditionally, but it was initialized only
when screen->precompile is set. Move the util_queue_fence_init call
to the iris_create_uncompiled_shader to initialize it always.
Fixes: 42c34e1a ("iris: Enable threaded shader compilation")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7074
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Tested-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18182>
(cherry picked from commit 0a0aa24b33c4a3d18426f09674ff67c23e71cfd2)
First we should only support the extension if we can support reporting
on all the heaps.
Second we should not run any query code if the extension is not
supported.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: fae88d8791 ("anv: make use of the new smallbar uAPI")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18153>
(cherry picked from commit b8c472c111ee1e5a7feb45a9da81e5f73145b6fb)
With VK_FORMAT_B10G11R11_UFLOAT_PACK32 in particular, we're seeing
applications create image views with swizzle = R,G,B,0
But since the format has no alpha channel, the swizzle value for it
does not matter for the equivalence we're trying to verify.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: a9edc268b9 ("anv: validate image view lowered storage formats for storage")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18081>
(cherry picked from commit 4ab38112f36ec25afe98a1636909bb8bde4ad7a1)
this doesn't need fixing
Fixes: 3a47576687 ("zink: add a compiler pass to match up tex op dest types")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18196>
(cherry picked from commit 585fa6bf406e064877baf4b2b106e116bee21c6b)
If this happens then "after" is NULL, so we can't use it to get the
block, and the instruction is never moved at the end so we have to
create the split instructions before creating the collect to make sure
they are in the right order.
This happens when reloading a complex vector value that has been
coalesced at the end of a basic block, which apparently hasn't happened
until a gfxbench5 shader on zink hit this case. This fixes it.
Closes: #7054
Fixes: 613eaac7b5 ("ir3: Initial support for spilling non-shared registers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18082>
(cherry picked from commit dcfbb60392fce468eb2bc2513c3b1ba5dfc1e62e)
Fixes: bbdf7e45b1 ("wsi/x11: Hook up KHR_incremental_present")
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18177>
(cherry picked from commit 20fba14f2cb34060ecae42634bfe8c266f56952f)
When unpacking the texture sample result ensure it is moved to the
proper expected dest register.
This fixes incorrect texturing in Chromium using PixiJS framework.
CC: mesa-stable
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18122>
(cherry picked from commit 4ba21c3e8cef567f0c39460dd3f1d20f754c3c6f)
Clause scheduler edition of db2bdc1dc3 ("pan/bi: Require ATEST coverage mask
input in R60"). ATEST wants to read r60, which can't work if its input isn't
even in a register.
When per-sample shading isn't in use, prevents regressions in:
KHR-GLES31.core.sample_variables.mask.*
These tests previously passed because per-sample shading was forced. It's
not clear whether the bug addressed in this patch is possible to hit "in the
wild", i.e. without the optimizations in this series that allow us to use
per-pixel shading in more cases.
No shader-db changes.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17841>
(cherry picked from commit 394e1f5862a5cd537f60c01ed75dc698e112da58)
Fixes flaking in
dEQP-GLES31.functional.image_load_store.cube.qualifiers.volatile_r32i due to
image reads being moved past a BARRIER.
To make this more robust/optimal, we probably need scheduling information
(coherent/volatile/etc) added to instructions like ACO does. That's left for a
future extension, for now I just want the test to stop flaking.
Fixes: 569e5dc745 ("pan/bi: Schedule for pressure pre-RA")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17841>
(cherry picked from commit e12a9ce8d691a311cd37eecbdeadb30400adeb95)
If we don't recognize the model, dev->model will be NULL. In that case, we can't
dereference dev->model to get the tilebuffer size. If we do, we'll segfault,
instead of gracefully refusing to probe and loading the swrast instead.
Fixes: 96d65b47c7 ("panfrost: Use implementation-specific tile size")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18115>
(cherry picked from commit 93f69e0452e0cdb2cf1faecb613f54220b798f79)
Additionally add support for PIPE_CAP_CLEAR_SCISSORED since we are already
touching the scissor state.
Fixes various gnome-shell rendering artifacts.
v2: Remove NEW_SCISSOR as clear now updates scissor registers explicitly
v3: Reset scissor_off state since its not off now after clear
Cc: mesa-stable
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18137>
(cherry picked from commit 7908cb895e2dea8cff91cecb53457a099dc96b07)
Alpha-to-coverage acts like discard and happens after FS ends,
so like with discard LRZ write should be disabled.
With discard we don't know at the moment of binning whether
fragment would be not discarded, so we cannot write its depth to LRZ.
Cc: mesa-stable
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18102>
(cherry picked from commit 09676b5817339cb7653fb23c9c5341b7f95392bb)
SPIR-V shift ops unlike NIR have undefined behavior if shift count
larger than or equalt to bitwidth.
This means that true translation of NIR ishl/ishr/ushr to SPIR-V requires
masking like that done in gallivm.
This was seen in the case of soft fp64 in cts case
KHR-GL46.gpu_shader_fp64.builtin.ceil_double.
Cc: mesa-stable
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18074>
(cherry picked from commit b386df918fd3274b3814c639ad7297f5b07cc48a)
Loading indirectly from a register that was just written to
doesn't work on R600 class hardware, so add a NOP group with
the address register load being emitted in the t-slot. to make
sure that the register write was finished.
Fixes: 33765aa92a
r600/sfn: Enable NIR for pre RG hardware
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18130>
(cherry picked from commit 404d95ca49af48e06d786e765091dc8d3a531b3c)
On R600 and R700 class hardware the input declaration order maps
directly to the register the hardware writes the inputs to, so
make all interpolated inputs come first, and only then emit the
system values like POS or FACE.
Related: #7035
Fixes: 33765aa92a
r600/sfn: Enable NIR for pre RG hardware
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18130>
(cherry picked from commit f6582027dc839f9f886854b3a6e581d4c41ac5a7)
The old code does the same for R600.
Fixes: 33765aa92a
r600/sfn: Enable NIR for pre RG hardware
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18130>
(cherry picked from commit 34b9e3e44c1939e9773bb26a2cac2871b2579f03)
This reverts commit 23e5b910c5.
Reason for revert:
It's causing the regression for H264 transcoding. We will Enable EFC
once we verify all corner cases and as of now disabling
Signed-off-by: Ikshwaku Chauhan <ikshwaku.chauhan@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17869>
(cherry picked from commit ddc8ab9e4322bed0ce7e47c986d54c852fb56852)
textureGatherOffsets always takes a highp array of constants. As
per the discussion in [1] trying to lower the precision results in segfault
later on in the compiler as textureGatherOffsets will end up being passed
a temp when its expecting a constant as required by the spec.
[1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16547#note_1393704
Fixes: b83f4b9fa2 ("glsl: Add an IR lowering pass to convert mediump operations to 16-bit")
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18101>
(cherry picked from commit 87940c31939f45f94c7af02c6c280773f917ff25)
Android CDD has additional requirements that must be met in order to
enable 1.1+:
- samplerYcbcrConversion
- VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
- VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
- VK_ANDROID_external_memory_android_hardware_buffer >= v2
Requirements are checked by:
android.graphics.cts.VulkanFeaturesTest#testVulkan1_1Requirements CTS
Fixes: 2686c5419d ("v3dv: add Android support")
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18047>
(cherry picked from commit b17ea48f91d8fa09668ac61a034013f4a79dc6be)
vk_common_AcquireImageANDROID and vk_common_QueueSignalReleaseImageANDROID
expect sync_fd import/export to be enabled, otherwise they crashes
while trying to ImportSemaphoreFdKHR() / GetSemaphoreFdKHR().
Features was disabled on Linux to skip sync_fd CTS tests, which is using
late vkEvent signalling which causes deadlock / dEQP timeout on v3dv.
One of the options was implementing blocking v3dv-specific
AcquireImageANDROID / QueueSignalReleaseImageANDROID to avoid importing
/ exporting sync_fd, but since these features are also required by CDD
for Vulkan 1.1 and above, it was decided to enable the extensions for
Android in exchange of a few failed dEQP tests (which should not cause
any issues in non-dEQP scenarious).
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6977
Fixes: 316728a55b ("v3dv: Switch to the common submit framework")
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18047>
(cherry picked from commit 5e32e8c962da237772c78df7654897acfd4787f7)
Right now even the simplest mesh test (func.mesh.basic.mesh from crucible) fails like this:
ASSERT: Scalar MESH validation failed!
load_payload(16) vgrf11+0.0:F, vgrf8:D
../../src/intel/compiler/brw_fs_validate.cpp:61: inst->dst.offset / REG_SIZE + regs_written(inst) <= alloc.sizes[inst->dst.nr]
Because we try to load 8 regs with LOAD_PAYLOAD in SIMD16 mode.
Fixes: 349a040f68 ("intel/fs: Make logical URB write instructions more like other logical instructions")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18075>
(cherry picked from commit 446eeccb1c95f65511aa5ffdfd7f6ce23b1ea83f)
If we have VRAM we're not exactly a unified memory architecture, are we?
Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18123>
(cherry picked from commit 1ef43ea3c4ec8b29e45ec6e052e37ce3991b77b6)
get_ssa_temp's and NIR's bit size can differ for scalar sources.
This causes broken packing of the MIMG operands with A16/G16.
Fixes: f5f73db846 ("aco: Support 16bit sources for texture ops.")
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18008>
(cherry picked from commit 2dd641119fa545528eefdcd50e0d690c7f592bcb)
The lp_rasterizer is shared across contexts, and lp_rast_fence called
without holding rast_mutex could race with rast_mutex being replaced and
unref'd on a different thread.
Fixes: a680fd078c ("llvmpipe: make last_fence a screen/rast object not a context one.")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18116>
(cherry picked from commit f228c26520dcfdc2d600ba78c51796ef2a4a31fd)
Since PIPE_CAP_TGSI_TEXCOORD is now enabled, texcoord is now declared
as TGSI_SEMANTIC_TEXCOORD instead of TGSI_SEMANTIC_GENERIC.
Fixes assert running REDTurbineDEMO with MTL Renderer when the guest needs to
fallback to swtnl for line stipple.
Fixes: e73443b7a5 ("svga: enable PIPE_CAP_TGSI_TEXCOORD for vgpu10 and up")
Reviewed-by: Martin Krastev <krastevm@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18113>
(cherry picked from commit 854e8797ac3b010c980810fa5d0638a872df3aa0)
Alpha-to-coverage acts like discard and happens after FS ends,
so like with discard LRZ write should be disabled.
With discard we don't know at the moment of binning whether
fragment would be not discarded, so we cannot write its depth to LRZ.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6876
Cc: mesa-stable
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18083>
(cherry picked from commit c45fded26b8c858d1974a8b4017200b1cbe92d31)
Drivers don't use this, so avoid the assert it could have.
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18042>
(cherry picked from commit ad274ba8893a31477ca946dfb670d29f8643b01d)
When primitive is points, EndPrimitive can't be used to count
primitive. Need to use vertex count instead. And it's also not
needed to do vertex per primitive count and overwrite incomplete
primitive work for points.
Fixes: 2be99012e9 ("nir: Add ability to count emitted GS primitives.")
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17805>
(cherry picked from commit 84956286a8d30790dda7568043ec2b546904fdf2)
TEX instrutions can't write xyz and w to separate registers so we
need to create variables from them first, otherwise we can create
two variables from ALU writing the same register xyz and w in other
branch (this usually works when TEX is not present as the xyz and
w can read/write from different registers).
This fixes regalloc because the variables are later used as a
graph nodes.
The variable order should not matter but it slightly does (leading
to approx 0.3% shader-db temps increase as compared to previous
state), so just sort the variables list afterwards to be as close
to the previous behavior as possible and prevent the regression.
CC: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6936
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17987>
(cherry picked from commit 88fd397c741c0e1fe0d851fbc566925078df6013)
For post-transformed vertices, w = 0 is similar to
w = 1. Replace the value to fix rcp(w).
It is common for apps to pass w = 0 for
position_t.
cc: mesa-stable
Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18021>
(cherry picked from commit b5df20568a6e60056211b634efa3bea4758f18e9)
Due to the driver live shader cache, it's possible
two different d3d9 shaders get the same cso.
As it's disallowed to destroy a shader cso being
bound, nine checks for this scenario. However it
was not taking into account the cso might be from
a different shader.
cc: mesa-stable
Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18021>
(cherry picked from commit 93da6e9f34226549b4eb8726383fb54c584a9e15)
Invalidating all state groups is not sufficient, as
some states check for actual changes.
The correct way is to invalidate the
commit mask.
Found with a wine test.
cc: mesa-stable
Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18021>
(cherry picked from commit 4c65ccab6d48abe7be650ee7b9f3b72a70609a9a)
The previous code was incorrectly checking the previous
value of alphatestenable.
In addition, remove an optimization that cannot hit (as we
filter out redundant state settings).
cc: mesa-stable
Fixes: 1272640d5 ("st/nine: Fix alpha to coverage states")
Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18021>
(cherry picked from commit 4f953ad51299a744aa74b7667debd8a8245685f5)
Fixes a crash in a ffxi trace, which draws out of bounds.
This was previously resulting in trying to fill a buffer
resource not big enough.
cc: mesa-stable
Fixes: 380c2bf ("st/nine: Optimize dynamic systemmem buffers")
Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18021>
(cherry picked from commit e5124e83ba1f9a7c86a3b1b8d38e7c71cd481f88)
Without this it may crash running wine tests.
According to the test themselves, the correct
behaviour is a bit more complicated, but
that's a first step.
cc: mesa-stable
Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18021>
(cherry picked from commit b74febffe6e97938130dfd405ae1678539eafcfe)
Fixes: e342081c ("util/format: Assert that formats are valid")
Closes#7020
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18024>
(cherry picked from commit 075b72ea069863021c51235d46c4c89c859d698b)
In create_rt_shader, we were setting group_idx to the stage index before.
Fixes the following tests:
dEQP-VK.ray_query.builtin.instancecustomindex.miss.aabbs
dEQP-VK.ray_query.builtin.objectrayorigin.miss.triangles
Fixes: c39ccce ("radv/rt: use stage ID as handle for general and closestHit shaders")
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17936>
(cherry picked from commit 2d39227a90440e5b911f5ac6c0fb5ac04c433565)
It's already correctly cleaned in radv_device_init_meta().
This fixes a recent regression with
dEQP-VK.api.device_init.create_instance_device_intentional_alloc_fail.
Fixes: 1a95d43e55 ("radv: Simplify the meta init fail path")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17952>
(cherry picked from commit 37dfa4e3f3c669af16a53aa6c0401989a26099a1)
Conflicts:
src/amd/ci/radv-hawaii-aco-fails.txt
src/amd/ci/radv-oland-aco-fails.txt
Stable:
- remove CI files that don't exist in 22.2
these are required framebuffer formats in certain versions of GL,
so don't create a texture that can't later be bound to a framebuffer
see also spec@!opengl 3.0@required-texture-attachment-formats
cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17687>
(cherry picked from commit 28d033b34fe3c52f4720235449a0a1fd5fe683b0)
neither of these have a real alpha channel, so reuse the xrgb blend
clamping here to ensure the "right" alpha value is used
cc: mesa-stable
fixes:
spec@arb_texture_float@fbo-blending-formats
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17687>
(cherry picked from commit 4f28e2827c9ccc26dc608a870209b4deab7b5882)
Currently the sb.MOCS is being reset to zero after struct init.
Signed-off-by: sjfricke <spencerfricke@gmail.com>
Fixes: c27fcb1d3b ("isl: Fill in MOCS for NULL depth, stencil, and HiZ buffers.")
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17985>
(cherry picked from commit 861167f41d17e1c8d114cb511a817308491327c1)
The nir shader memory is freed in nir_to_tgsi(), but the already
freed shader info is referenced later when create compute state.
To avoid referencing the freed memory, copy the shader info first before
calling nir_to_tgsi.
Fixes vmx crash running aztec on SVGA driver.
Fixes: 580f1ac473 ("nir: Extract shader_info->cs.shared_size out of union")
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17999>
(cherry picked from commit 4393be8291ff3f39ff37a61133b6e5b0fa3e9698)
Fixes: 3415bf02 ("egl: Add a basic Windows driver")
Suggested-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Sidney Just <justsid@x-plane.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12964>
(cherry picked from commit 17eda68df3b88e5ed02cf180411491b28be1e6d5)
Fixes: 3415bf02 ("egl: Add a basic Windows driver")
Suggested-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Sidney Just <justsid@x-plane.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Tested-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12964>
(cherry picked from commit efd2ae6c0c87b8eca3bf0a476a008a16c00c51a2)
this is the "default" size that's expected
cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17874>
(cherry picked from commit b7eda568a4acf8b3d551e22b6ef72689663f9550)
Without this, we might end up trying to use VK_FORMAT_D32_SFLOAT_S8_UINT
even when it's not supported...
Cc: mesa-stable
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17953>
(cherry picked from commit 3340dea1941885e85087bd35b6261dfee8148722)
This will be reused in the following commit.
Cc: mesa-stable
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17953>
(cherry picked from commit 71c1ca3c67bc64ba1d74841fa664b0ee0e045c11)
With the switch to common dynamic state tracking, something got lost
that made the scissors not always be emitted when they are not dynamic
and the pipeline is marked dirty.
Since both viewport and scissors make use of each other to calculate
their values, just stick the scissor emit in the same if block as
viewport for now.
I'd rather have them decoupled, and at least the Vulkan CTS didn't
complain when I tried it, but I don't know what other effects that
may have, especially when it comes to the guardband.
Fixes a bunch of tests under
dEQP-VK.pipeline.*.multisample.misc.*
Fixes: 7d25c04236 ("anv: Switch to using common dynamic state tracking")
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17964>
(cherry picked from commit fbd41337354326354739042368989535d79f1640)
For external image imports, we'd lose the mutable image format list,
causing turnip to get angry that we try to do UBWC despite not having a
UBWC-compatible format list.
Cc: mesa-stable
Fixes: 28ee911ad671 ("zink: handle mutable swapchain images with dmabuf")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17900>
(cherry picked from commit 8dda0a01bb3ea5a618a73ea4e506cb61e68e6d0c)
The driver should still gather XFB info even if all XFB outputs are
dead, otherwise the pipeline can't find the streamout shader.
RADV should use vk_spirv_to_nir() at some point to reduce code
duplication during SPIRV->NIR compilation.
This fixes new dEQP-VK.transform_feedback.simple.*.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17939>
(cherry picked from commit e95531e101f0ba61d28195fe38414e411bf418b3)
We can't invalidate CCU if there is any dirty data that hasn't been
flushed yet. In the case where we clear depth, we know that the depth
attachment itself isn't dirty but there may be dirty data from other
renderpasses. Therefore we need to flush before invalidating depth.
Fixes: 487aa80 ("tu: Rewrite flushing to use barriers")
Closes: #6987
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17940>
(cherry picked from commit a7e64ab63c5aa0b5c2079badc3ae0d5668c234f8)
For example, "DS -> branch -> VMEM -> branch -> DS".
fossil-db (navi10):
Totals from 639 (0.40% of 161220) affected shaders:
Instrs: 629090 -> 628254 (-0.13%); split: -0.19%, +0.06%
CodeSize: 3410164 -> 3406748 (-0.10%); split: -0.14%, +0.04%
Latency: 7834755 -> 7821011 (-0.18%); split: -0.70%, +0.52%
InvThroughput: 1369698 -> 1374495 (+0.35%); split: -0.12%, +0.47%
A lot of the fossil-db changes are noise.
threekingdoms.8db138826c386a62.1.foz/0b222ed175eebad0 is an example of a
shader that actually has this issue.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Fixes: c037ba1bb7 ("aco/gfx10: Mitigate LdsBranchVmemWARHazard.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17697>
(cherry picked from commit b17e59a03b2c31460145b691dc5b39b13e340003)
This might break out-of-order rasterization on GFX8-GFX9 because it
relies on the stencil write mask which can be dynamic.
Found by inspection.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17673>
(cherry picked from commit 2012246075abd33751d344a7777f80439e65e7fc)
This reverts commit 96fa23bca5.
The correct fix to the problem was a1bc152340, making this
change obsolete as the pass skips any vars marked with
always_active_io. There was no real advantage to allowing these
vars to be split because they can't be removed anyway. Also there
is no way to split varying arrays gracefully here due to the xfb
layout rules, and this change didn't handle arrays at all.
Removing this obsolete code also fixes an assert in the new CTS
test KHR-Single-GL45.enhanced_layouts.xfb_all_stages. The test
was legally adding xfb offsets to all vertex stages but since
we only mark the varyings in the final vertex stage with the
always_active_io flag the other stages were correctly lowering
to scalars but when an array with an offset hit this code it
asserted since it couldn't handle it.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Fixes: a1bc152340 ("spirv: mark variables decorated with XfbBuffer as always active")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6928
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17878>
(cherry picked from commit 8bffd601ede40f259b3f9239e3d67393e47138e9)
Typo in the handwritten packing code, oof!
Fixes incorrectly repeated shadows in Neverball (among many other bugs,
I assume). Huge thanks to Lina for the idea that this was the
bug -- fixing it was a breeze from there :-)
Fixes: 9f55538834 ("agx: Pack texture ops")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Suggested-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
(cherry picked from commit 47a3f1226c84d2783358737c2d3ca0040f29ed43)
OpenGL API calls like glClearBufferData() result in mapping/unmapping
of a given buffer by Mesa and unmapping of a host blob fails in
virglrenderer because VirGL driver uses command that is intended for
unmapping of a guest buffer. In particular this causes problem for the
"Total War: Warhammer" game that gets GL_OUT_OF_MEMORY error due to the
failed unmapping command. Fix this by setting the mapping usage flag in
accordance to the resource flags, allowing virgl_buffer_transfer_unmap()
to differentiate host buffer from guest.
Fixes: 3b54e5837a ("virgl: support PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT")
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17914>
(cherry picked from commit 46396e97bea603a5cef8177b66a760a11a78af2a)
Fix typo in calculation of position of start of a row of tiles. This
could otherwise cause an out-of-bounds access in the next patch.
Fixes: 81d85be9a5 freedreno/gmem: Reverse order of alternative tile rows
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17888>
(cherry picked from commit 2497741a1b142b0e19f3946d3f49f064c0c8f119)
Keep the list head valid (empty) after allocation from bo cache. Avoids
a potential later crash in lookup_bo in the following sequence:
1. alloc, bo cache hit
2. export
3. re-import
Cc: mesa-stable
Fixes: f3cc0d2747 ("freedreno: import libdrm_freedreno + redesign submit")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6988
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17888>
(cherry picked from commit 8b3f2a9e5d49098a921de643916dd693f569d1bc)
Just got into a midnight discussion with a hw guy.
TC_ACTION_ENA apparently doesn't invalidate L1, so don't clear
the INV_VCACHE flag.
Fixes: 4056e953fe - radeonsi: move emit_cache_flush functions into si_gfx_cs.c
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17902>
(cherry picked from commit 279315fd73e981f0c8876811327bcee0f0ccf7a3)
We're missing a condition that is currently papered over by having
ANV_PIPE_HDC_PIPELINE_FLUSH_BIT in the invalidate bits.
v2: rework with simplication (Caio)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16905>
(cherry picked from commit 5e21f474288e2159c80a80fa20e7b473056df939)
These shouldn't be accessed, and shows up as an uninit access in
valgrind with piglit rasterpos
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10641>
(cherry picked from commit 5449e6d14c872c21f1a8acb05252aef7b31a77f4)
this is broken, and these will never need to be fixed
Fixes: 3a47576687 ("zink: add a compiler pass to match up tex op dest types")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17775>
(cherry picked from commit 32446f51a83f74cd63a589e86f30da59dc53f97c)
adding LINEAR before was a good starter step, but LINEAR
might not actually be supported (e.g., nvidia)
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17775>
(cherry picked from commit 247b8f2924b7832d8520e890cff6891217f5a860)
this is effectively the same as LINEAR, and it still allows dmabuf creation
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17775>
(cherry picked from commit b59eb9c8b791e59cadca161f952ae2ef4473ebe4)
this has a return code, and if it return false, this is probably an
exit condition
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17775>
(cherry picked from commit 188721d6d3d4cab9b0ca8fa419e4c33a33ae3910)
this uses the extension now
Fixes: 21ea19d504 ("zink: Always enable depth clamping, make depth clipping independent.")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17775>
(cherry picked from commit 721f33cd0fc9756c4db5cc88bccc46c977ad05f3)
the shader is already getting a -0.5,-0.5 bias, but the viewport also
needs to be shifted by 0.5 to match
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17775>
(cherry picked from commit 55a4a6b8dcc8b068d24cc1b1c2e1500369c14485)
Conflicts:
src/gallium/drivers/zink/zink_state.c
nine uses this to pass unscaled units for depth bias, which means
the units must be scaled based on the format of the depth buffer
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17775>
(cherry picked from commit 8a8edb310d84f1400d8b8b7e096a9dfc33e198b2)
Conflicts:
src/gallium/drivers/zink/zink_screen.h
this doesn't need to be updated on primtype change since it's always
set
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17775>
(cherry picked from commit a912952c3ea8f4191abc83e3638c6f09341ef15b)
can't clear outside the framebuffer, so set a new one if necessary
Fixes: f1f08e3529 ("zink: massively simplify zink_clear_depth_stencil")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17775>
(cherry picked from commit ff1fb9101fd1ca383c3e2a88f61911c0c2eecd62)
I've noticed this before but never tracked it down, but it's annoying.
The printf hooks would crash with debug shaders when they were loaded
from the cache. This was because nothing was initing the printf hook
in the cached path so the global was never set.
No problems just always creating this afaics.
Fixes: 333ee94285 ("gallivm: rework debug printf hook to use global mapping.")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17867>
(cherry picked from commit 4c0a7a169dd3b929352d8c61f3e47abc2b5628ea)
if a non-kopper swapchain image supports srgb, add a VkImageFormatListCreateInfo
to permit srgb mutability and avoid violating spec
cc: mesa-stable
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17773>
(cherry picked from commit 28ee911ad67192bc7a0683b6061b89e372482faf)
