144186 Commits

Author SHA1 Message Date
Michael Tang
88220083cf microsoft/compiler: More robustly handle setting Register=-1
This is the 'N/A mask' case in the DXIL disassembly.

This logic is taken from: 7c9e487afd/tools/clang/tools/dxcompiler/dxcdisassembler.cpp (L106)

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12513>
2021-08-25 20:19:05 +00:00
Michael Tang
62c3492d0b microsoft/compiler: Add support for SV_SampleIndex intrinsic
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12513>
2021-08-25 20:19:05 +00:00
Alyssa Rosenzweig
c4b5921d55 pan/bi: Fix format specifiers in disassembler
Flagged by cppcheck.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12530>
2021-08-25 20:03:08 +00:00
Alyssa Rosenzweig
589f365d05 pan/bi: Remove unused clause_start field
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12530>
2021-08-25 20:03:08 +00:00
Alyssa Rosenzweig
1c2bc67fac pan/bi: Assert l != NULL in bi_ra
Confuses cppcheck; indeed, the proof is confusing.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12530>
2021-08-25 20:03:08 +00:00
Alyssa Rosenzweig
b1aa15d582 pan/bi: Simplify condition
Flagged by cppcheck.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12530>
2021-08-25 20:03:08 +00:00
Alyssa Rosenzweig
c08423699c panfrost: Remove unused functions
Flagged by cppcheck.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12530>
2021-08-25 20:03:08 +00:00
Alyssa Rosenzweig
e9afd245f4 panfrost: Remove stale TODOs and XXXs
These don't meaningfully apply but their comments never got updated.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12530>
2021-08-25 20:03:08 +00:00
Alyssa Rosenzweig
8f25a606b4 panfrost: Remove CACHE_LINE_SIZE #define
Not only is it unused, it's totally wrong. Not even a little right.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12530>
2021-08-25 20:03:08 +00:00
Erik Faye-Lund
6e05f68924 llvmpipe: rip out cylindrical wrap support
Acked-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12505>
2021-08-25 19:37:16 +00:00
Erik Faye-Lund
e9cc7f1ae4 softpipe: rip out cylindrical wrap support
This is never used, so let's just remove it.

Acked-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12505>
2021-08-25 19:37:16 +00:00
Erik Faye-Lund
7b0bda2e55 gallium/tgsi: rip out cylindrical wrap support
We never enable this feature, so let's rip it out completely.

Acked-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12505>
2021-08-25 19:37:16 +00:00
Erik Faye-Lund
526f7d7790 gallium/tgsi: rip out cylindrical wrap from ureg
We always pass zero to these arguments, so this feature isn't in use.

Acked-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12505>
2021-08-25 19:37:16 +00:00
Erik Faye-Lund
bd93364ea2 gallium/tgsi: remove unused helper
Acked-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12505>
2021-08-25 19:37:16 +00:00
Erik Faye-Lund
e26fd607ca draw/llvmpipe: correct exponent calculation for negative z
If the z components here contain negative values, we'll end up with the
wrong maximum value.

This updated equation is taken from the D3D11 functional spec (section
15.10 Depth Bias), which is a bit more clear than the OpenGL spec.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12443>
2021-08-25 19:12:12 +00:00
Samuel Pitoiset
0f05c84bba radv: allow storage images with VK_FORMAT_E5B9G9R9_UFLOAT_PACK32 on GFX10.3+
It should be supported.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12543>
2021-08-25 16:27:46 +00:00
Rob Clark
74d1052537 freedreno/a6xx: Fix a6xx gen4 compute shaders
I believe the addition of these new regs is related to the changes made
for LPAC ring, so let's key off of that.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12497>
2021-08-25 15:24:19 +00:00
Rob Clark
12a9adbb3b freedreno/a6xx: Register updates for a6xx gen4
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12497>
2021-08-25 15:24:19 +00:00
Rob Clark
ab37109d23 freedreno/a6xx: Updates for tess_use_shared
The formula for calculating these two values seems to depend on
tess_use_shared, ie. a6xx_gen3 and a6xx_gen4 match.  The existing
calculation matches a6xx_gen1 and a6xx_gen2.

The new formula is based on traces varying # of output (from VS)
varyings from (1..31)*vec4 and vertices from (1..31) and coming up
with something that matches the blob.  Once hs_input_size*4 divided
by tcs_vertices_out goes above 64, this deviates a bit from the
blob, but AFAICT it is safe to pick a larger values.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12497>
2021-08-25 15:24:19 +00:00
Rob Clark
31835ac3b8 freedreno/a6xx: Fix streamout with tess_use_shared
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12497>
2021-08-25 15:24:19 +00:00
Rob Clark
219e12b7f3 freedreno/a6xx: Rast updates for a6xx gen3
Not really sure what these new regs are, but blob emits them as part of
rasterizer state starting with a650.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12497>
2021-08-25 15:24:19 +00:00
Rob Clark
677dbb0e52 freedreno/a6xx: Register updates for a6xx gen3
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12497>
2021-08-25 15:24:19 +00:00
Rob Clark
28c5384cf9 freedreno/a6xx: Set type for PC_HS_INPUT_SIZE
It is an unsigned integer.. display it as such.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12497>
2021-08-25 15:24:19 +00:00
Rob Clark
8dff5356ff freedreno/common: Fix comment typo
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12497>
2021-08-25 15:24:19 +00:00
Alyssa Rosenzweig
d051b06a48 panfrost: Raise maximum texture size
The hardware can handle much larger textures than we allowed. The game
"Cathedral" requires larger textures for some bizarre reason. Raise the
limit so the game runs, syncing MAX_MIP_LEVELS, the comments, and the CAPs.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Closes: #5203
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12312>
2021-08-25 13:49:17 +00:00
Daniel Schürmann
cd489e5388 aco: remove redundant s_and exec after nir_op_inot
Totals from 22585 (15.04% of 150170) affected shaders: (GFX10.3)
VGPRs: 1474048 -> 1473904 (-0.01%)
CodeSize: 155238876 -> 155187688 (-0.03%); split: -0.06%, +0.03%
MaxWaves: 385086 -> 385122 (+0.01%)
Instrs: 29297735 -> 29284442 (-0.05%); split: -0.08%, +0.04%
Latency: 675841742 -> 675764151 (-0.01%); split: -0.02%, +0.01%
InvThroughput: 174859037 -> 174854796 (-0.00%); split: -0.01%, +0.01%
VClause: 479790 -> 479781 (-0.00%); split: -0.01%, +0.00%
SClause: 1106900 -> 1106615 (-0.03%); split: -0.03%, +0.01%
Copies: 1829037 -> 1828042 (-0.05%); split: -0.09%, +0.03%
Branches: 859971 -> 859967 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 1341850 -> 1342356 (+0.04%); split: -0.01%, +0.04%
PreVGPRs: 1327322 -> 1327034 (-0.02%)

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11573>
2021-08-25 12:43:50 +00:00
Timur Kristóf
abcc83e713 aco: Fix to_uniform_bool_instr when operands are not suitable.
Don't attempt to transform uniform boolean instructions when
their operands are unsuitable. This can happen eg. due to other
optimizations that combine SALU instructions which clear out
the uniform instruction labels.

Cc: mesa-stable
Fixes: 8a32f57fff56b3b94f1b5589feba38016f39427c
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11573>
2021-08-25 12:43:50 +00:00
Lionel Landwerlin
a13e79843e nir: prevent peephole from generating invalid NIR
We can't append instructions following a return/halt instruction
because the control flow helpers will modify the successor of the
block containing the return/halt. And the NIR validator enforces that
the return/halt must have the end of the function as successor.

This tends to happen following lower_shader_calls lowering which
inserts halts. This probably doesn't prevent the optimization, it'll
just happen in one of the return shaders after the halt has been
removed.

v2: Move prev block ending check earlier in the function (Daniel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12506>
2021-08-25 11:38:21 +00:00
Samuel Pitoiset
e0a703af11 ci: update the list of expected failures/skips for RADV
Against CTS 1.2.7.0.
Tested chips are Pitcairn, Polaris10, Navi14 and Sienna Cichlid.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12539>
2021-08-25 13:00:07 +02:00
Tomeu Vizoso
3f5053b899 iris/ci: Add manual jobs for tracking performance
Use Piglit's replay profile to measure and store the time that frames
take to render in the GPU.

This job won't run automatically in regular pipelines, but will be
triggered automatically by a script for every successful pre-merge
pipeline.

This is because we want to generate performance data for every relevant
commit merged in main, but we don't want to keep a device busy during
the pre-merge run.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12236>
2021-08-25 09:32:17 +02:00
Samuel Pitoiset
cff106c4b6 nir/opt_algebraic: optimize fmax(-fmin(b, a), b) -> fmax(fabs(b), -a)
and fmin(-fmax(b, a)) to fmin(-fabs(b), -a).

fossils-db (Sienna Cichlid):
Totals from 34 (0.02% of 150170) affected shaders:
CodeSize: 388540 -> 387748 (-0.20%)
Instrs: 74621 -> 74423 (-0.27%)
Latency: 1039407 -> 1039011 (-0.04%)
InvThroughput: 208364 -> 208150 (-0.10%)

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12519>
2021-08-25 07:18:24 +02:00
Dave Airlie
ad78643061 crocus: add missing fs dirty on reduced prim change.
the reduced prim is used to decide some line antialiasing settings.
this fixes mesa-demos antialias

Fixes: f3630548f1da ("crocus: initial gallium driver for Intel gfx 4-7")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12536>
2021-08-25 03:30:16 +00:00
Dave Airlie
6b7a68b7c2 crocus: add missing line smooth bits.
Just noticed this in passing.

Fixes: f3630548f1da ("crocus: initial gallium driver for Intel gfx 4-7")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12536>
2021-08-25 03:30:16 +00:00
Mike Blumenkrantz
560dc4f790 zink: fix pipeline caching
this was apparently always broken, but in a very, very subtle way
where the hash table would compare the current pipeline state against
itself instead of using the cache entry's state

Cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12535>
2021-08-25 03:11:41 +00:00
Mike Blumenkrantz
712a4d2fd2 zink: fix program init flag
this was accidentally !! instead of ! as intended

Fixes: c4702204bc3 ("zink: optimize shader recalc")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12535>
2021-08-25 03:11:41 +00:00
Michael Tang
4237aa3a7e spirv_to_dxil: Run nir_lower_tex during compilation
We need this to get e.g. a default lod for some instructions when it is
not provided.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12462>
2021-08-24 22:18:30 +00:00
Dave Airlie
4c260f017c crocus: drop u_primconvert header.
This is just leftover.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12531>
2021-08-24 21:38:27 +00:00
Mike Blumenkrantz
ea18b0930b zink: add better TODO note for surface swizzles
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12529>
2021-08-24 21:23:45 +00:00
Mike Blumenkrantz
6ff5eaa7d5 zink: make void swizzle clamping util public
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12529>
2021-08-24 21:23:45 +00:00
Mike Blumenkrantz
52032d5efa zink: make component mapping function a static inline
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12529>
2021-08-24 21:23:45 +00:00
Mike Blumenkrantz
08bad3b2b8 zink: move void format detection function to zink_format
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12529>
2021-08-24 21:23:45 +00:00
Mike Blumenkrantz
e645e3c523 nine: replace unnecessary dynamic-sized array with bitfield
PIPE_MAX_VERTEX_STREAMS is 4, so this can be simplified to reduce cpu usage

Reviewed-by: <Axel Davy davyaxel0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12523>
2021-08-24 20:38:41 +00:00
Alyssa Rosenzweig
16b4916432 panfrost: Take a ctx when submitting/destroying
This reduces the number of batch->ctx shenanigans we do, and in turn
should reduce raciness.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12366>
2021-08-24 20:20:29 +00:00
Ian Romanick
fe956d0182 spirv: Add support for SPV_KHR_integer_dot_product
v2 (Ivan): Add missing capability enum handling.

v3 (idr): Properly handle cases where dest_size != 32.

v4 (idr): Rewrite most of the error checking to use vtn_fail_if.  Use
nir_ssa_def with vtn_push_nir_ssa instead of vtn_ssa_value with
vtn_push_ssa_value.  All suggested by Jason.  Massive rewrite of the
handling of packed 4x8 saturating opcodes.  Based on some observations
made by Jason.

v5 (idr): Remove some debugging cruft accidentally added in v4.  Noticed
by Jason.

v6: Emit packed versions of vectored instructions when possible.
Suggested by Jason.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12142>
2021-08-24 19:58:57 +00:00
Ian Romanick
652d304ee9 spirv: Update headers and metadata from latest Khronos commit
This corresponds to e7b49d7 ("Implement SPV_INTEL_optnone extension
(#230)") in https://github.com/KhronosGroup/SPIRV-Headers.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12142>
2021-08-24 19:58:57 +00:00
Ian Romanick
a6db40605e nir/algebraic: Add some extract optimizations
These help quite a bit when vectored versions of SpvOpSDotKHR and
friends are emitted as packed versions and then lowered.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12142>
2021-08-24 19:58:57 +00:00
Ian Romanick
839495efc6 nir/algebraic: Add lowering for dot_4x8 instructions
v2: Fix copy-and-paste bugs in lowering patterns.

v3: Add has_sudot_4x8 flag.  Requested by Rhys.

v4: Since the names of the opcodes changed from dp4 to dot_4x8, also
change the names of the lowering helpers.  Suggested by Jason.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12142>
2021-08-24 19:58:57 +00:00
Ian Romanick
0f809dbf40 intel/compiler: Basic support for DP4A instruction
v2: Very significant rebase on changes to previous commits.
Specifically, brw_fs_nir.cpp changes were pretty much rewritten from
scratch after changing the NIR opcode names and types.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12142>
2021-08-24 19:58:57 +00:00
Ian Romanick
806cd2341c nir/algebraic: Basic patterns for dot_4x8
v2: Add and modify patterns to let constant folding do better.

v3: Remove '(is_not_zero)' from the patterns that try to combine
addends.  I honestly don't know why I had it there in the first place,
and nothing in my deep git logs could help clue me in.  Noticed by
Alyssa.  Remover patterns that detect open-coded udot_4x8.  Suggested by
Alyssa and Jason.  Add missing sudot_4x8 patterns.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12142>
2021-08-24 19:58:57 +00:00
Ian Romanick
6c18a3b497 nir/opcodes: Add integer dot-product opcodes
Six opcodes are added: sdot_4x8_iadd, udot_4x8_uadd, sudot_4x8_iadd,
sdot_4x8_iadd_sat, udot_4x8_uadd_sate, and sudot_4x8_iadd_sat.  These
represent the combinations of integer dot-product and add that operate
on packed source vectors.  That is, the four 8-bit values for each
vector is stored in a single 32-bit integer.

Some hardware may prefer to operate on unpacked byte vectors.  When such
hardware comes to Mesa, we'll have to figure out how to name things.

v2: Add nir_op_iudp4a and nir_op_iudp4a_sat instructions.  These opcodes
are not 2-source commutative.

v3: Rename all opcodes to be more like some existing 4x8 opcodes.
Suggested by Timur.  Change type of packed vector sources to uint32,
change types of constant folding variables to have explicit size, and
delete some extra casts.  All suggested by Jason.

v4: Fix typo previously noticed by Alyssa but missed in v2.

v5: Add has_sudot_4x8 flag.  Requested by Rhys.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12142>
2021-08-24 19:58:57 +00:00