96675 Commits

Author SHA1 Message Date
Marek Olšák
255573996c st/dri: implement __DRIimageExtension::validateUsage properly
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-12 19:03:33 +02:00
Marek Olšák
07fdc0a09c gallium: add pipe_screen::check_resource_capability
This is optional (and no CAP).

Implemented by radeonsi, ddebug, rbug, trace.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-12 19:03:33 +02:00
Marek Olšák
5f2073be32 ac/surface: add ac_surface::is_displayable
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-12 19:03:33 +02:00
Marek Olšák
c3f3685fd6 amd/addrlib: add Addr2IsValidDisplaySwizzleMode
Some "standard" (_S) swizzle modes are displayable on Raven,
even though the micro tile mode says it's not displayable.
Expose the addrlib function to the driver.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-12 19:03:33 +02:00
tournier.elie
1233d32d2a meson: fix typo in isl
Signed-off-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Antia Puentes <apuentes@igalia.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2017-10-12 09:39:07 -07:00
Rob Herring
137b32b815 Android: disable i9x5 drivers on non-x86 builds
The i965 driver has become dependent on x86 specific compiler builtin
functions, so ensure it's disabled for non-x86 builds.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Rob Herring <robh@kernel.org>
2017-10-12 09:06:09 -05:00
Wladimir J. van der Laan
78ade65956 etnaviv: Do GC3000 resolve-in-place when possible
If an RS blit is done with source exactly the same as destination, and
the hardware supports this, do an in-place resolve. This only fills in
tiles that have not been rendered to using information from the TS.

This is the same as the blob does and potentially saves significant
bandwidth when doing i.MX6qp scanout using PRE, and when rendering to
textures (though here using sampler TS would be even better).

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
2017-10-12 16:03:26 +02:00
Eric Engestrom
3ba5a467a5 egl_haiku: drop haiku_egl_driver struct
The struct only contained the one field we're interested in.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-10-12 14:55:10 +01:00
Eric Engestrom
3188b6e45f egl: remove left over _EGLMain_t
Fixes: b174a1ae720cb404738c "egl: Simplify the "driver" interface"
Cc: Adam Jackson <ajax@redhat.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-10-12 14:43:48 +01:00
Eric Engestrom
4a6c7e8ad8 egl: drop memset(0) of calloc'ed memory
`_EGLDriver *drv` is a freshly calloc()'ed object, memset(0)'ing some of
it is a no-op.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-10-12 14:40:12 +01:00
Eric Engestrom
9690759d0c egl: replace _egl_driver->Unload() callback with a simple free()
Bonus: fixes a memleak on haiku when unloading the driver

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-10-12 14:38:55 +01:00
Dave Airlie
6049fa454e radv: don't crash if cache is disabled.
If you set MESA_GLSL_CACHE_DISABLE, radv crashed.

Fixes: fd24be134f (radv: make use of on-disk cache)
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-10-12 14:14:43 +02:00
Samuel Pitoiset
4f42ea4dcf radv: use CLEAR_STATE for initializing some registers
Based on RadeonSI.

This improves some Vulkan demos by +1% to +3%.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-12 09:17:43 +02:00
Samuel Pitoiset
65dcff7a26 radv: add has_clear_state and enable it on CIK+ only
This will allow us to emit the CLEAR_STATE packet instead
of a bunch of useless packets when doing CS initialization.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-12 09:17:40 +02:00
Samuel Pitoiset
c74ed3966e radv: do not set registers for merged ES-GS on GFX9
Based on RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-12 09:17:38 +02:00
Samuel Pitoiset
1789cac6dd radv: move the raster config emission in si_set_raster_config()
Similar to RadeonSI, also only call this function for <= VI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-12 09:17:35 +02:00
Nicolai Hähnle
bc2d874101 radeonsi: add support for PIPE_FORMAT_{X1,A1}R5G5B5_UNORM
Fixes dEQP-EGL.functional.image.modify.tex_rgb5_a1_tex_subimage_rgba8

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-10-12 08:42:55 +02:00
Nicolai Hähnle
9f55da130e gallium: add tests for PIPE_FORMAT_{X1,A1}B5G5R5_UNORM formats
This is a left-over from my version of adding the new format
after rebasing on Eric's version.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-10-12 08:42:55 +02:00
Dave Airlie
a3ba14d0ce include/drm-uapi: clarify when headers can be updated.
Clarify when headers can be updated here.

Reviewed-by: Gurchetan Singh<gurchetansingh@chromium.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-12 09:44:27 +10:00
Timothy Arceri
0061a90550 radv: remove duplicate line of code
The same line of code is a few lines above.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-10-12 08:52:39 +11:00
Timothy Arceri
fd24be134f radv: make use of on-disk cache
If the app provided in-memory pipeline cache doesn't yet contain
what we are looking for, or it doesn't provide one at all then we
fallback to the on-disk cache.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-12 08:52:38 +11:00
Timothy Arceri
1421625292 radv: create on-disk shader cache
This is the drivers on-disk cache intended to be used as a
fallback as opposed to the pipeline cache provided by apps.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-12 08:52:38 +11:00
Timothy Arceri
7664aaf331 radv: remove duplicate debug_flags field
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-12 08:52:38 +11:00
Lionel Landwerlin
e568d2bd1f anv: intel: use anv_image's computed size for importing a BO
Rather than relying on size = stride * height, we can rely on
anv_image's total size.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Daniel Stone <daniels@collabora.com>
2017-10-11 22:29:55 +01:00
Lionel Landwerlin
c0a4f56fb9 anv: bo_cache: allow importing a BO larger than needed
It's not a problem if a BO has been allocated larger than we need it
to be.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102940
Fixes: 818b857914 ("anv: Use the BO cache for DeviceMemory allocations")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Cc: mesa-stable@lists.freedesktop.org
2017-10-11 22:29:55 +01:00
Nicolai Hähnle
cf3dd91969 st/glsl_to_tgsi: the second destination doesn't support relative addressing
It's not used -- DFRACEXP gets array indexes of its exponent out-parameter
lowered earlier -- and it wouldn't have worked correctly anyway when both
dst and dst1 use relative addressing.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-10-11 23:17:08 +02:00
Nicolai Hähnle
3b666aa747 st/glsl_to_tgsi: fix DFRACEXP with only one destination
Replace the undefined destination by a new temporary register.

Cleanup merge_two_dsts while we're at it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-10-11 23:17:06 +02:00
Nicolai Hähnle
541208cf13 st/glsl_to_tgsi: fix indirect access to 64-bit integer
Make sure we actually allocate two adjacent TGSI temporaries. The
current code fails e.g. when an arithmetic operation has two
operands with indirect accesses.

I will send out a new piglit test
(arb_gpu_shader_int64/execution/indirect-array-two-accesses.shader_test)

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-10-11 23:16:56 +02:00
Nicolai Hähnle
2991c0d7df st/mesa: don't assign prog->ShadowSamplers
It's not used, and the assignment for the TGSI case was incorrect
for sampler arrays.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-10-11 23:16:21 +02:00
Nicolai Hähnle
0e26e767d2 st/glsl_to_tgsi: ignore GL_TEXTURE_SRGB_DECODE_EXT for samplers used with texelFetch*()
See the comment for the relevant spec quote.

Fixes dEQP-GLES31.functional.srgb_texture_decode.skip_decode.srgba8.texel_fetch

v2: note the interaction between ARB_bindless_texture and EXT_texture_sRGB_decode
    as a TODO

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-10-11 23:16:20 +02:00
Nicolai Hähnle
bce3055c69 st/mesa: store state that affects sampler views per context
This fixes sequences like:

1. Context 1 samples from texture with sRGB decode enabled
2. Context 2 samples from texture with sRGB decode disabled
3. Context 1 samples from texture with sRGB decode disabled

Previously, step 3 would see the prev_sRGBDecode value from context 2
and would incorrectly use the old sampler view with sRGB decode enabled.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-10-11 23:16:20 +02:00
Tim Rowley
e484805352 swr: simd16 shaders work in progress
Start building vertex shaders as simd16.

Disabled by default, set USE_SIMD16_SHADERS in knobs.h to experiment.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-10-11 14:35:23 -05:00
Tim Rowley
9cad9cbaf8 gallium: allow 512-bit vectors
Increase the max allowed vector size from 256 to 512.

No piglit llvmpipe regressions running on avx2.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-10-11 14:34:31 -05:00
Kenneth Graunke
fe7fab4be5 i965: Drop brw_bo_alloc in ARB_indirect_parameters implementation.
The original implementation allocated a new BO here, but we decided to
switch to intel_upload_space, which returns a reference to the current
upload BO.  We accidentally kept the brw_bo_alloc, even though it's no
longer necessary - intel_upload_space will immediately unreference it,
causing us to allocate and immediately free a buffer.

Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
2017-10-11 12:22:29 -07:00
Kenneth Graunke
e401cfa28a i965: Allow mapped VBOs during drawing in non-debug contexts.
Section 6.3.2 of the GL 4.5 spec says:

   "Any GL command which attempts to read from, write to, or change
    the state of a buffer object may generate an INVALID_OPERATION error
    if all or part of the buffer object is mapped ... However, only
    commands which explicitly describe this error are required to do so.
    If an error is not generated, such commands will have undefined
    results and may result in GL interruption or termination."

Setting this flag allows us to skip walking over the buffer bindings
for every enabled vertex attribute (_mesa_all_buffers_are_unmapped).

Improves performance in GFXBench4's gl_driver2_off microbenchmark by
3.05797% +/- 0.709031% (n=33) on Apollolake.

This breaks KHR-*.draw_elements_base_vertex_tests.invalid_mapped_bos,
but that test is invalid and has been removed from the upstream CTS.

Reviewed-by: Eric Anholt <eric@anholt.net>
2017-10-11 12:22:25 -07:00
Dylan Baker
3c66a461f3 meson: fix glx test
That requires a generated header that was rolled into a loop.

fixes: a47c525f3281a27 ("meson: build glx")
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-10-11 10:45:31 -07:00
Ilia Mirkin
b20bccbcac nv50,nvc0: fix push hint logic in presence of a start offset
Previously buffer offsets were passed in explicitly as an offset, which
had to be added to the resource address. Now they are passed in via an
increased 'start' parameter. As a result, we were double-adding the
start offset in this kind of situation.

This condition was triggered by piglit's draw-elements test which has a
requisite glMultiDrawElements in combination with a small enough number
of vertices to go through the immediate push path.

Fixes: 330d0607ed6 ("gallium: remove pipe_index_buffer and set_index_buffer")
Reported-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
2017-10-11 08:18:16 -04:00
Kenneth Graunke
735711ab86 i965: Make brw_update_texture_surface static.
Trivial.  It's not used in other files.
2017-10-11 00:09:06 -07:00
Rob Herring
e5e93c727f Android: fix build break from r600/radeon split
Commit 06bfb2d28f7a ("r600: fork and import gallium/radeon") broke the
Android build:

external/mesa3d/src/gallium/drivers/radeon/r600_pipe_common.c:43:10: fatal error: 'llvm-c/TargetMachine.h' file not found
         ^~~~~~~~~~~~~~~~~~~~~~~~

Update the Android makefiles so that drivers/radeon is only built when
radeonsi (and therefore LLVM) is enabled.

Fixes: 06bfb2d28f7a (r600: fork and import gallium/radeon)
Acked-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Rob Herring <robh@kernel.org>
2017-10-10 21:37:19 -05:00
Rob Herring
c3f75d483c Android: move libraries to /vendor
As part of Treble project in Android O, all the device specific files have
to be located in a separate vendor partition. This is done by setting
LOCAL_PROPRIETARY_MODULE (the name is misleading). This change will not
break existing platforms without a vendor partition as it will just move
files to /system/vendor.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Rob Herring <robh@kernel.org>
2017-10-10 21:37:16 -05:00
Kenneth Graunke
6f5abf3146 i965: Fix output register sizes when multiple variables share a slot.
ARB_enhanced_layouts allows multiple output variables to share the same
location - and these variables may not have the same sizes.  For
example, consider these output variables:

   // consume X/Y/Z components of 6 vectors
   layout(location = 0) out vec3 a[6];

   // consumes W component of the first vector
   layout(location = 0, component = 3) out float b;

Looking at the first declaration, we see that VARYING_SLOT_VAR0 needs 24
components worth of space (vec3 padded out to a vec4, 4 * 6 = 24).  But
looking at the second declaration, we would think that VARYING_SLOT_VAR0
needs only 4 components of space (a single float padded out to a vec4).

nir_setup_outputs() only considered the space requirements of the first
declaration it happened to see, so if 'float b' came first, it would
underallocate the output register space, causing brw_fs_validator.cpp
to assert fail about inst->dst.offset exceeding the register size.

Fixes Piglit's tests/spec/arb_enhanced_layouts/execution/component-layout/
vs-to-fs-array-interleave-single-location.shader_test.

Thanks to Tim Arceri for finding this bug and writing a test!

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-10-10 17:29:37 -07:00
Dave Airlie
2d36efdb7f nir: bump loop unroll limit to 96.
With the ssao demo from Vulkan demos:
radv/rx480: 440->440fps
anv/haswell: 24->34 fps

The demo does a 0->32 loop across a ubo with 32 members.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-11 10:11:36 +10:00
Dave Airlie
5be3fdfa32 anv: fix assert in wsi image code.
This assert was firing just running demos.

Jason said it should be this.

Fixes: 6c7720ed78 (anv/wsi: Allocate enough memory for the entire image)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-11 09:52:57 +10:00
Dave Airlie
9926af0e71 mesa/st: fix atomic buffer sizing to align with ssbo.
This respects the size from the range setting like ssbo.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-11 09:10:21 +10:00
Dave Airlie
3e156b89ed mesa/bufferobj: consolidate some buffer binding code.
These paths are again 90% the same, consolidate them into
one.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-11 09:10:21 +10:00
Dave Airlie
35ac13ed32 mesa/bufferobj: consolidate some codepaths between ubo/ssbo/atomics.
These are 90% the same code, consolidate them into a couple of
common codepaths.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-11 09:10:21 +10:00
Dave Airlie
d2bfa76045 mesa: rename various buffer bindings to one struct.
One binding to bind them all, these are all the same thing.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-11 09:10:20 +10:00
Dave Airlie
65d3ef7cd4 mesa: align atomic buffer handling code with ubo/ssbo (v1.1)
this adds automatic size support to the atomic buffer code,
but also realigns the code to act like the ubo/ssbo code.

v1.1:
add missing blank lines.
reindent one block properly.
check for NullBufferObj.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-11 09:10:20 +10:00
Kenneth Graunke
03087686ff i965: Don't try to decode types for non-existent src1.
KHR-GL45.shader_ballot_tests.ShaderBallotBitmasks has a MOV that hits
this validation path.  MOVs don't have a src1 file, but calling
brw_inst_src1_type() was tripping on src1.file being BRW_IMMEDIATE_VALUE
and the hw_type being something invalid for immediates.

To work around this, just pretend src1 is src0 if there isn't a src1.

Fixes: 2572c2771d0cab0b9bc489d354ede44dfc88547b (i965: Validate "Special
       Requirements for Handling Double Precision Data Types")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102680
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2017-10-10 15:11:35 -07:00
Karol Herbst
eab078f132 main/format: skip format conversion if src and dst format are equal
Fixes 'KHR-GL45.copy_image.functional' on Nouveau and i965.

v2: (by Kenneth Graunke)
    Rewrite patch according to Jason Ekstrand's review feedback.
    This makes it handle differing strides, which i965 needed.

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-10 15:06:17 -07:00