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Merge branch 'master' of https://github.com/KhronosGroup/SPIRV-Headers into uniform_group_instructions

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This commit is contained in:
Nikita Kornev
2022-03-02 15:30:15 +03:00
parent 5b634e4352 8c7c8d3e0e
commit 534e72c73d
10 changed files with 63 additions and 2 deletions
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include/spirv/spir-v.xml
+2 -1
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@@ -166,13 +166,14 @@
<ids type="enumerant" start="6144" end="6271" vendor="Intel" comment="Contact michael.kinsner@intel.com"/>
<ids type="enumerant" start="6272" end="6399" vendor="Huawei" comment="Contact wanghuilong2@xunweitech.com"/>
<ids type="enumerant" start="6400" end="6463" vendor="Intel" comment="Contact ben.ashbaugh@intel.com"/>
<ids type="enumerant" start="6464" end="6527" vendor="Mikkosoft Productions" comment="Contact Mikko Rasa, tdb@tdb.fi"/>
<!-- Enumerants to reserve for future use. To get a block, allocate
multiples of 64 starting at the lowest available point in this
block and add a corresponding <ids> tag immediately above. Make
sure to fill in the vendor attribute, and preferably add a contact
person/address in a comment attribute. -->
<!-- Example new block: <ids type="enumerant" start="XXXX" end="XXXX+64n-1" vendor="Add vendor" comment="Contact TBD"/> -->
<ids type="enumerant" start="6464" end="4294967295" comment="Enumerant range reservable for future use by vendors"/>
<ids type="enumerant" start="6528" end="4294967295" comment="Enumerant range reservable for future use by vendors"/>
<!-- End reservations of enumerants -->
include/spirv/unified1/spirv.core.grammar.json
+31 -1
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@@ -5029,7 +5029,7 @@
"opname" : "OpDemoteToHelperInvocationEXT",
"class" : "Control-Flow",
"opcode" : 5380,
"capabilities" : [ "DemoteToHelperInvocation" ],
"capabilities" : [ "DemoteToHelperInvocationEXT" ],
"version" : "1.6"
},
{
@@ -8550,6 +8550,30 @@
"capabilities" : [ "LongConstantCompositeINTEL" ],
"version" : "None"
},
{
"opname" : "OpControlBarrierArriveINTEL",
"class" : "Barrier",
"opcode" : 6142,
"operands" : [
{ "kind" : "IdScope", "name" : "'Execution'" },
{ "kind" : "IdScope", "name" : "'Memory'" },
{ "kind" : "IdMemorySemantics", "name" : "'Semantics'" }
],
"capabilities" : [ "SplitBarrierINTEL" ],
"version" : "None"
},
{
"opname" : "OpControlBarrierWaitINTEL",
"class" : "Barrier",
"opcode" : 6143,
"operands" : [
{ "kind" : "IdScope", "name" : "'Execution'" },
{ "kind" : "IdScope", "name" : "'Memory'" },
{ "kind" : "IdMemorySemantics", "name" : "'Semantics'" }
],
"capabilities" : [ "SplitBarrierINTEL" ],
"version" : "None"
},
{
"opname" : "OpGroupIMulKHR",
"class" : "Group",
@@ -14002,6 +14026,12 @@
"extensions" : [ "SPV_INTEL_debug_module" ],
"version" : "None"
},
{
"enumerant" : "SplitBarrierINTEL",
"value" : 6141,
"extensions" : [ "SPV_INTEL_split_barrier" ],
"version" : "None"
},
{
"enumerant" : "GroupUniformArithmeticKHR",
"value" : 6400,
include/spirv/unified1/spirv.cs
+3
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@@ -1087,6 +1087,7 @@ namespace Spv
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
SplitBarrierINTEL = 6141,
GroupUniformArithmeticKHR = 6400,
}
@@ -1852,6 +1853,8 @@ namespace Spv
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,
include/spirv/unified1/spirv.h
+5
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@@ -1087,6 +1087,7 @@ typedef enum SpvCapability_ {
SpvCapabilityOptNoneINTEL = 6094,
SpvCapabilityAtomicFloat16AddEXT = 6095,
SpvCapabilityDebugInfoModuleINTEL = 6114,
SpvCapabilitySplitBarrierINTEL = 6141,
SpvCapabilityGroupUniformArithmeticKHR = 6400,
SpvCapabilityMax = 0x7fffffff,
} SpvCapability;
@@ -1850,6 +1851,8 @@ typedef enum SpvOp_ {
SpvOpTypeStructContinuedINTEL = 6090,
SpvOpConstantCompositeContinuedINTEL = 6091,
SpvOpSpecConstantCompositeContinuedINTEL = 6092,
SpvOpControlBarrierArriveINTEL = 6142,
SpvOpControlBarrierWaitINTEL = 6143,
SpvOpGroupIMulKHR = 6401,
SpvOpGroupFMulKHR = 6402,
SpvOpGroupBitwiseAndKHR = 6403,
@@ -2512,6 +2515,8 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
case SpvOpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
case SpvOpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
case SpvOpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
include/spirv/unified1/spirv.hpp
+5
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@@ -1083,6 +1083,7 @@ enum Capability {
CapabilityOptNoneINTEL = 6094,
CapabilityAtomicFloat16AddEXT = 6095,
CapabilityDebugInfoModuleINTEL = 6114,
CapabilitySplitBarrierINTEL = 6141,
CapabilityGroupUniformArithmeticKHR = 6400,
CapabilityMax = 0x7fffffff,
};
@@ -1846,6 +1847,8 @@ enum Op {
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,
@@ -2508,6 +2511,8 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
case OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
case OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
case OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
case OpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
include/spirv/unified1/spirv.hpp11
+5
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@@ -1083,6 +1083,7 @@ enum class Capability : unsigned {
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
SplitBarrierINTEL = 6141,
GroupUniformArithmeticKHR = 6400,
Max = 0x7fffffff,
};
@@ -1846,6 +1847,8 @@ enum class Op : unsigned {
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,
@@ -2508,6 +2511,8 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
case Op::OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
case Op::OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
case Op::OpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
include/spirv/unified1/spirv.json
+3
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@@ -1065,6 +1065,7 @@
"OptNoneINTEL": 6094,
"AtomicFloat16AddEXT": 6095,
"DebugInfoModuleINTEL": 6114,
"SplitBarrierINTEL": 6141,
"GroupUniformArithmeticKHR": 6400
}
},
@@ -1839,6 +1840,8 @@
"OpTypeStructContinuedINTEL": 6090,
"OpConstantCompositeContinuedINTEL": 6091,
"OpSpecConstantCompositeContinuedINTEL": 6092,
"OpControlBarrierArriveINTEL": 6142,
"OpControlBarrierWaitINTEL": 6143,
"OpGroupIMulKHR": 6401,
"OpGroupFMulKHR": 6402,
"OpGroupBitwiseAndKHR": 6403,
include/spirv/unified1/spirv.lua
+3
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@@ -1045,6 +1045,7 @@ spv = {
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
SplitBarrierINTEL = 6141,
GroupUniformArithmeticKHR = 6400,
},
@@ -1797,6 +1798,8 @@ spv = {
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,
include/spirv/unified1/spirv.py
+3
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@@ -1045,6 +1045,7 @@ spv = {
'OptNoneINTEL' : 6094,
'AtomicFloat16AddEXT' : 6095,
'DebugInfoModuleINTEL' : 6114,
'SplitBarrierINTEL' : 6141,
'GroupUniformArithmeticKHR' : 6400,
},
@@ -1797,6 +1798,8 @@ spv = {
'OpTypeStructContinuedINTEL' : 6090,
'OpConstantCompositeContinuedINTEL' : 6091,
'OpSpecConstantCompositeContinuedINTEL' : 6092,
'OpControlBarrierArriveINTEL' : 6142,
'OpControlBarrierWaitINTEL' : 6143,
'OpGroupIMulKHR' : 6401,
'OpGroupFMulKHR' : 6402,
'OpGroupBitwiseAndKHR' : 6403,
include/spirv/unified1/spv.d
+3
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@@ -1090,6 +1090,7 @@ enum Capability : uint
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
SplitBarrierINTEL = 6141,
GroupUniformArithmeticKHR = 6400,
}
@@ -1855,6 +1856,8 @@ enum Op : uint
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,