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46b7918218
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286 Commits

Author SHA1 Message Date
John Kessenich
46b7918218
Merge pull request #274 from rayanht/patch-1 
Register magic number for SPIRVSmith
 2022-04-20 22:57:59 +07:00
Kevin Petit
ee9e6ddf3f do not enable the instruction with the extension 
Go via the capability

Change-Id: I9273f53dc6fa29a1bc6a66854f17731da1532117
 2022-04-20 16:53:10 +01:00
Kevin Petit
c0bd604223 Add SPV_KHR_subgroup_rotate 
Signed-off-by: Kevin Petit <kevin.petit@arm.com>
Change-Id: I49e7c2d509007958fbe1a6aa2d2fdf11dffbef4d
 2022-04-20 13:26:47 +01:00
Rayan Hatout
ef6ecedddd
Register magic number for SPIRVSmith 2022-04-17 22:56:56 +01:00
Raun Krisch
9c3fd01c8a
Merge pull request #270 from kpet/sycl 
Add a SourceLanguage for SYCL
 2022-04-06 11:23:53 -05:00
DmitryBushev
5ecb8bc821 Removed extension section 2022-04-05 16:01:03 +03:00
DmitryBushev
bf5bffa938 Add NamedBarrierCountINTEL execution mode 2022-04-05 15:18:24 +03:00
Kevin Petit
064395f0f8 Add a SourceLanguage for SYCL 
Signed-off-by: Kevin Petit <kevin.petit@arm.com>
Change-Id: Ib12851c89000bbda7bf516a30146ca6f63f98419
 2022-03-17 16:42:51 +00:00
Raun Krisch
4995a2f272
Merge pull request #269 from KornevNikita/uniform_group_instructions 
Implement SPV_KHR_uniform_group_instructions extension
 2022-03-15 22:27:40 -05:00
Nikita Kornev
7744288e2d Remove extensions tag from instructions 2022-03-03 10:07:13 +03:00
Raun Krisch
0e994ee9c4
Merge pull request #261 from ProkopRandacek/master 
Include bool type if not already defined
 2022-03-02 11:18:40 -06:00
Nikita Kornev
48fadab867 Merge branch 'master' of https://github.com/KhronosGroup/SPIRV-Headers into uniform_group_instructions 2022-03-02 15:30:15 +03:00
Nikita Kornev
a4a03f677a Implement SPV_KHR_uniform_group_instructions extension 
Spec: https://github.com/KhronosGroup/SPIRV-Registry/pull/138
 2022-03-02 15:12:49 +03:00
Raun Krisch
f75fc98bad
Merge pull request #268 from bashbaug/SPV_INTEL_split_barrier 
update SPIR-V headers for SPV_INTEL_split_barrier
 2022-02-23 11:04:06 -06:00
Raun Krisch
24c841de7d
Merge pull request #263 from DataBeaver/master 
Reserve enum range for MSP extensions
 2022-02-23 11:02:48 -06:00
Raun Krisch
f85647cbf2
Merge pull request #264 from gnl21/demote-ext-tag 
Add EXT tag to capability to DemoteToHelperInvocationEXT
 2022-02-23 11:01:13 -06:00
Ben Ashbaugh
ed206e3817 update SPIR-V headers for SPV_INTEL_split_barrier 2022-02-12 18:14:08 -08:00
Dmitry Bushev
6a55fade62
Implement SPV_INTEL_memory_access_aliasing extension (#265) 
Modify headers to include declarations of tokens described
by this spec:

   https://github.com/intel/llvm/pull/3426
 2022-02-08 13:29:45 +03:00
Prokop Randacek
bf985e99ec
regenerate headers 2022-02-08 09:26:02 +01:00
Graeme Leese
c89cabce94 Add EXT tag to capability to DemoteToHelperInvocationEXT 
Normally the grammar uses the extension tagged capability names when
talking about extension tagged instructions. Technically speaking
they're the same capability, but it's nice to be consistent.
 2022-01-31 13:52:19 +00:00
Mikko Rasa
c31dbf6c14 Reserve enum range for MSP extensions 2022-01-28 12:33:48 +02:00
Michael Kinsner
bf2809d6f4 Allocate additional loop control bit for upcoming Intel extension 2022-01-17 16:45:26 -04:00
Prokop Randacek
e14816714e
regenerate the headers 2022-01-05 19:02:52 +01:00
Sylvain Doremus
9dd7c53c71
Merge branch 'master' into add_shader_writer 2021-12-21 13:24:31 +01:00
John Kessenich
dcd4752edb Update headers with SPIR-V version 1.6, revision 1. 2021-12-16 00:26:22 +07:00
Raun Krisch
d53b49635b
Merge pull request #256 from jjfumero/tornadovm-generator 
Register TornadoVM SPIRV Beehive Tookit Generator
 2021-12-08 08:51:28 -06:00
Raun Krisch
29414ae1fd
Merge pull request #257 from Hardcode84/atomic-float-no-shader 
Atomic float add should not imply Shader
 2021-12-01 11:05:17 -06:00
Raun Krisch
993b82fe63
Merge pull request #258 from kpet/arm-contact 
Change contact for Arm
 2021-11-30 17:07:48 -06:00
Dmitry Bushev
20b02de995
Add MediaBlockIOINTEL decoration declaration (#255) 
Declared new MediaBlockIOINTEL decoration added by VectorComputeINTEL
capability
 2021-11-30 17:05:45 +03:00
Kevin Petit
98f12c1504 Change contact for Arm 
Signed-off-by: Kevin Petit <kevin.petit@arm.com>
Change-Id: I5ab24d76c4b3227ae768c23bf1702b18665f3995
 2021-11-30 09:54:39 +00:00
Butygin
28005d6576 Atomic float add should not imply Shader 2021-11-24 23:25:29 +03:00
Juan Fumero
6d7d2f74cc Register TornadoVM SPIRV Beehive Tookit Generator 2021-11-23 15:23:58 +01:00
DragonJoker
9b37ebb4a2 Add ShaderWriter as SPIR-V generation tool. 2021-11-16 15:34:48 +01:00
Raun Krisch
814e728b30
Merge pull request #251 from MrSidims/private/MrSidims/FunctionPointerINTEL 
Rename ConstFunctionPointerINTEL to ConstantFunctionPointerINTEL
 2021-11-10 11:15:54 -06:00
Raun Krisch
29817199b7
Merge pull request #250 from kpet/clspv-reflection-subgroups 
Add SpecConstantSubgroupMaxSize to the clspv reflection non-semantic instruction set
 2021-11-03 10:53:38 -05:00
Dmitry Sidorov
1639e91f42 Rename ConstFunctionPointerINTEL to ConstantFunctionPointerINTEL 
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
 2021-11-03 13:10:10 +03:00
Kévin Petit
43d173bd65 Add SpecConstantSubgroupMaxSize to the clspv reflection non-semantic instruction set 
Signed-off-by: Kévin Petit <kpet@free.fr>
 2021-10-25 18:33:26 +01:00
Pankaj Mistry
cec3084901 Implement header definitions for SPV_NV_bindless_texture 2021-10-21 11:17:23 -07:00
Ben Ashbaugh
442c6a62db reserve SPIR-V enum block for Intel extensions 2021-10-12 17:04:12 -07:00
John Kessenich
19e8350415
Merge pull request #245 from pmistryNV/nonconstoffset 
Define a new Image operand bit mask for non constant offsets
 2021-10-08 11:22:39 +07:00
Pankaj Mistry
e225eb0bec Define a new Image operand bit mask for non constant offsets 
For details refer to https://gitlab.khronos.org/spirv/SPIR-V/-/issues/639
As part of the commit following changes have been introduced:
1. Added a separate section in spirv xml to reserve vendor specific bit masks.
2. Added a new image operand bit mask to support non constant offsets in textureGatherOffsets as defined in GL_NV_gpu_shader5
 2021-10-06 09:54:05 -07:00
egdaniel
2c4b195695
Register Magic Num for Skia SkSL SPIR-V Generator 2021-10-01 09:34:50 -04:00
Graeme Leese
f487ad9199 Remove 'Kernel' capability from fast-math flags 
The use of these flags (the FPFastMath decoration) is already protected
by the capability, so it isn't needed to protect the individual values
as well.
 2021-09-16 10:44:39 +01:00
Marijn Suijten
b1a7c66be7 spirv.core.grammar: Remove duplicate OpArbitraryFloatPowNINTEL declaration 
An identical declaration of `OpArbitraryFloatPowNINTEL` exists just
above, with the exact same opcode and operands.
 2021-08-16 11:40:02 +02:00
Raun Krisch
e71feddb3f
Merge pull request #226 from clayengine/master 
Clay is an internal framework of Tellusim Technologies Inc.
 2021-08-11 11:26:16 -05:00
Raun Krisch
1160d54e9c
Merge pull request #233 from NikitaRudenkoIntel/opt 
Fix minor details in SPV_INTEL_optnone extension
 2021-08-11 11:23:51 -05:00
alelenv
b1d2909b95 Add support for SPV_NV_ray_tracing_motion_blur. 2021-08-10 11:01:14 -07:00
Nikita Rudenko
b6b8b6792e Fix minor details in SPV_INTEL_optnone extension 
Spec: https://github.com/intel/llvm/pull/3198
 2021-07-28 19:39:47 +03:00
Nikita Rudenko
e7b49d7fb5
Implement SPV_INTEL_optnone extension (#230) 
Spec: https://github.com/intel/llvm/pull/3198
 2021-07-28 19:46:47 +06:00
Graeme Leese
737f9dcde9 Correct grammar for LocalSizeHintId 
It is described in the spec as being the "same as LocalSizeHint mode,
but using <id> operands instead of literals", but the grammar had a
single <id> operand instead of the 3 literals for LocalSizeHint.
 2021-07-20 10:18:36 +01:00