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f85647cbf2
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267 Commits

Author SHA1 Message Date
Raun Krisch
f85647cbf2
Merge pull request #264 from gnl21/demote-ext-tag 
Add EXT tag to capability to DemoteToHelperInvocationEXT
 2022-02-23 11:01:13 -06:00
Dmitry Bushev
6a55fade62
Implement SPV_INTEL_memory_access_aliasing extension (#265) 
Modify headers to include declarations of tokens described
by this spec:

   https://github.com/intel/llvm/pull/3426
 2022-02-08 13:29:45 +03:00
Graeme Leese
c89cabce94 Add EXT tag to capability to DemoteToHelperInvocationEXT 
Normally the grammar uses the extension tagged capability names when
talking about extension tagged instructions. Technically speaking
they're the same capability, but it's nice to be consistent.
 2022-01-31 13:52:19 +00:00
Michael Kinsner
bf2809d6f4 Allocate additional loop control bit for upcoming Intel extension 2022-01-17 16:45:26 -04:00
Sylvain Doremus
9dd7c53c71
Merge branch 'master' into add_shader_writer 2021-12-21 13:24:31 +01:00
John Kessenich
dcd4752edb Update headers with SPIR-V version 1.6, revision 1. 2021-12-16 00:26:22 +07:00
Raun Krisch
d53b49635b
Merge pull request #256 from jjfumero/tornadovm-generator 
Register TornadoVM SPIRV Beehive Tookit Generator
 2021-12-08 08:51:28 -06:00
Raun Krisch
29414ae1fd
Merge pull request #257 from Hardcode84/atomic-float-no-shader 
Atomic float add should not imply Shader
 2021-12-01 11:05:17 -06:00
Raun Krisch
993b82fe63
Merge pull request #258 from kpet/arm-contact 
Change contact for Arm
 2021-11-30 17:07:48 -06:00
Dmitry Bushev
20b02de995
Add MediaBlockIOINTEL decoration declaration (#255) 
Declared new MediaBlockIOINTEL decoration added by VectorComputeINTEL
capability
 2021-11-30 17:05:45 +03:00
Kevin Petit
98f12c1504 Change contact for Arm 
Signed-off-by: Kevin Petit <kevin.petit@arm.com>
Change-Id: I5ab24d76c4b3227ae768c23bf1702b18665f3995
 2021-11-30 09:54:39 +00:00
Butygin
28005d6576 Atomic float add should not imply Shader 2021-11-24 23:25:29 +03:00
Juan Fumero
6d7d2f74cc Register TornadoVM SPIRV Beehive Tookit Generator 2021-11-23 15:23:58 +01:00
DragonJoker
9b37ebb4a2 Add ShaderWriter as SPIR-V generation tool. 2021-11-16 15:34:48 +01:00
Raun Krisch
814e728b30
Merge pull request #251 from MrSidims/private/MrSidims/FunctionPointerINTEL 
Rename ConstFunctionPointerINTEL to ConstantFunctionPointerINTEL
 2021-11-10 11:15:54 -06:00
Raun Krisch
29817199b7
Merge pull request #250 from kpet/clspv-reflection-subgroups 
Add SpecConstantSubgroupMaxSize to the clspv reflection non-semantic instruction set
 2021-11-03 10:53:38 -05:00
Dmitry Sidorov
1639e91f42 Rename ConstFunctionPointerINTEL to ConstantFunctionPointerINTEL 
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
 2021-11-03 13:10:10 +03:00
Kévin Petit
43d173bd65 Add SpecConstantSubgroupMaxSize to the clspv reflection non-semantic instruction set 
Signed-off-by: Kévin Petit <kpet@free.fr>
 2021-10-25 18:33:26 +01:00
Pankaj Mistry
cec3084901 Implement header definitions for SPV_NV_bindless_texture 2021-10-21 11:17:23 -07:00
Ben Ashbaugh
442c6a62db reserve SPIR-V enum block for Intel extensions 2021-10-12 17:04:12 -07:00
John Kessenich
19e8350415
Merge pull request #245 from pmistryNV/nonconstoffset 
Define a new Image operand bit mask for non constant offsets
 2021-10-08 11:22:39 +07:00
Pankaj Mistry
e225eb0bec Define a new Image operand bit mask for non constant offsets 
For details refer to https://gitlab.khronos.org/spirv/SPIR-V/-/issues/639
As part of the commit following changes have been introduced:
1. Added a separate section in spirv xml to reserve vendor specific bit masks.
2. Added a new image operand bit mask to support non constant offsets in textureGatherOffsets as defined in GL_NV_gpu_shader5
 2021-10-06 09:54:05 -07:00
egdaniel
2c4b195695
Register Magic Num for Skia SkSL SPIR-V Generator 2021-10-01 09:34:50 -04:00
Graeme Leese
f487ad9199 Remove 'Kernel' capability from fast-math flags 
The use of these flags (the FPFastMath decoration) is already protected
by the capability, so it isn't needed to protect the individual values
as well.
 2021-09-16 10:44:39 +01:00
Marijn Suijten
b1a7c66be7 spirv.core.grammar: Remove duplicate OpArbitraryFloatPowNINTEL declaration 
An identical declaration of `OpArbitraryFloatPowNINTEL` exists just
above, with the exact same opcode and operands.
 2021-08-16 11:40:02 +02:00
Raun Krisch
e71feddb3f
Merge pull request #226 from clayengine/master 
Clay is an internal framework of Tellusim Technologies Inc.
 2021-08-11 11:26:16 -05:00
Raun Krisch
1160d54e9c
Merge pull request #233 from NikitaRudenkoIntel/opt 
Fix minor details in SPV_INTEL_optnone extension
 2021-08-11 11:23:51 -05:00
alelenv
b1d2909b95 Add support for SPV_NV_ray_tracing_motion_blur. 2021-08-10 11:01:14 -07:00
Nikita Rudenko
b6b8b6792e Fix minor details in SPV_INTEL_optnone extension 
Spec: https://github.com/intel/llvm/pull/3198
 2021-07-28 19:39:47 +03:00
Nikita Rudenko
e7b49d7fb5
Implement SPV_INTEL_optnone extension (#230) 
Spec: https://github.com/intel/llvm/pull/3198
 2021-07-28 19:46:47 +06:00
Graeme Leese
737f9dcde9 Correct grammar for LocalSizeHintId 
It is described in the spec as being the "same as LocalSizeHint mode,
but using <id> operands instead of literals", but the grammar had a
single <id> operand instead of the 3 literals for LocalSizeHint.
 2021-07-20 10:18:36 +01:00
Raun Krisch
1d4e3a7e3a
Merge pull request #227 from kpet/fix-integer-dot-product-grammar 
Fix grammar for PackedVectorFormat
 2021-07-14 11:15:34 -05:00
Mariusz Merecki
810d13d3e4 Add missing capabilities and '"version" : "None"' to QuantizationModes and OverflowModes enumerants 2021-07-09 12:25:19 +02:00
Kevin Petit
6c7e7f9f27 Fix grammar for PackedVectorFormat 
PackedVectorFormat4x8BitKHR should be enabled by the SPV_KHR_integer_dot_product
extension that first introduced it and not the DotProductInput4x8BitPackedKHR
as per the extension specification.

See http://htmlpreview.github.io/?https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/KHR/SPV_KHR_integer_dot_product.html

Signed-off-by: Kevin Petit <kevin.petit@arm.com>
 2021-07-07 19:42:53 +01:00
Raun Krisch
e3bc1b14eb
Merge pull request #223 from WyvernWang/master 
reserve value range for huawei
 2021-06-30 10:49:20 -05:00
Raun Krisch
8aec5fcf95
Merge pull request #224 from Fznamznon/upstream-debug-module-ext 
Upstream SPV_INTEL_debug_module extension
 2021-06-30 10:47:38 -05:00
Alexander Zapryagaev
5f003bd00c Clay is an internal framework of Tellusim Technologies Inc. 2021-06-28 23:38:52 -07:00
Mariya Podchishchaeva
0320c5dd2a Upstream SPV_INTEL_debug_module 
Spec https://github.com/intel/llvm/pull/3976
 2021-06-25 13:44:25 +03:00
WyvernWang
8ed0ff2c75
reserve value range 2021-06-24 20:26:05 +08:00
Ben Ashbaugh
6553701d39 add support for SPV_KHR_bit_instructions 2021-06-23 15:54:12 -07:00
Raun Krisch
f95c3b3761
Merge pull request #219 from cmarcelo/SPV_EXT_shader_atomic_float16_add 
Add header changes for SPV_EXT_shader_atomic_float16_add
 2021-06-23 10:51:49 -05:00
David Neto
e51883eceb Support SPV_KHR_integer_dot_product 
Signed-off-by: David Neto <dneto@google.com>
Signed-off-by: Kevin Petit <kevin.petit@arm.com>
Change-Id: Icd243bb9c2a6f8a40713db215a6ca5946ea7abb3
 2021-06-16 18:41:41 +01:00
Jason Ekstrand
2351f3a749 Add header changes for SPV_EXT_shader_atomic_float16_add 2021-06-16 08:45:58 -07:00
John Kessenich
7b5a2f4118 Fix two ordering problems. 2021-06-16 15:41:50 +07:00
Raun Krisch
f5417a4b66
Merge pull request #216 from mkinsner/mkinsner/allocate_vendor_extension_enum_range 
Allocate additional Intel vendor extension enum blocks
 2021-06-09 09:34:39 -07:00
Raun Krisch
bce66d87b2
Merge pull request #213 from alan-baker/SPV_KHR_subgroup_uniform_control_flow 
Support SPV_KHR_subgroup_uniform_control_flow
 2021-06-09 09:32:40 -07:00
Raun Krisch
857642c6b3
Merge pull request #217 from StuartDBrady/add-C++-for-OpenCL-lang 
Add CPP_for_OpenCL to grammar
 2021-06-09 09:32:12 -07:00
Raun Krisch
7bfb1b5329
Merge pull request #177 from MrSidims/private/MrSidims/AP 
Upstream ac_fixed and hls_float Intel extensions
 2021-06-09 09:31:41 -07:00
Stuart Brady
67da8a913f Add CPP_for_OpenCL to grammar 2021-06-09 16:03:50 +01:00
Michael Kinsner
9a4b24433b Allocate additional Intel vendor extension enum blocks 2021-06-08 16:30:58 -03:00