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Handle out-of-bounds accesses in VDCE (#4518)
It is possible that other optimization will propagate a value into an OpCompositeExtract or OpVectorShuffle instruction that is larger than the vector size. Vector DCE has to be able to handle it. Fixes https://github.com/KhronosGroup/SPIRV-Tools/issues/4513.
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@ -110,7 +110,11 @@ void VectorDCE::MarkExtractUseAsLive(const Instruction* current_inst,
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if (current_inst->NumInOperands() < 2) {
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new_item.components = live_elements;
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} else {
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new_item.components.Set(current_inst->GetSingleWordInOperand(1));
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uint32_t element_index = current_inst->GetSingleWordInOperand(1);
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uint32_t item_size = GetVectorComponentCount(operand_inst->type_id());
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if (element_index < item_size) {
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new_item.components.Set(element_index);
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}
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}
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AddItemToWorkListIfNeeded(new_item, live_components, work_list);
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}
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@ -176,10 +180,10 @@ void VectorDCE::MarkVectorShuffleUsesAsLive(
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second_operand.instruction =
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def_use_mgr->GetDef(current_item.instruction->GetSingleWordInOperand(1));
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analysis::TypeManager* type_mgr = context()->get_type_mgr();
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analysis::Vector* first_type =
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type_mgr->GetType(first_operand.instruction->type_id())->AsVector();
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uint32_t size_of_first_operand = first_type->element_count();
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uint32_t size_of_first_operand =
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GetVectorComponentCount(first_operand.instruction->type_id());
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uint32_t size_of_second_operand =
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GetVectorComponentCount(second_operand.instruction->type_id());
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for (uint32_t in_op = 2; in_op < current_item.instruction->NumInOperands();
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++in_op) {
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@ -187,7 +191,7 @@ void VectorDCE::MarkVectorShuffleUsesAsLive(
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if (current_item.components.Get(in_op - 2)) {
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if (index < size_of_first_operand) {
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first_operand.components.Set(index);
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} else {
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} else if (index - size_of_first_operand < size_of_second_operand) {
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second_operand.components.Set(index - size_of_first_operand);
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}
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}
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@ -202,7 +206,6 @@ void VectorDCE::MarkCompositeContructUsesAsLive(
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VectorDCE::LiveComponentMap* live_components,
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std::vector<VectorDCE::WorkListItem>* work_list) {
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analysis::DefUseManager* def_use_mgr = context()->get_def_use_mgr();
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analysis::TypeManager* type_mgr = context()->get_type_mgr();
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uint32_t current_component = 0;
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Instruction* current_inst = work_item.instruction;
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@ -223,8 +226,7 @@ void VectorDCE::MarkCompositeContructUsesAsLive(
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assert(HasVectorResult(op_inst));
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WorkListItem new_work_item;
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new_work_item.instruction = op_inst;
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uint32_t op_vector_size =
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type_mgr->GetType(op_inst->type_id())->AsVector()->element_count();
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uint32_t op_vector_size = GetVectorComponentCount(op_inst->type_id());
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for (uint32_t op_vector_idx = 0; op_vector_idx < op_vector_size;
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op_vector_idx++, current_component++) {
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@ -297,6 +299,18 @@ bool VectorDCE::HasScalarResult(const Instruction* inst) const {
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}
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}
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uint32_t VectorDCE::GetVectorComponentCount(uint32_t type_id) {
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assert(type_id != 0 &&
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"Trying to get the vector element count, but the type id is 0");
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analysis::TypeManager* type_mgr = context()->get_type_mgr();
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const analysis::Type* type = type_mgr->GetType(type_id);
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const analysis::Vector* vector_type = type->AsVector();
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assert(
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vector_type &&
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"Trying to get the vector element count, but the type is not a vector");
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return vector_type->element_count();
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}
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bool VectorDCE::RewriteInstructions(
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Function* function, const VectorDCE::LiveComponentMap& live_components) {
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bool modified = false;
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@ -94,12 +94,15 @@ class VectorDCE : public MemPass {
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// Returns true if the result of |inst| is a vector or a scalar.
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bool HasVectorOrScalarResult(const Instruction* inst) const;
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// Returns true if the result of |inst| is a scalar.
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// Returns true if the result of |inst| is a vector.
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bool HasVectorResult(const Instruction* inst) const;
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// Returns true if the result of |inst| is a vector.
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// Returns true if the result of |inst| is a scalar.
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bool HasScalarResult(const Instruction* inst) const;
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// Returns the number of elements in the vector type with id |type_id|.
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uint32_t GetVectorComponentCount(uint32_t type_id);
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// Adds |work_item| to |work_list| if it is not already live according to
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// |live_components|. |live_components| is updated to indicate that
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// |work_item| is now live.
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@ -1351,6 +1351,72 @@ OpFunctionEnd
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SinglePassRunAndMatch<VectorDCE>(text, true);
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}
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TEST_F(VectorDCETest, OutOfBoundsExtract) {
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// It tests that the vector DCE pass is able to handle an extract with an
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// index that is out of bounds.
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const std::string text = R"(
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; CHECK: [[undef:%\w+]] = OpUndef %v4float
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; CHECK: OpCompositeExtract %float [[undef]] 8
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OpCapability Shader
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OpMemoryModel Logical GLSL450
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OpEntryPoint Fragment %main "main" %OutColor
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OpExecutionMode %main OriginUpperLeft
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OpDecorate %OutColor Location 0
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%void = OpTypeVoid
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%10 = OpTypeFunction %void
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%float = OpTypeFloat 32
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%v4float = OpTypeVector %float 4
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%_ptr_Output_float = OpTypePointer Output %float
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%OutColor = OpVariable %_ptr_Output_float Output
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%null = OpConstantNull %v4float
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%float_1 = OpConstant %float 1
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%main = OpFunction %void None %10
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%28 = OpLabel
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%33 = OpCompositeInsert %v4float %float_1 %null 1
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%extract = OpCompositeExtract %float %33 8
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OpStore %OutColor %extract
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OpReturn
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OpFunctionEnd
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)";
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SetDisassembleOptions(SPV_BINARY_TO_TEXT_OPTION_NO_HEADER |
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SPV_BINARY_TO_TEXT_OPTION_FRIENDLY_NAMES);
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SinglePassRunAndMatch<VectorDCE>(text, false);
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}
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TEST_F(VectorDCETest, OutOfBoundsShuffle) {
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// It tests that the vector DCE pass is able to handle a shuffle with an
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// index that is out of bounds.
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const std::string text = R"(
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; CHECK: [[undef:%\w+]] = OpUndef %v4float
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; CHECK: OpVectorShuffle %v4float [[undef]] [[undef]] 9 10 11 12
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OpCapability Shader
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OpMemoryModel Logical GLSL450
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OpEntryPoint Fragment %main "main" %OutColor
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OpExecutionMode %main OriginUpperLeft
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OpDecorate %OutColor Location 0
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%void = OpTypeVoid
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%10 = OpTypeFunction %void
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%float = OpTypeFloat 32
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%v4float = OpTypeVector %float 4
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%_ptr_Output_v4float = OpTypePointer Output %v4float
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%OutColor = OpVariable %_ptr_Output_v4float Output
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%null = OpConstantNull %v4float
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%float_1 = OpConstant %float 1
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%main = OpFunction %void None %10
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%28 = OpLabel
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%33 = OpCompositeInsert %v4float %float_1 %null 1
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%shuffle = OpVectorShuffle %v4float %33 %33 9 10 11 12
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OpStore %OutColor %shuffle
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OpReturn
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OpFunctionEnd
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)";
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SetDisassembleOptions(SPV_BINARY_TO_TEXT_OPTION_NO_HEADER |
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SPV_BINARY_TO_TEXT_OPTION_FRIENDLY_NAMES);
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SinglePassRunAndMatch<VectorDCE>(text, false);
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}
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} // namespace
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} // namespace opt
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} // namespace spvtools
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