From b78f13911bfe6eda303e91ef215c87a165aae8ae Mon Sep 17 00:00:00 2001 From: Alexandre Rames Date: Fri, 1 Jul 2016 14:22:22 +0100 Subject: [PATCH] Add an `AUTHORS` file and update copyright notices. Change-Id: Ifb505e5664996c1af41e38376e58ba49864213a3 --- .clang-format | 2 +- AUTHORS | 8 ++++++++ LICENCE | 2 +- SConstruct | 2 +- benchmarks/a64/bench-branch-link-masm.cc | 2 +- benchmarks/a64/bench-branch-link.cc | 2 +- benchmarks/a64/bench-branch-masm.cc | 2 +- benchmarks/a64/bench-branch.cc | 2 +- benchmarks/a64/bench-dataop.cc | 2 +- examples/a32/abs.cc | 2 +- examples/a32/disasm-a32.cc | 2 +- examples/a32/examples.h | 2 +- examples/a32/getting-started.cc | 2 +- examples/a32/pi.cc | 2 +- examples/a32/switch.cc | 2 +- examples/a64/abs.cc | 2 +- examples/a64/add2-vectors.cc | 2 +- examples/a64/add3-double.cc | 2 +- examples/a64/add4-double.cc | 2 +- examples/a64/check-bounds.cc | 2 +- examples/a64/crc-checksums.cc | 2 +- examples/a64/custom-disassembler.cc | 2 +- examples/a64/custom-disassembler.h | 2 +- examples/a64/debugger.cc | 2 +- examples/a64/examples.h | 2 +- examples/a64/factorial-rec.cc | 2 +- examples/a64/factorial.cc | 2 +- examples/a64/getting-started.cc | 2 +- examples/a64/literal.cc | 2 +- examples/a64/neon-matrix-multiply.cc | 2 +- examples/a64/non-const-visitor.cc | 2 +- examples/a64/non-const-visitor.h | 2 +- examples/a64/sum-array.cc | 2 +- examples/a64/swap-int32.cc | 2 +- examples/a64/swap4.cc | 2 +- src/a32/assembler-a32.cc | 2 +- src/a32/assembler-a32.h | 2 +- src/a32/constants-a32.h | 2 +- src/a32/disasm-a32.cc | 2 +- src/a32/disasm-a32.h | 2 +- src/a32/instructions-a32.cc | 2 +- src/a32/instructions-a32.h | 2 +- src/a32/label-a32.h | 2 +- src/a32/macro-assembler-a32.cc | 2 +- src/a32/macro-assembler-a32.h | 2 +- src/a32/operand-a32.cc | 2 +- src/a32/operand-a32.h | 2 +- src/a64/assembler-a64.cc | 2 +- src/a64/assembler-a64.h | 2 +- src/a64/constants-a64.h | 2 +- src/a64/cpu-a64.cc | 2 +- src/a64/cpu-a64.h | 2 +- src/a64/debugger-a64.cc | 2 +- src/a64/debugger-a64.h | 2 +- src/a64/decoder-a64.cc | 2 +- src/a64/decoder-a64.h | 2 +- src/a64/disasm-a64.cc | 2 +- src/a64/disasm-a64.h | 2 +- src/a64/instructions-a64.cc | 2 +- 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test/a32/traces/assembler-cond-rd-operand-rn-a32-movs.h | 2 +- test/a32/traces/assembler-cond-rd-operand-rn-a32-mvn.h | 2 +- test/a32/traces/assembler-cond-rd-operand-rn-a32-mvns.h | 2 +- test/a32/traces/assembler-cond-rd-operand-rn-a32-sxtb.h | 2 +- test/a32/traces/assembler-cond-rd-operand-rn-a32-sxtb16.h | 2 +- test/a32/traces/assembler-cond-rd-operand-rn-a32-sxth.h | 2 +- test/a32/traces/assembler-cond-rd-operand-rn-a32-teq.h | 2 +- test/a32/traces/assembler-cond-rd-operand-rn-a32-tst.h | 2 +- test/a32/traces/assembler-cond-rd-operand-rn-a32-uxtb.h | 2 +- test/a32/traces/assembler-cond-rd-operand-rn-a32-uxtb16.h | 2 +- test/a32/traces/assembler-cond-rd-operand-rn-a32-uxth.h | 2 +- .../assembler-cond-rd-operand-rn-ror-amount-a32-sxtb.h | 2 +- .../assembler-cond-rd-operand-rn-ror-amount-a32-sxtb16.h | 2 +- .../assembler-cond-rd-operand-rn-ror-amount-a32-sxth.h | 2 +- .../assembler-cond-rd-operand-rn-ror-amount-a32-uxtb.h | 2 +- .../assembler-cond-rd-operand-rn-ror-amount-a32-uxtb16.h | 2 +- .../assembler-cond-rd-operand-rn-ror-amount-a32-uxth.h | 2 +- .../assembler-cond-rd-operand-rn-ror-amount-t32-sxtb.h | 2 +- .../assembler-cond-rd-operand-rn-ror-amount-t32-sxtb16.h | 2 +- .../assembler-cond-rd-operand-rn-ror-amount-t32-sxth.h | 2 +- .../assembler-cond-rd-operand-rn-ror-amount-t32-uxtb.h | 2 +- .../assembler-cond-rd-operand-rn-ror-amount-t32-uxtb16.h | 2 +- .../assembler-cond-rd-operand-rn-ror-amount-t32-uxth.h | 2 +- ...embler-cond-rd-operand-rn-shift-amount-1to31-a32-cmn.h | 2 +- ...embler-cond-rd-operand-rn-shift-amount-1to31-a32-cmp.h | 2 +- ...embler-cond-rd-operand-rn-shift-amount-1to31-a32-mov.h | 2 +- ...mbler-cond-rd-operand-rn-shift-amount-1to31-a32-movs.h | 2 +- ...embler-cond-rd-operand-rn-shift-amount-1to31-a32-mvn.h | 2 +- ...mbler-cond-rd-operand-rn-shift-amount-1to31-a32-mvns.h | 2 +- ...embler-cond-rd-operand-rn-shift-amount-1to31-a32-teq.h | 2 +- ...embler-cond-rd-operand-rn-shift-amount-1to31-a32-tst.h | 2 +- ...embler-cond-rd-operand-rn-shift-amount-1to31-t32-cmn.h | 2 +- ...embler-cond-rd-operand-rn-shift-amount-1to31-t32-cmp.h | 2 +- ...rd-operand-rn-shift-amount-1to31-t32-in-it-block-mov.h | 2 +- ...embler-cond-rd-operand-rn-shift-amount-1to31-t32-mov.h | 2 +- ...mbler-cond-rd-operand-rn-shift-amount-1to31-t32-movs.h | 2 +- ...embler-cond-rd-operand-rn-shift-amount-1to31-t32-mvn.h | 2 +- ...mbler-cond-rd-operand-rn-shift-amount-1to31-t32-mvns.h | 2 +- ...embler-cond-rd-operand-rn-shift-amount-1to31-t32-teq.h | 2 +- ...embler-cond-rd-operand-rn-shift-amount-1to31-t32-tst.h | 2 +- ...embler-cond-rd-operand-rn-shift-amount-1to32-a32-cmn.h | 2 +- ...embler-cond-rd-operand-rn-shift-amount-1to32-a32-cmp.h | 2 +- ...embler-cond-rd-operand-rn-shift-amount-1to32-a32-mov.h | 2 +- ...mbler-cond-rd-operand-rn-shift-amount-1to32-a32-movs.h | 2 +- ...embler-cond-rd-operand-rn-shift-amount-1to32-a32-mvn.h | 2 +- ...mbler-cond-rd-operand-rn-shift-amount-1to32-a32-mvns.h | 2 +- ...embler-cond-rd-operand-rn-shift-amount-1to32-a32-teq.h | 2 +- ...embler-cond-rd-operand-rn-shift-amount-1to32-a32-tst.h | 2 +- ...embler-cond-rd-operand-rn-shift-amount-1to32-t32-cmn.h | 2 +- ...embler-cond-rd-operand-rn-shift-amount-1to32-t32-cmp.h | 2 +- ...rd-operand-rn-shift-amount-1to32-t32-in-it-block-mov.h | 2 +- ...embler-cond-rd-operand-rn-shift-amount-1to32-t32-mov.h | 2 +- ...mbler-cond-rd-operand-rn-shift-amount-1to32-t32-movs.h | 2 +- ...embler-cond-rd-operand-rn-shift-amount-1to32-t32-mvn.h | 2 +- ...mbler-cond-rd-operand-rn-shift-amount-1to32-t32-mvns.h | 2 +- ...embler-cond-rd-operand-rn-shift-amount-1to32-t32-teq.h | 2 +- ...embler-cond-rd-operand-rn-shift-amount-1to32-t32-tst.h | 2 +- .../assembler-cond-rd-operand-rn-shift-rs-a32-cmn.h | 2 +- .../assembler-cond-rd-operand-rn-shift-rs-a32-cmp.h | 2 +- .../assembler-cond-rd-operand-rn-shift-rs-a32-mov.h | 2 +- .../assembler-cond-rd-operand-rn-shift-rs-a32-movs.h | 2 +- .../assembler-cond-rd-operand-rn-shift-rs-a32-mvn.h | 2 +- .../assembler-cond-rd-operand-rn-shift-rs-a32-mvns.h | 2 +- .../assembler-cond-rd-operand-rn-shift-rs-a32-teq.h | 2 +- .../assembler-cond-rd-operand-rn-shift-rs-a32-tst.h | 2 +- ...bler-cond-rd-operand-rn-shift-rs-t32-in-it-block-mov.h | 2 +- .../assembler-cond-rd-operand-rn-shift-rs-t32-mov.h | 2 +- .../assembler-cond-rd-operand-rn-shift-rs-t32-movs.h | 2 +- ...-rd-operand-rn-shift-rs-t32-narrow-out-it-block-movs.h | 2 +- test/a32/traces/assembler-cond-rd-operand-rn-t32-cmn.h | 2 +- test/a32/traces/assembler-cond-rd-operand-rn-t32-cmp.h | 2 +- ...erand-rn-t32-identical-low-registers-in-it-block-mvn.h | 2 +- .../assembler-cond-rd-operand-rn-t32-in-it-block-cmp.h | 2 +- .../assembler-cond-rd-operand-rn-t32-in-it-block-mov.h | 2 +- ...cond-rd-operand-rn-t32-low-registers-in-it-block-cmn.h | 2 +- ...cond-rd-operand-rn-t32-low-registers-in-it-block-tst.h | 2 +- test/a32/traces/assembler-cond-rd-operand-rn-t32-mov.h | 2 +- test/a32/traces/assembler-cond-rd-operand-rn-t32-movs.h | 2 +- test/a32/traces/assembler-cond-rd-operand-rn-t32-mvn.h | 2 +- test/a32/traces/assembler-cond-rd-operand-rn-t32-mvns.h | 2 +- test/a32/traces/assembler-cond-rd-operand-rn-t32-sxtb.h | 2 +- test/a32/traces/assembler-cond-rd-operand-rn-t32-sxtb16.h | 2 +- test/a32/traces/assembler-cond-rd-operand-rn-t32-sxth.h | 2 +- test/a32/traces/assembler-cond-rd-operand-rn-t32-teq.h | 2 +- test/a32/traces/assembler-cond-rd-operand-rn-t32-tst.h | 2 +- test/a32/traces/assembler-cond-rd-operand-rn-t32-uxtb.h | 2 +- test/a32/traces/assembler-cond-rd-operand-rn-t32-uxtb16.h | 2 +- test/a32/traces/assembler-cond-rd-operand-rn-t32-uxth.h | 2 +- .../traces/assembler-cond-rd-pc-operand-imm12-t32-add.h | 2 +- .../traces/assembler-cond-rd-pc-operand-imm12-t32-addw.h | 2 +- .../traces/assembler-cond-rd-pc-operand-imm12-t32-sub.h | 2 +- .../traces/assembler-cond-rd-pc-operand-imm8-t32-add.h | 2 +- test/a32/traces/assembler-cond-rd-rn-a32-clz.h | 2 +- test/a32/traces/assembler-cond-rd-rn-a32-rbit.h | 2 +- test/a32/traces/assembler-cond-rd-rn-a32-rev.h | 2 +- test/a32/traces/assembler-cond-rd-rn-a32-rev16.h | 2 +- test/a32/traces/assembler-cond-rd-rn-a32-revsh.h | 2 +- test/a32/traces/assembler-cond-rd-rn-a32-rrx.h | 2 +- test/a32/traces/assembler-cond-rd-rn-a32-rrxs.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-a32-adc.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-a32-adcs.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-a32-add.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-a32-adds.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-a32-and.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-a32-ands.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-a32-bic.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-a32-bics.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-a32-eor.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-a32-eors.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-a32-orr.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-a32-orrs.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-a32-rsb.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-a32-rsbs.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-a32-rsc.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-a32-rscs.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-a32-sbc.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-a32-sbcs.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-a32-sub.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-a32-subs.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-t32-adc.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-t32-adcs.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-t32-add.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-t32-adds.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-t32-and.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-t32-ands.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-t32-bic.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-t32-bics.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-t32-eor.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-t32-eors.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-t32-orn.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-t32-orns.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-t32-orr.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-t32-orrs.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-t32-rsb.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-t32-rsbs.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-t32-sbc.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-t32-sbcs.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-t32-sub.h | 2 +- .../traces/assembler-cond-rd-rn-operand-const-t32-subs.h | 2 +- .../traces/assembler-cond-rd-rn-operand-imm12-t32-add.h | 2 +- .../traces/assembler-cond-rd-rn-operand-imm12-t32-addw.h | 2 +- .../traces/assembler-cond-rd-rn-operand-imm12-t32-sub.h | 2 +- .../traces/assembler-cond-rd-rn-operand-imm12-t32-subw.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-adc.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-a32-adcs.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-add.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-a32-adds.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-and.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-a32-ands.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-asr.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-a32-asrs.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-bic.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-a32-bics.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-eor.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-a32-eors.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsl.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsls.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsr.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsrs.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-orr.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-a32-orrs.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-ror.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-a32-rors.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsb.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsbs.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsc.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-a32-rscs.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sbc.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-a32-sbcs.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sub.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-a32-subs.h | 2 +- .../traces/assembler-cond-rd-rn-operand-rm-a32-sxtab.h | 2 +- .../traces/assembler-cond-rd-rn-operand-rm-a32-sxtab16.h | 2 +- .../traces/assembler-cond-rd-rn-operand-rm-a32-sxtah.h | 2 +- .../traces/assembler-cond-rd-rn-operand-rm-a32-uxtab.h | 2 +- .../traces/assembler-cond-rd-rn-operand-rm-a32-uxtab16.h | 2 +- .../traces/assembler-cond-rd-rn-operand-rm-a32-uxtah.h | 2 +- ...assembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtab.h | 2 +- ...sembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtab16.h | 2 +- ...assembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtah.h | 2 +- ...assembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtab.h | 2 +- ...sembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtab16.h | 2 +- ...assembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtah.h | 2 +- ...assembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtab.h | 2 +- ...sembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtab16.h | 2 +- ...assembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtah.h | 2 +- ...assembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtab.h | 2 +- ...sembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtab16.h | 2 +- ...assembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtah.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adc.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adcs.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-add.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adds.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-and.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to31-a32-ands.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bic.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bics.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eor.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eors.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orr.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orrs.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsb.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsbs.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsc.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rscs.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbc.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbcs.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sub.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to31-a32-subs.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adc.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adcs.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-add.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adds.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-and.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to31-t32-ands.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bic.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bics.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eor.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eors.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orn.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orns.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orr.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orrs.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsb.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsbs.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbc.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbcs.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sub.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to31-t32-subs.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adc.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adcs.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-add.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adds.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-and.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to32-a32-ands.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bic.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bics.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eor.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eors.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orr.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orrs.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsb.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsbs.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsc.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rscs.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbc.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbcs.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sub.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to32-a32-subs.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adc.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adcs.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-add.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adds.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-and.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to32-t32-ands.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bic.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bics.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eor.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eors.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orn.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orns.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orr.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orrs.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsb.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsbs.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbc.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbcs.h | 2 +- ...ler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sub.h | 2 +- ...er-cond-rd-rn-operand-rm-shift-amount-1to32-t32-subs.h | 2 +- .../assembler-cond-rd-rn-operand-rm-shift-rs-a32-adc.h | 2 +- .../assembler-cond-rd-rn-operand-rm-shift-rs-a32-adcs.h | 2 +- .../assembler-cond-rd-rn-operand-rm-shift-rs-a32-add.h | 2 +- .../assembler-cond-rd-rn-operand-rm-shift-rs-a32-adds.h | 2 +- .../assembler-cond-rd-rn-operand-rm-shift-rs-a32-and.h | 2 +- .../assembler-cond-rd-rn-operand-rm-shift-rs-a32-ands.h | 2 +- .../assembler-cond-rd-rn-operand-rm-shift-rs-a32-bic.h | 2 +- .../assembler-cond-rd-rn-operand-rm-shift-rs-a32-bics.h | 2 +- .../assembler-cond-rd-rn-operand-rm-shift-rs-a32-eor.h | 2 +- .../assembler-cond-rd-rn-operand-rm-shift-rs-a32-eors.h | 2 +- .../assembler-cond-rd-rn-operand-rm-shift-rs-a32-orr.h | 2 +- .../assembler-cond-rd-rn-operand-rm-shift-rs-a32-orrs.h | 2 +- .../assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsb.h | 2 +- .../assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsbs.h | 2 +- .../assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsc.h | 2 +- .../assembler-cond-rd-rn-operand-rm-shift-rs-a32-rscs.h | 2 +- .../assembler-cond-rd-rn-operand-rm-shift-rs-a32-sbc.h | 2 +- .../assembler-cond-rd-rn-operand-rm-shift-rs-a32-sbcs.h | 2 +- .../assembler-cond-rd-rn-operand-rm-shift-rs-a32-sub.h | 2 +- .../assembler-cond-rd-rn-operand-rm-shift-rs-a32-subs.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-adc.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-t32-adcs.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-add.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-t32-adds.h | 2 +- ...er-cond-rd-rn-operand-rm-t32-all-low-in-it-block-add.h | 2 +- ...er-cond-rd-rn-operand-rm-t32-all-low-in-it-block-sub.h | 2 +- ...d-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-adc.h | 2 +- ...d-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-and.h | 2 +- ...d-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-asr.h | 2 +- ...d-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-bic.h | 2 +- ...d-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-eor.h | 2 +- ...d-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-lsl.h | 2 +- ...d-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-lsr.h | 2 +- ...d-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-orr.h | 2 +- ...d-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-ror.h | 2 +- ...d-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-sbc.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-and.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-t32-ands.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-asr.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-t32-asrs.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-bic.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-t32-bics.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-eor.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-t32-eors.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsl.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsls.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsr.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsrs.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orn.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-t32-orns.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orr.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-t32-orrs.h | 2 +- ...r-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block-add.h | 2 +- ...-rd-rn-operand-rm-t32-rd-is-rn-is-sp-in-it-block-add.h | 2 +- ...r-cond-rd-rn-operand-rm-t32-rn-is-sp-in-it-block-add.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-ror.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-t32-rors.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rsb.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-t32-rsbs.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sbc.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-t32-sbcs.h | 2 +- test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sub.h | 2 +- .../a32/traces/assembler-cond-rd-rn-operand-rm-t32-subs.h | 2 +- .../traces/assembler-cond-rd-rn-operand-rm-t32-sxtab.h | 2 +- .../traces/assembler-cond-rd-rn-operand-rm-t32-sxtab16.h | 2 +- .../traces/assembler-cond-rd-rn-operand-rm-t32-sxtah.h | 2 +- .../traces/assembler-cond-rd-rn-operand-rm-t32-uxtab.h | 2 +- .../traces/assembler-cond-rd-rn-operand-rm-t32-uxtab16.h | 2 +- .../traces/assembler-cond-rd-rn-operand-rm-t32-uxtah.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-mul.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-muls.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd16.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd8.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-qasx.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-qdadd.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-qdsub.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-qsax.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub16.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub8.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-sadd16.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-sadd8.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-sasx.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-sdiv.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-sel.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-shadd16.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-shadd8.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-shasx.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-shsax.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-shsub16.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-shsub8.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-smmul.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-smmulr.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-smuad.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-smuadx.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-smulbb.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-smulbt.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-smultb.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-smultt.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-smulwb.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-smulwt.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-smusd.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-smusdx.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-ssax.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-ssub16.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-ssub8.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-uadd16.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-uadd8.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-uasx.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-udiv.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-uhadd16.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-uhadd8.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-uhasx.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsax.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsub16.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsub8.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-uqadd16.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-uqadd8.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-uqasx.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsax.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsub16.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsub8.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-usad8.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-usax.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-usub16.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-a32-usub8.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-mul.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd16.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd8.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-qasx.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-qdadd.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-qdsub.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-qsax.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub16.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub8.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-sadd16.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-sadd8.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-sasx.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-sdiv.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-sel.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-shadd16.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-shadd8.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-shasx.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-shsax.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-shsub16.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-shsub8.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-smmul.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-smmulr.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-smuad.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-smuadx.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-smulbb.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-smulbt.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-smultb.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-smultt.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-smulwb.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-smulwt.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-smusd.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-smusdx.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-ssax.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-ssub16.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-ssub8.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-uadd16.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-uadd8.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-uasx.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-udiv.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-uhadd16.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-uhadd8.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-uhasx.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsax.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsub16.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsub8.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-uqadd16.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-uqadd8.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-uqasx.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsax.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsub16.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsub8.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-usad8.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-usax.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-usub16.h | 2 +- test/a32/traces/assembler-cond-rd-rn-rm-t32-usub8.h | 2 +- test/a32/traces/assembler-cond-rd-rn-t32-clz.h | 2 +- test/a32/traces/assembler-cond-rd-rn-t32-rbit.h | 2 +- test/a32/traces/assembler-cond-rd-rn-t32-rev.h | 2 +- test/a32/traces/assembler-cond-rd-rn-t32-rev16.h | 2 +- test/a32/traces/assembler-cond-rd-rn-t32-revsh.h | 2 +- test/a32/traces/assembler-cond-rd-rn-t32-rrx.h | 2 +- test/a32/traces/assembler-cond-rd-rn-t32-rrxs.h | 2 +- .../traces/assembler-cond-rd-sp-operand-imm8-t32-add.h | 2 +- .../traces/assembler-cond-rdlow-operand-imm8-t32-cmp.h | 2 +- ...ssembler-cond-rdlow-operand-imm8-t32-in-it-block-cmp.h | 2 +- ...ssembler-cond-rdlow-operand-imm8-t32-in-it-block-mov.h | 2 +- .../traces/assembler-cond-rdlow-operand-imm8-t32-mov.h | 2 +- .../traces/assembler-cond-rdlow-operand-imm8-t32-movs.h | 2 +- ...ler-cond-rdlow-rnlow-operand-immediate-t32-imm3-adds.h | 2 +- ...low-rnlow-operand-immediate-t32-imm3-in-it-block-add.h | 2 +- ...low-rnlow-operand-immediate-t32-imm3-in-it-block-sub.h | 2 +- ...ler-cond-rdlow-rnlow-operand-immediate-t32-imm3-subs.h | 2 +- ...ler-cond-rdlow-rnlow-operand-immediate-t32-imm8-adds.h | 2 +- ...low-rnlow-operand-immediate-t32-imm8-in-it-block-add.h | 2 +- ...low-rnlow-operand-immediate-t32-imm8-in-it-block-sub.h | 2 +- ...ler-cond-rdlow-rnlow-operand-immediate-t32-imm8-subs.h | 2 +- ...low-rnlow-operand-immediate-t32-zero-in-it-block-rsb.h | 2 +- ...ler-cond-rdlow-rnlow-operand-immediate-t32-zero-rsbs.h | 2 +- ...assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block-mul.h | 2 +- .../traces/assembler-cond-rdlow-rnlow-rmlow-t32-muls.h | 2 +- .../traces/assembler-cond-sp-sp-operand-imm7-t32-add.h | 2 +- .../traces/assembler-cond-sp-sp-operand-imm7-t32-sub.h | 2 +- test/a32/traces/assembler-rd-rn-rm-a32-crc32b.h | 2 +- test/a32/traces/assembler-rd-rn-rm-a32-crc32cb.h | 2 +- test/a32/traces/assembler-rd-rn-rm-a32-crc32ch.h | 2 +- test/a32/traces/assembler-rd-rn-rm-a32-crc32cw.h | 2 +- test/a32/traces/assembler-rd-rn-rm-a32-crc32h.h | 2 +- test/a32/traces/assembler-rd-rn-rm-a32-crc32w.h | 2 +- test/a32/traces/assembler-rd-rn-rm-t32-crc32b.h | 2 +- test/a32/traces/assembler-rd-rn-rm-t32-crc32cb.h | 2 +- test/a32/traces/assembler-rd-rn-rm-t32-crc32ch.h | 2 +- test/a32/traces/assembler-rd-rn-rm-t32-crc32cw.h | 2 +- test/a32/traces/assembler-rd-rn-rm-t32-crc32h.h | 2 +- test/a32/traces/assembler-rd-rn-rm-t32-crc32w.h | 2 +- .../simulator-cond-rd-memop-immediate-512-a32-ldrh.h | 2 +- .../simulator-cond-rd-memop-immediate-512-a32-ldrsb.h | 2 +- .../simulator-cond-rd-memop-immediate-512-a32-ldrsh.h | 2 +- .../simulator-cond-rd-memop-immediate-512-a32-strh.h | 2 +- .../simulator-cond-rd-memop-immediate-8192-a32-ldr.h | 2 +- .../simulator-cond-rd-memop-immediate-8192-a32-ldrb.h | 2 +- .../simulator-cond-rd-memop-immediate-8192-a32-str.h | 2 +- .../simulator-cond-rd-memop-immediate-8192-a32-strb.h | 2 +- test/a32/traces/simulator-cond-rd-memop-rs-a32-ldr.h | 2 +- test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrb.h | 2 +- test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrh.h | 2 +- test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrsb.h | 2 +- test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrsh.h | 2 +- test/a32/traces/simulator-cond-rd-memop-rs-a32-str.h | 2 +- test/a32/traces/simulator-cond-rd-memop-rs-a32-strb.h | 2 +- test/a32/traces/simulator-cond-rd-memop-rs-a32-strh.h | 2 +- ...imulator-cond-rd-memop-rs-shift-amount-1to31-a32-ldr.h | 2 +- ...mulator-cond-rd-memop-rs-shift-amount-1to31-a32-ldrb.h | 2 +- ...imulator-cond-rd-memop-rs-shift-amount-1to31-a32-str.h | 2 +- ...mulator-cond-rd-memop-rs-shift-amount-1to31-a32-strb.h | 2 +- ...imulator-cond-rd-memop-rs-shift-amount-1to32-a32-ldr.h | 2 +- ...mulator-cond-rd-memop-rs-shift-amount-1to32-a32-ldrb.h | 2 +- ...imulator-cond-rd-memop-rs-shift-amount-1to32-a32-str.h | 2 +- ...mulator-cond-rd-memop-rs-shift-amount-1to32-a32-strb.h | 2 +- test/a32/traces/simulator-cond-rd-operand-const-a32-cmn.h | 2 +- test/a32/traces/simulator-cond-rd-operand-const-a32-cmp.h | 2 +- test/a32/traces/simulator-cond-rd-operand-const-a32-mov.h | 2 +- .../a32/traces/simulator-cond-rd-operand-const-a32-movs.h | 2 +- test/a32/traces/simulator-cond-rd-operand-const-a32-mvn.h | 2 +- .../a32/traces/simulator-cond-rd-operand-const-a32-mvns.h | 2 +- test/a32/traces/simulator-cond-rd-operand-const-a32-teq.h | 2 +- test/a32/traces/simulator-cond-rd-operand-const-a32-tst.h | 2 +- test/a32/traces/simulator-cond-rd-operand-const-t32-cmn.h | 2 +- test/a32/traces/simulator-cond-rd-operand-const-t32-cmp.h | 2 +- test/a32/traces/simulator-cond-rd-operand-const-t32-mov.h | 2 +- .../a32/traces/simulator-cond-rd-operand-const-t32-movs.h | 2 +- test/a32/traces/simulator-cond-rd-operand-const-t32-mvn.h | 2 +- .../a32/traces/simulator-cond-rd-operand-const-t32-mvns.h | 2 +- test/a32/traces/simulator-cond-rd-operand-const-t32-teq.h | 2 +- test/a32/traces/simulator-cond-rd-operand-const-t32-tst.h | 2 +- test/a32/traces/simulator-cond-rd-operand-imm16-t32-mov.h | 2 +- .../a32/traces/simulator-cond-rd-operand-imm16-t32-movt.h | 2 +- .../a32/traces/simulator-cond-rd-operand-imm16-t32-movw.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-a32-cmn.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-a32-cmp.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-a32-mov.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-a32-movs.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-a32-mvn.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-a32-mvns.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-a32-sxtb.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-a32-sxtb16.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-a32-sxth.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-a32-teq.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-a32-tst.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-a32-uxtb.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-a32-uxtb16.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-a32-uxth.h | 2 +- .../simulator-cond-rd-operand-rn-ror-amount-a32-sxtb.h | 2 +- .../simulator-cond-rd-operand-rn-ror-amount-a32-sxtb16.h | 2 +- .../simulator-cond-rd-operand-rn-ror-amount-a32-sxth.h | 2 +- .../simulator-cond-rd-operand-rn-ror-amount-a32-uxtb.h | 2 +- .../simulator-cond-rd-operand-rn-ror-amount-a32-uxtb16.h | 2 +- .../simulator-cond-rd-operand-rn-ror-amount-a32-uxth.h | 2 +- .../simulator-cond-rd-operand-rn-ror-amount-t32-sxtb.h | 2 +- .../simulator-cond-rd-operand-rn-ror-amount-t32-sxtb16.h | 2 +- .../simulator-cond-rd-operand-rn-ror-amount-t32-sxth.h | 2 +- .../simulator-cond-rd-operand-rn-ror-amount-t32-uxtb.h | 2 +- .../simulator-cond-rd-operand-rn-ror-amount-t32-uxtb16.h | 2 +- .../simulator-cond-rd-operand-rn-ror-amount-t32-uxth.h | 2 +- ...ulator-cond-rd-operand-rn-shift-amount-1to31-a32-cmn.h | 2 +- ...ulator-cond-rd-operand-rn-shift-amount-1to31-a32-cmp.h | 2 +- ...ulator-cond-rd-operand-rn-shift-amount-1to31-a32-mov.h | 2 +- ...lator-cond-rd-operand-rn-shift-amount-1to31-a32-movs.h | 2 +- ...ulator-cond-rd-operand-rn-shift-amount-1to31-a32-mvn.h | 2 +- ...lator-cond-rd-operand-rn-shift-amount-1to31-a32-mvns.h | 2 +- ...ulator-cond-rd-operand-rn-shift-amount-1to31-a32-teq.h | 2 +- ...ulator-cond-rd-operand-rn-shift-amount-1to31-a32-tst.h | 2 +- ...ulator-cond-rd-operand-rn-shift-amount-1to31-t32-cmn.h | 2 +- ...ulator-cond-rd-operand-rn-shift-amount-1to31-t32-cmp.h | 2 +- ...ulator-cond-rd-operand-rn-shift-amount-1to31-t32-mov.h | 2 +- ...lator-cond-rd-operand-rn-shift-amount-1to31-t32-movs.h | 2 +- ...ulator-cond-rd-operand-rn-shift-amount-1to31-t32-mvn.h | 2 +- ...lator-cond-rd-operand-rn-shift-amount-1to31-t32-mvns.h | 2 +- ...ulator-cond-rd-operand-rn-shift-amount-1to31-t32-teq.h | 2 +- ...ulator-cond-rd-operand-rn-shift-amount-1to31-t32-tst.h | 2 +- ...ulator-cond-rd-operand-rn-shift-amount-1to32-a32-cmn.h | 2 +- ...ulator-cond-rd-operand-rn-shift-amount-1to32-a32-cmp.h | 2 +- ...ulator-cond-rd-operand-rn-shift-amount-1to32-a32-mov.h | 2 +- ...lator-cond-rd-operand-rn-shift-amount-1to32-a32-movs.h | 2 +- ...ulator-cond-rd-operand-rn-shift-amount-1to32-a32-mvn.h | 2 +- ...lator-cond-rd-operand-rn-shift-amount-1to32-a32-mvns.h | 2 +- ...ulator-cond-rd-operand-rn-shift-amount-1to32-a32-teq.h | 2 +- ...ulator-cond-rd-operand-rn-shift-amount-1to32-a32-tst.h | 2 +- ...ulator-cond-rd-operand-rn-shift-amount-1to32-t32-cmn.h | 2 +- ...ulator-cond-rd-operand-rn-shift-amount-1to32-t32-cmp.h | 2 +- ...ulator-cond-rd-operand-rn-shift-amount-1to32-t32-mov.h | 2 +- ...lator-cond-rd-operand-rn-shift-amount-1to32-t32-movs.h | 2 +- ...ulator-cond-rd-operand-rn-shift-amount-1to32-t32-mvn.h | 2 +- ...lator-cond-rd-operand-rn-shift-amount-1to32-t32-mvns.h | 2 +- ...ulator-cond-rd-operand-rn-shift-amount-1to32-t32-teq.h | 2 +- ...ulator-cond-rd-operand-rn-shift-amount-1to32-t32-tst.h | 2 +- .../simulator-cond-rd-operand-rn-shift-rs-a32-cmn.h | 2 +- .../simulator-cond-rd-operand-rn-shift-rs-a32-cmp.h | 2 +- .../simulator-cond-rd-operand-rn-shift-rs-a32-mov.h | 2 +- .../simulator-cond-rd-operand-rn-shift-rs-a32-movs.h | 2 +- .../simulator-cond-rd-operand-rn-shift-rs-a32-mvn.h | 2 +- .../simulator-cond-rd-operand-rn-shift-rs-a32-mvns.h | 2 +- .../simulator-cond-rd-operand-rn-shift-rs-a32-teq.h | 2 +- .../simulator-cond-rd-operand-rn-shift-rs-a32-tst.h | 2 +- .../simulator-cond-rd-operand-rn-shift-rs-t32-mov.h | 2 +- .../simulator-cond-rd-operand-rn-shift-rs-t32-movs.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-t32-cmn.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-t32-cmp.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-t32-mov.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-t32-movs.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-t32-mvn.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-t32-mvns.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-t32-sxtb.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-t32-sxtb16.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-t32-sxth.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-t32-teq.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-t32-tst.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-t32-uxtb.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-t32-uxtb16.h | 2 +- test/a32/traces/simulator-cond-rd-operand-rn-t32-uxth.h | 2 +- test/a32/traces/simulator-cond-rd-rn-a32-clz.h | 2 +- test/a32/traces/simulator-cond-rd-rn-a32-rbit.h | 2 +- test/a32/traces/simulator-cond-rd-rn-a32-rev.h | 2 +- test/a32/traces/simulator-cond-rd-rn-a32-rev16.h | 2 +- test/a32/traces/simulator-cond-rd-rn-a32-revsh.h | 2 +- test/a32/traces/simulator-cond-rd-rn-a32-rrx.h | 2 +- test/a32/traces/simulator-cond-rd-rn-a32-rrxs.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-a32-adc.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-a32-adcs.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-a32-add.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-a32-adds.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-a32-and.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-a32-ands.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-a32-bic.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-a32-bics.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-a32-eor.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-a32-eors.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-a32-orr.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-a32-orrs.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-a32-rsb.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-a32-rsbs.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-a32-rsc.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-a32-rscs.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-a32-sbc.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-a32-sbcs.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-a32-sub.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-a32-subs.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-t32-adc.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-t32-adcs.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-t32-add.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-t32-adds.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-t32-and.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-t32-ands.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-t32-bic.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-t32-bics.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-t32-eor.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-t32-eors.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-t32-orn.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-t32-orns.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-t32-orr.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-t32-orrs.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-t32-rsb.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-t32-rsbs.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-t32-sbc.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-t32-sbcs.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-t32-sub.h | 2 +- .../traces/simulator-cond-rd-rn-operand-const-t32-subs.h | 2 +- .../traces/simulator-cond-rd-rn-operand-imm12-t32-add.h | 2 +- .../traces/simulator-cond-rd-rn-operand-imm12-t32-addw.h | 2 +- .../traces/simulator-cond-rd-rn-operand-imm12-t32-sub.h | 2 +- .../traces/simulator-cond-rd-rn-operand-imm12-t32-subw.h | 2 +- test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-adc.h | 2 +- .../a32/traces/simulator-cond-rd-rn-operand-rm-a32-adcs.h | 2 +- test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-add.h | 2 +- .../a32/traces/simulator-cond-rd-rn-operand-rm-a32-adds.h | 2 +- test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-and.h | 2 +- .../a32/traces/simulator-cond-rd-rn-operand-rm-a32-ands.h | 2 +- test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-asr.h | 2 +- .../a32/traces/simulator-cond-rd-rn-operand-rm-a32-asrs.h | 2 +- test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-bic.h | 2 +- .../a32/traces/simulator-cond-rd-rn-operand-rm-a32-bics.h | 2 +- test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-eor.h | 2 +- .../a32/traces/simulator-cond-rd-rn-operand-rm-a32-eors.h | 2 +- test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsl.h | 2 +- .../a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsls.h | 2 +- test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsr.h | 2 +- .../a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsrs.h | 2 +- test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-orr.h | 2 +- .../a32/traces/simulator-cond-rd-rn-operand-rm-a32-orrs.h | 2 +- test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-ror.h | 2 +- .../a32/traces/simulator-cond-rd-rn-operand-rm-a32-rors.h | 2 +- test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsb.h | 2 +- .../a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsbs.h | 2 +- test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsc.h | 2 +- .../a32/traces/simulator-cond-rd-rn-operand-rm-a32-rscs.h | 2 +- test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sbc.h | 2 +- .../a32/traces/simulator-cond-rd-rn-operand-rm-a32-sbcs.h | 2 +- test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sub.h | 2 +- .../a32/traces/simulator-cond-rd-rn-operand-rm-a32-subs.h | 2 +- .../traces/simulator-cond-rd-rn-operand-rm-a32-sxtab.h | 2 +- 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test/a32/traces/simulator-cond-rd-rn-rm-a32-uhsub8.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-a32-uqadd16.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-a32-uqadd8.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-a32-uqasx.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsax.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsub16.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsub8.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-a32-usad8.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-a32-usax.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-a32-usub16.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-a32-usub8.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sadd16.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sadd8.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sasx.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssax.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssub16.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssub8.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uadd16.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uadd8.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uasx.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usax.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usub16.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usub8.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-mul.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qadd.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qdadd.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qdsub.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qsub.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd16.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd8.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-qasx.h | 2 +- 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2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-shsub8.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-smmul.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-smmulr.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-smuad.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-smuadx.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-smulbb.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-smulbt.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-smultb.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-smultt.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-smulwb.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-smulwt.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-smusd.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-smusdx.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-ssax.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-ssub16.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-ssub8.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-uadd16.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-uadd8.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-uasx.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-udiv.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-uhadd16.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-uhadd8.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-uhasx.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsax.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsub16.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsub8.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-uqadd16.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-uqadd8.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-uqasx.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsax.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsub16.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsub8.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-usad8.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-usax.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-usub16.h | 2 +- test/a32/traces/simulator-cond-rd-rn-rm-t32-usub8.h | 2 +- test/a32/traces/simulator-cond-rd-rn-t32-clz.h | 2 +- test/a32/traces/simulator-cond-rd-rn-t32-rbit.h | 2 +- test/a32/traces/simulator-cond-rd-rn-t32-rev.h | 2 +- test/a32/traces/simulator-cond-rd-rn-t32-rev16.h | 2 +- test/a32/traces/simulator-cond-rd-rn-t32-revsh.h | 2 +- test/a32/traces/simulator-cond-rd-rn-t32-rrx.h | 2 +- test/a32/traces/simulator-cond-rd-rn-t32-rrxs.h | 2 +- .../traces/simulator-cond-rdlow-operand-imm8-t32-cmp.h | 2 +- .../traces/simulator-cond-rdlow-operand-imm8-t32-mov.h | 2 +- .../traces/simulator-cond-rdlow-operand-imm8-t32-movs.h | 2 +- ...simulator-cond-rdlow-rnlow-operand-immediate-t32-add.h | 2 +- ...imulator-cond-rdlow-rnlow-operand-immediate-t32-adds.h | 2 +- ...simulator-cond-rdlow-rnlow-operand-immediate-t32-rsb.h | 2 +- ...imulator-cond-rdlow-rnlow-operand-immediate-t32-rsbs.h | 2 +- ...simulator-cond-rdlow-rnlow-operand-immediate-t32-sub.h | 2 +- ...imulator-cond-rdlow-rnlow-operand-immediate-t32-subs.h | 2 +- .../a32/traces/simulator-cond-rdlow-rnlow-rmlow-t32-mul.h | 2 +- .../traces/simulator-cond-rdlow-rnlow-rmlow-t32-muls.h | 2 +- test/a32/traces/simulator-rd-rn-rm-a32-crc32b.h | 2 +- test/a32/traces/simulator-rd-rn-rm-a32-crc32cb.h | 2 +- test/a32/traces/simulator-rd-rn-rm-a32-crc32ch.h | 2 +- test/a32/traces/simulator-rd-rn-rm-a32-crc32cw.h | 2 +- test/a32/traces/simulator-rd-rn-rm-a32-crc32h.h | 2 +- test/a32/traces/simulator-rd-rn-rm-a32-crc32w.h | 2 +- test/a32/traces/simulator-rd-rn-rm-t32-crc32b.h | 2 +- test/a32/traces/simulator-rd-rn-rm-t32-crc32cb.h | 2 +- test/a32/traces/simulator-rd-rn-rm-t32-crc32ch.h | 2 +- test/a32/traces/simulator-rd-rn-rm-t32-crc32cw.h | 2 +- test/a32/traces/simulator-rd-rn-rm-t32-crc32h.h | 2 +- test/a32/traces/simulator-rd-rn-rm-t32-crc32w.h | 2 +- test/a64/examples/test-examples.cc | 2 +- test/a64/test-assembler-a64.cc | 2 +- test/a64/test-disasm-a64.cc | 2 +- test/a64/test-fuzz-a64.cc | 2 +- test/a64/test-simulator-a64.cc | 2 +- test/a64/test-simulator-inputs-a64.h | 2 +- test/a64/test-simulator-traces-a64.h | 2 +- test/a64/test-trace-a64.cc | 2 +- test/a64/test-utils-a64.cc | 2 +- test/a64/test-utils-a64.h | 2 +- test/a64/traces/sim-abs-16b-trace-a64.h | 2 +- test/a64/traces/sim-abs-2d-trace-a64.h | 2 +- test/a64/traces/sim-abs-2s-trace-a64.h | 2 +- test/a64/traces/sim-abs-4h-trace-a64.h | 2 +- test/a64/traces/sim-abs-4s-trace-a64.h | 2 +- test/a64/traces/sim-abs-8b-trace-a64.h | 2 +- test/a64/traces/sim-abs-8h-trace-a64.h | 2 +- test/a64/traces/sim-abs-d-trace-a64.h | 2 +- test/a64/traces/sim-add-16b-trace-a64.h | 2 +- test/a64/traces/sim-add-2d-trace-a64.h | 2 +- test/a64/traces/sim-add-2s-trace-a64.h | 2 +- test/a64/traces/sim-add-4h-trace-a64.h | 2 +- test/a64/traces/sim-add-4s-trace-a64.h | 2 +- test/a64/traces/sim-add-8b-trace-a64.h | 2 +- test/a64/traces/sim-add-8h-trace-a64.h | 2 +- test/a64/traces/sim-add-d-trace-a64.h | 2 +- test/a64/traces/sim-addhn-2s-trace-a64.h | 2 +- test/a64/traces/sim-addhn-4h-trace-a64.h | 2 +- test/a64/traces/sim-addhn-8b-trace-a64.h | 2 +- test/a64/traces/sim-addhn2-16b-trace-a64.h | 2 +- test/a64/traces/sim-addhn2-4s-trace-a64.h | 2 +- test/a64/traces/sim-addhn2-8h-trace-a64.h | 2 +- test/a64/traces/sim-addp-16b-trace-a64.h | 2 +- test/a64/traces/sim-addp-2d-trace-a64.h | 2 +- test/a64/traces/sim-addp-2s-trace-a64.h | 2 +- test/a64/traces/sim-addp-4h-trace-a64.h | 2 +- test/a64/traces/sim-addp-4s-trace-a64.h | 2 +- test/a64/traces/sim-addp-8b-trace-a64.h | 2 +- test/a64/traces/sim-addp-8h-trace-a64.h | 2 +- test/a64/traces/sim-addp-scalar-trace-a64.h | 2 +- test/a64/traces/sim-addv-b-16b-trace-a64.h | 2 +- test/a64/traces/sim-addv-b-8b-trace-a64.h | 2 +- test/a64/traces/sim-addv-h-4h-trace-a64.h | 2 +- test/a64/traces/sim-addv-h-8h-trace-a64.h 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test/a64/traces/sim-cmgt-2s-trace-a64.h | 2 +- test/a64/traces/sim-cmgt-4h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-cmgt-4h-trace-a64.h | 2 +- test/a64/traces/sim-cmgt-4s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-cmgt-4s-trace-a64.h | 2 +- test/a64/traces/sim-cmgt-8b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-cmgt-8b-trace-a64.h | 2 +- test/a64/traces/sim-cmgt-8h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-cmgt-8h-trace-a64.h | 2 +- test/a64/traces/sim-cmgt-d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-cmgt-d-trace-a64.h | 2 +- test/a64/traces/sim-cmhi-16b-trace-a64.h | 2 +- test/a64/traces/sim-cmhi-2d-trace-a64.h | 2 +- test/a64/traces/sim-cmhi-2s-trace-a64.h | 2 +- test/a64/traces/sim-cmhi-4h-trace-a64.h | 2 +- test/a64/traces/sim-cmhi-4s-trace-a64.h | 2 +- test/a64/traces/sim-cmhi-8b-trace-a64.h | 2 +- test/a64/traces/sim-cmhi-8h-trace-a64.h | 2 +- test/a64/traces/sim-cmhi-d-trace-a64.h | 2 +- test/a64/traces/sim-cmhs-16b-trace-a64.h | 2 +- test/a64/traces/sim-cmhs-2d-trace-a64.h | 2 +- test/a64/traces/sim-cmhs-2s-trace-a64.h | 2 +- test/a64/traces/sim-cmhs-4h-trace-a64.h | 2 +- test/a64/traces/sim-cmhs-4s-trace-a64.h | 2 +- test/a64/traces/sim-cmhs-8b-trace-a64.h | 2 +- test/a64/traces/sim-cmhs-8h-trace-a64.h | 2 +- test/a64/traces/sim-cmhs-d-trace-a64.h | 2 +- test/a64/traces/sim-cmle-16b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-cmle-2d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-cmle-2s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-cmle-4h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-cmle-4s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-cmle-8b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-cmle-8h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-cmle-d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-cmlt-16b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-cmlt-2d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-cmlt-2s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-cmlt-4h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-cmlt-4s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-cmlt-8b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-cmlt-8h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-cmlt-d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-cmtst-16b-trace-a64.h | 2 +- test/a64/traces/sim-cmtst-2d-trace-a64.h | 2 +- test/a64/traces/sim-cmtst-2s-trace-a64.h | 2 +- test/a64/traces/sim-cmtst-4h-trace-a64.h | 2 +- test/a64/traces/sim-cmtst-4s-trace-a64.h | 2 +- test/a64/traces/sim-cmtst-8b-trace-a64.h | 2 +- test/a64/traces/sim-cmtst-8h-trace-a64.h | 2 +- test/a64/traces/sim-cmtst-d-trace-a64.h | 2 +- test/a64/traces/sim-cnt-16b-trace-a64.h | 2 +- test/a64/traces/sim-cnt-8b-trace-a64.h | 2 +- test/a64/traces/sim-dup-16b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-dup-2d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-dup-2s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-dup-4h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-dup-4s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-dup-8b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-dup-8h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-dup-b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-dup-d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-dup-h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-dup-s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-eor-16b-trace-a64.h | 2 +- test/a64/traces/sim-eor-8b-trace-a64.h | 2 +- test/a64/traces/sim-fabd-2d-trace-a64.h | 2 +- test/a64/traces/sim-fabd-2s-trace-a64.h | 2 +- test/a64/traces/sim-fabd-4s-trace-a64.h | 2 +- test/a64/traces/sim-fabd-d-trace-a64.h | 2 +- test/a64/traces/sim-fabd-s-trace-a64.h | 2 +- test/a64/traces/sim-fabs-2d-trace-a64.h | 2 +- test/a64/traces/sim-fabs-2s-trace-a64.h | 2 +- test/a64/traces/sim-fabs-4s-trace-a64.h | 2 +- test/a64/traces/sim-fabs-d-trace-a64.h | 2 +- test/a64/traces/sim-fabs-s-trace-a64.h | 2 +- test/a64/traces/sim-facge-2d-trace-a64.h | 2 +- test/a64/traces/sim-facge-2s-trace-a64.h | 2 +- test/a64/traces/sim-facge-4s-trace-a64.h | 2 +- test/a64/traces/sim-facge-d-trace-a64.h | 2 +- test/a64/traces/sim-facge-s-trace-a64.h | 2 +- test/a64/traces/sim-facgt-2d-trace-a64.h | 2 +- test/a64/traces/sim-facgt-2s-trace-a64.h | 2 +- test/a64/traces/sim-facgt-4s-trace-a64.h | 2 +- test/a64/traces/sim-facgt-d-trace-a64.h | 2 +- test/a64/traces/sim-facgt-s-trace-a64.h | 2 +- test/a64/traces/sim-fadd-2d-trace-a64.h | 2 +- test/a64/traces/sim-fadd-2s-trace-a64.h | 2 +- test/a64/traces/sim-fadd-4s-trace-a64.h | 2 +- test/a64/traces/sim-fadd-d-trace-a64.h | 2 +- test/a64/traces/sim-fadd-s-trace-a64.h | 2 +- test/a64/traces/sim-faddp-2d-trace-a64.h | 2 +- test/a64/traces/sim-faddp-2s-trace-a64.h | 2 +- test/a64/traces/sim-faddp-4s-trace-a64.h | 2 +- test/a64/traces/sim-faddp-d-trace-a64.h | 2 +- test/a64/traces/sim-faddp-s-trace-a64.h | 2 +- test/a64/traces/sim-fcmeq-2d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcmeq-2d-trace-a64.h | 2 +- test/a64/traces/sim-fcmeq-2s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcmeq-2s-trace-a64.h | 2 +- test/a64/traces/sim-fcmeq-4s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcmeq-4s-trace-a64.h | 2 +- test/a64/traces/sim-fcmeq-d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcmeq-d-trace-a64.h | 2 +- test/a64/traces/sim-fcmeq-s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcmeq-s-trace-a64.h | 2 +- test/a64/traces/sim-fcmge-2d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcmge-2d-trace-a64.h | 2 +- test/a64/traces/sim-fcmge-2s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcmge-2s-trace-a64.h | 2 +- test/a64/traces/sim-fcmge-4s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcmge-4s-trace-a64.h | 2 +- test/a64/traces/sim-fcmge-d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcmge-d-trace-a64.h | 2 +- test/a64/traces/sim-fcmge-s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcmge-s-trace-a64.h | 2 +- test/a64/traces/sim-fcmgt-2d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcmgt-2d-trace-a64.h | 2 +- test/a64/traces/sim-fcmgt-2s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcmgt-2s-trace-a64.h | 2 +- test/a64/traces/sim-fcmgt-4s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcmgt-4s-trace-a64.h | 2 +- test/a64/traces/sim-fcmgt-d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcmgt-d-trace-a64.h | 2 +- test/a64/traces/sim-fcmgt-s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcmgt-s-trace-a64.h | 2 +- test/a64/traces/sim-fcmle-2d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcmle-2s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcmle-4s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcmle-d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcmle-s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcmlt-2d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcmlt-2s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcmlt-4s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcmlt-d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcmlt-s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcmp-d-trace-a64.h | 2 +- test/a64/traces/sim-fcmp-dz-trace-a64.h | 2 +- test/a64/traces/sim-fcmp-s-trace-a64.h | 2 +- test/a64/traces/sim-fcmp-sz-trace-a64.h | 2 +- test/a64/traces/sim-fcvt-ds-trace-a64.h | 2 +- test/a64/traces/sim-fcvt-sd-trace-a64.h | 2 +- test/a64/traces/sim-fcvtas-2d-trace-a64.h | 2 +- test/a64/traces/sim-fcvtas-2s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtas-4s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtas-d-trace-a64.h | 2 +- test/a64/traces/sim-fcvtas-s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtas-wd-trace-a64.h | 2 +- test/a64/traces/sim-fcvtas-ws-trace-a64.h | 2 +- test/a64/traces/sim-fcvtas-xd-trace-a64.h | 2 +- test/a64/traces/sim-fcvtas-xs-trace-a64.h | 2 +- test/a64/traces/sim-fcvtau-2d-trace-a64.h | 2 +- test/a64/traces/sim-fcvtau-2s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtau-4s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtau-d-trace-a64.h | 2 +- test/a64/traces/sim-fcvtau-s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtau-wd-trace-a64.h | 2 +- test/a64/traces/sim-fcvtau-ws-trace-a64.h | 2 +- test/a64/traces/sim-fcvtau-xd-trace-a64.h | 2 +- test/a64/traces/sim-fcvtau-xs-trace-a64.h | 2 +- test/a64/traces/sim-fcvtl-2d-trace-a64.h | 2 +- test/a64/traces/sim-fcvtl-4s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtl2-2d-trace-a64.h | 2 +- test/a64/traces/sim-fcvtl2-4s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtms-2d-trace-a64.h | 2 +- test/a64/traces/sim-fcvtms-2s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtms-4s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtms-d-trace-a64.h | 2 +- test/a64/traces/sim-fcvtms-s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtms-wd-trace-a64.h | 2 +- test/a64/traces/sim-fcvtms-ws-trace-a64.h | 2 +- test/a64/traces/sim-fcvtms-xd-trace-a64.h | 2 +- test/a64/traces/sim-fcvtms-xs-trace-a64.h | 2 +- test/a64/traces/sim-fcvtmu-2d-trace-a64.h | 2 +- test/a64/traces/sim-fcvtmu-2s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtmu-4s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtmu-d-trace-a64.h | 2 +- test/a64/traces/sim-fcvtmu-s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtmu-wd-trace-a64.h | 2 +- test/a64/traces/sim-fcvtmu-ws-trace-a64.h | 2 +- test/a64/traces/sim-fcvtmu-xd-trace-a64.h | 2 +- test/a64/traces/sim-fcvtmu-xs-trace-a64.h | 2 +- test/a64/traces/sim-fcvtn-2s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtn-4h-trace-a64.h | 2 +- test/a64/traces/sim-fcvtn2-4s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtn2-8h-trace-a64.h | 2 +- test/a64/traces/sim-fcvtns-2d-trace-a64.h | 2 +- test/a64/traces/sim-fcvtns-2s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtns-4s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtns-d-trace-a64.h | 2 +- test/a64/traces/sim-fcvtns-s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtns-wd-trace-a64.h | 2 +- test/a64/traces/sim-fcvtns-ws-trace-a64.h | 2 +- test/a64/traces/sim-fcvtns-xd-trace-a64.h | 2 +- test/a64/traces/sim-fcvtns-xs-trace-a64.h | 2 +- test/a64/traces/sim-fcvtnu-2d-trace-a64.h | 2 +- test/a64/traces/sim-fcvtnu-2s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtnu-4s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtnu-d-trace-a64.h | 2 +- test/a64/traces/sim-fcvtnu-s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtnu-wd-trace-a64.h | 2 +- test/a64/traces/sim-fcvtnu-ws-trace-a64.h | 2 +- test/a64/traces/sim-fcvtnu-xd-trace-a64.h | 2 +- test/a64/traces/sim-fcvtnu-xs-trace-a64.h | 2 +- test/a64/traces/sim-fcvtps-2d-trace-a64.h | 2 +- test/a64/traces/sim-fcvtps-2s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtps-4s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtps-d-trace-a64.h | 2 +- test/a64/traces/sim-fcvtps-s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtpu-2d-trace-a64.h | 2 +- test/a64/traces/sim-fcvtpu-2s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtpu-4s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtpu-d-trace-a64.h | 2 +- test/a64/traces/sim-fcvtpu-s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtxn-2s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtxn-scalar-trace-a64.h | 2 +- test/a64/traces/sim-fcvtxn2-4s-trace-a64.h | 2 +- test/a64/traces/sim-fcvtzs-2d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcvtzs-2s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcvtzs-4s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcvtzs-d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcvtzs-s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcvtzs-wd-trace-a64.h | 2 +- test/a64/traces/sim-fcvtzs-ws-trace-a64.h | 2 +- test/a64/traces/sim-fcvtzs-xd-trace-a64.h | 2 +- test/a64/traces/sim-fcvtzs-xs-trace-a64.h | 2 +- test/a64/traces/sim-fcvtzu-2d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcvtzu-2s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcvtzu-4s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcvtzu-d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcvtzu-s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-fcvtzu-wd-trace-a64.h | 2 +- test/a64/traces/sim-fcvtzu-ws-trace-a64.h | 2 +- test/a64/traces/sim-fcvtzu-xd-trace-a64.h | 2 +- test/a64/traces/sim-fcvtzu-xs-trace-a64.h | 2 +- test/a64/traces/sim-fdiv-2d-trace-a64.h | 2 +- test/a64/traces/sim-fdiv-2s-trace-a64.h | 2 +- test/a64/traces/sim-fdiv-4s-trace-a64.h | 2 +- test/a64/traces/sim-fdiv-d-trace-a64.h | 2 +- test/a64/traces/sim-fdiv-s-trace-a64.h | 2 +- test/a64/traces/sim-fmadd-d-trace-a64.h | 2 +- test/a64/traces/sim-fmadd-s-trace-a64.h | 2 +- test/a64/traces/sim-fmax-2d-trace-a64.h | 2 +- test/a64/traces/sim-fmax-2s-trace-a64.h | 2 +- test/a64/traces/sim-fmax-4s-trace-a64.h | 2 +- test/a64/traces/sim-fmax-d-trace-a64.h | 2 +- test/a64/traces/sim-fmax-s-trace-a64.h | 2 +- test/a64/traces/sim-fmaxnm-2d-trace-a64.h | 2 +- test/a64/traces/sim-fmaxnm-2s-trace-a64.h | 2 +- test/a64/traces/sim-fmaxnm-4s-trace-a64.h | 2 +- test/a64/traces/sim-fmaxnm-d-trace-a64.h | 2 +- test/a64/traces/sim-fmaxnm-s-trace-a64.h | 2 +- test/a64/traces/sim-fmaxnmp-2d-trace-a64.h | 2 +- test/a64/traces/sim-fmaxnmp-2s-trace-a64.h | 2 +- test/a64/traces/sim-fmaxnmp-4s-trace-a64.h | 2 +- test/a64/traces/sim-fmaxnmp-d-trace-a64.h | 2 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test/a64/traces/sim-fminnmp-4s-trace-a64.h | 2 +- test/a64/traces/sim-fminnmp-d-trace-a64.h | 2 +- test/a64/traces/sim-fminnmp-s-trace-a64.h | 2 +- test/a64/traces/sim-fminnmv-s-4s-trace-a64.h | 2 +- test/a64/traces/sim-fminp-2d-trace-a64.h | 2 +- test/a64/traces/sim-fminp-2s-trace-a64.h | 2 +- test/a64/traces/sim-fminp-4s-trace-a64.h | 2 +- test/a64/traces/sim-fminp-d-trace-a64.h | 2 +- test/a64/traces/sim-fminp-s-trace-a64.h | 2 +- test/a64/traces/sim-fminv-s-4s-trace-a64.h | 2 +- test/a64/traces/sim-fmla-2d-2d-d-trace-a64.h | 2 +- test/a64/traces/sim-fmla-2d-trace-a64.h | 2 +- test/a64/traces/sim-fmla-2s-2s-s-trace-a64.h | 2 +- test/a64/traces/sim-fmla-2s-trace-a64.h | 2 +- test/a64/traces/sim-fmla-4s-4s-s-trace-a64.h | 2 +- test/a64/traces/sim-fmla-4s-trace-a64.h | 2 +- test/a64/traces/sim-fmla-d-d-d-trace-a64.h | 2 +- test/a64/traces/sim-fmla-s-s-s-trace-a64.h | 2 +- test/a64/traces/sim-fmls-2d-2d-d-trace-a64.h | 2 +- test/a64/traces/sim-fmls-2d-trace-a64.h | 2 +- test/a64/traces/sim-fmls-2s-2s-s-trace-a64.h | 2 +- test/a64/traces/sim-fmls-2s-trace-a64.h | 2 +- test/a64/traces/sim-fmls-4s-4s-s-trace-a64.h | 2 +- test/a64/traces/sim-fmls-4s-trace-a64.h | 2 +- test/a64/traces/sim-fmls-d-d-d-trace-a64.h | 2 +- test/a64/traces/sim-fmls-s-s-s-trace-a64.h | 2 +- test/a64/traces/sim-fmov-d-trace-a64.h | 2 +- test/a64/traces/sim-fmov-s-trace-a64.h | 2 +- test/a64/traces/sim-fmsub-d-trace-a64.h | 2 +- test/a64/traces/sim-fmsub-s-trace-a64.h | 2 +- test/a64/traces/sim-fmul-2d-2d-d-trace-a64.h | 2 +- test/a64/traces/sim-fmul-2d-trace-a64.h | 2 +- test/a64/traces/sim-fmul-2s-2s-s-trace-a64.h | 2 +- test/a64/traces/sim-fmul-2s-trace-a64.h | 2 +- test/a64/traces/sim-fmul-4s-4s-s-trace-a64.h | 2 +- test/a64/traces/sim-fmul-4s-trace-a64.h | 2 +- test/a64/traces/sim-fmul-d-d-d-trace-a64.h | 2 +- test/a64/traces/sim-fmul-d-trace-a64.h | 2 +- test/a64/traces/sim-fmul-s-s-s-trace-a64.h | 2 +- test/a64/traces/sim-fmul-s-trace-a64.h | 2 +- test/a64/traces/sim-fmulx-2d-2d-d-trace-a64.h | 2 +- test/a64/traces/sim-fmulx-2d-trace-a64.h | 2 +- test/a64/traces/sim-fmulx-2s-2s-s-trace-a64.h | 2 +- test/a64/traces/sim-fmulx-2s-trace-a64.h | 2 +- test/a64/traces/sim-fmulx-4s-4s-s-trace-a64.h | 2 +- test/a64/traces/sim-fmulx-4s-trace-a64.h | 2 +- test/a64/traces/sim-fmulx-d-d-d-trace-a64.h | 2 +- test/a64/traces/sim-fmulx-d-trace-a64.h | 2 +- test/a64/traces/sim-fmulx-s-s-s-trace-a64.h | 2 +- test/a64/traces/sim-fmulx-s-trace-a64.h | 2 +- test/a64/traces/sim-fneg-2d-trace-a64.h | 2 +- test/a64/traces/sim-fneg-2s-trace-a64.h | 2 +- test/a64/traces/sim-fneg-4s-trace-a64.h | 2 +- test/a64/traces/sim-fneg-d-trace-a64.h | 2 +- test/a64/traces/sim-fneg-s-trace-a64.h | 2 +- test/a64/traces/sim-fnmadd-d-trace-a64.h | 2 +- test/a64/traces/sim-fnmadd-s-trace-a64.h | 2 +- test/a64/traces/sim-fnmsub-d-trace-a64.h | 2 +- test/a64/traces/sim-fnmsub-s-trace-a64.h | 2 +- test/a64/traces/sim-fnmul-d-trace-a64.h | 2 +- test/a64/traces/sim-fnmul-s-trace-a64.h | 2 +- test/a64/traces/sim-frecpe-2d-trace-a64.h | 2 +- test/a64/traces/sim-frecpe-2s-trace-a64.h | 2 +- test/a64/traces/sim-frecpe-4s-trace-a64.h | 2 +- test/a64/traces/sim-frecpe-d-trace-a64.h | 2 +- test/a64/traces/sim-frecpe-s-trace-a64.h | 2 +- test/a64/traces/sim-frecps-2d-trace-a64.h | 2 +- test/a64/traces/sim-frecps-2s-trace-a64.h | 2 +- test/a64/traces/sim-frecps-4s-trace-a64.h | 2 +- test/a64/traces/sim-frecps-d-trace-a64.h | 2 +- test/a64/traces/sim-frecps-s-trace-a64.h | 2 +- test/a64/traces/sim-frecpx-d-trace-a64.h | 2 +- test/a64/traces/sim-frecpx-s-trace-a64.h | 2 +- test/a64/traces/sim-frinta-2d-trace-a64.h | 2 +- test/a64/traces/sim-frinta-2s-trace-a64.h | 2 +- test/a64/traces/sim-frinta-4s-trace-a64.h | 2 +- test/a64/traces/sim-frinta-d-trace-a64.h | 2 +- test/a64/traces/sim-frinta-s-trace-a64.h | 2 +- test/a64/traces/sim-frinti-2d-trace-a64.h | 2 +- test/a64/traces/sim-frinti-2s-trace-a64.h | 2 +- test/a64/traces/sim-frinti-4s-trace-a64.h | 2 +- test/a64/traces/sim-frinti-d-trace-a64.h | 2 +- test/a64/traces/sim-frinti-s-trace-a64.h | 2 +- test/a64/traces/sim-frintm-2d-trace-a64.h | 2 +- test/a64/traces/sim-frintm-2s-trace-a64.h | 2 +- test/a64/traces/sim-frintm-4s-trace-a64.h | 2 +- test/a64/traces/sim-frintm-d-trace-a64.h | 2 +- test/a64/traces/sim-frintm-s-trace-a64.h | 2 +- test/a64/traces/sim-frintn-2d-trace-a64.h | 2 +- test/a64/traces/sim-frintn-2s-trace-a64.h | 2 +- test/a64/traces/sim-frintn-4s-trace-a64.h | 2 +- test/a64/traces/sim-frintn-d-trace-a64.h | 2 +- test/a64/traces/sim-frintn-s-trace-a64.h | 2 +- test/a64/traces/sim-frintp-2d-trace-a64.h | 2 +- test/a64/traces/sim-frintp-2s-trace-a64.h | 2 +- test/a64/traces/sim-frintp-4s-trace-a64.h | 2 +- test/a64/traces/sim-frintp-d-trace-a64.h | 2 +- test/a64/traces/sim-frintp-s-trace-a64.h | 2 +- test/a64/traces/sim-frintx-2d-trace-a64.h | 2 +- test/a64/traces/sim-frintx-2s-trace-a64.h | 2 +- test/a64/traces/sim-frintx-4s-trace-a64.h | 2 +- test/a64/traces/sim-frintx-d-trace-a64.h | 2 +- test/a64/traces/sim-frintx-s-trace-a64.h | 2 +- test/a64/traces/sim-frintz-2d-trace-a64.h | 2 +- test/a64/traces/sim-frintz-2s-trace-a64.h | 2 +- test/a64/traces/sim-frintz-4s-trace-a64.h | 2 +- test/a64/traces/sim-frintz-d-trace-a64.h | 2 +- test/a64/traces/sim-frintz-s-trace-a64.h | 2 +- test/a64/traces/sim-frsqrte-2d-trace-a64.h | 2 +- test/a64/traces/sim-frsqrte-2s-trace-a64.h | 2 +- test/a64/traces/sim-frsqrte-4s-trace-a64.h | 2 +- test/a64/traces/sim-frsqrte-d-trace-a64.h | 2 +- test/a64/traces/sim-frsqrte-s-trace-a64.h | 2 +- test/a64/traces/sim-frsqrts-2d-trace-a64.h | 2 +- test/a64/traces/sim-frsqrts-2s-trace-a64.h | 2 +- test/a64/traces/sim-frsqrts-4s-trace-a64.h | 2 +- test/a64/traces/sim-frsqrts-d-trace-a64.h | 2 +- test/a64/traces/sim-frsqrts-s-trace-a64.h | 2 +- test/a64/traces/sim-fsqrt-2d-trace-a64.h | 2 +- test/a64/traces/sim-fsqrt-2s-trace-a64.h | 2 +- test/a64/traces/sim-fsqrt-4s-trace-a64.h | 2 +- test/a64/traces/sim-fsqrt-d-trace-a64.h | 2 +- test/a64/traces/sim-fsqrt-s-trace-a64.h | 2 +- test/a64/traces/sim-fsub-2d-trace-a64.h | 2 +- test/a64/traces/sim-fsub-2s-trace-a64.h | 2 +- test/a64/traces/sim-fsub-4s-trace-a64.h | 2 +- test/a64/traces/sim-fsub-d-trace-a64.h | 2 +- test/a64/traces/sim-fsub-s-trace-a64.h | 2 +- test/a64/traces/sim-ins-b-trace-a64.h | 2 +- test/a64/traces/sim-ins-d-trace-a64.h | 2 +- test/a64/traces/sim-ins-h-trace-a64.h | 2 +- test/a64/traces/sim-ins-s-trace-a64.h | 2 +- test/a64/traces/sim-mla-16b-trace-a64.h | 2 +- test/a64/traces/sim-mla-2s-2s-s-trace-a64.h | 2 +- test/a64/traces/sim-mla-2s-trace-a64.h | 2 +- test/a64/traces/sim-mla-4h-4h-h-trace-a64.h | 2 +- test/a64/traces/sim-mla-4h-trace-a64.h | 2 +- test/a64/traces/sim-mla-4s-4s-s-trace-a64.h | 2 +- test/a64/traces/sim-mla-4s-trace-a64.h | 2 +- test/a64/traces/sim-mla-8b-trace-a64.h | 2 +- test/a64/traces/sim-mla-8h-8h-h-trace-a64.h | 2 +- test/a64/traces/sim-mla-8h-trace-a64.h | 2 +- test/a64/traces/sim-mls-16b-trace-a64.h | 2 +- test/a64/traces/sim-mls-2s-2s-s-trace-a64.h | 2 +- test/a64/traces/sim-mls-2s-trace-a64.h | 2 +- test/a64/traces/sim-mls-4h-4h-h-trace-a64.h | 2 +- test/a64/traces/sim-mls-4h-trace-a64.h | 2 +- test/a64/traces/sim-mls-4s-4s-s-trace-a64.h | 2 +- test/a64/traces/sim-mls-4s-trace-a64.h | 2 +- test/a64/traces/sim-mls-8b-trace-a64.h | 2 +- test/a64/traces/sim-mls-8h-8h-h-trace-a64.h | 2 +- test/a64/traces/sim-mls-8h-trace-a64.h | 2 +- test/a64/traces/sim-mul-16b-trace-a64.h | 2 +- test/a64/traces/sim-mul-2s-2s-s-trace-a64.h | 2 +- test/a64/traces/sim-mul-2s-trace-a64.h | 2 +- test/a64/traces/sim-mul-4h-4h-h-trace-a64.h | 2 +- test/a64/traces/sim-mul-4h-trace-a64.h | 2 +- test/a64/traces/sim-mul-4s-4s-s-trace-a64.h | 2 +- test/a64/traces/sim-mul-4s-trace-a64.h | 2 +- test/a64/traces/sim-mul-8b-trace-a64.h | 2 +- test/a64/traces/sim-mul-8h-8h-h-trace-a64.h | 2 +- test/a64/traces/sim-mul-8h-trace-a64.h | 2 +- test/a64/traces/sim-neg-16b-trace-a64.h | 2 +- test/a64/traces/sim-neg-2d-trace-a64.h | 2 +- test/a64/traces/sim-neg-2s-trace-a64.h | 2 +- test/a64/traces/sim-neg-4h-trace-a64.h | 2 +- test/a64/traces/sim-neg-4s-trace-a64.h | 2 +- test/a64/traces/sim-neg-8b-trace-a64.h | 2 +- test/a64/traces/sim-neg-8h-trace-a64.h | 2 +- test/a64/traces/sim-neg-d-trace-a64.h | 2 +- test/a64/traces/sim-not--16b-trace-a64.h | 2 +- test/a64/traces/sim-not--8b-trace-a64.h | 2 +- test/a64/traces/sim-orn-16b-trace-a64.h | 2 +- test/a64/traces/sim-orn-8b-trace-a64.h | 2 +- test/a64/traces/sim-orr-16b-trace-a64.h | 2 +- test/a64/traces/sim-orr-8b-trace-a64.h | 2 +- test/a64/traces/sim-pmul-16b-trace-a64.h | 2 +- test/a64/traces/sim-pmul-8b-trace-a64.h | 2 +- test/a64/traces/sim-pmull-8h-trace-a64.h | 2 +- test/a64/traces/sim-pmull2-8h-trace-a64.h | 2 +- test/a64/traces/sim-raddhn-2s-trace-a64.h | 2 +- test/a64/traces/sim-raddhn-4h-trace-a64.h | 2 +- test/a64/traces/sim-raddhn-8b-trace-a64.h | 2 +- test/a64/traces/sim-raddhn2-16b-trace-a64.h | 2 +- test/a64/traces/sim-raddhn2-4s-trace-a64.h | 2 +- test/a64/traces/sim-raddhn2-8h-trace-a64.h | 2 +- test/a64/traces/sim-rbit-16b-trace-a64.h | 2 +- test/a64/traces/sim-rbit-8b-trace-a64.h | 2 +- test/a64/traces/sim-rev16-16b-trace-a64.h | 2 +- test/a64/traces/sim-rev16-8b-trace-a64.h | 2 +- test/a64/traces/sim-rev32-16b-trace-a64.h | 2 +- test/a64/traces/sim-rev32-4h-trace-a64.h | 2 +- test/a64/traces/sim-rev32-8b-trace-a64.h | 2 +- test/a64/traces/sim-rev32-8h-trace-a64.h | 2 +- test/a64/traces/sim-rev64-16b-trace-a64.h | 2 +- test/a64/traces/sim-rev64-2s-trace-a64.h | 2 +- test/a64/traces/sim-rev64-4h-trace-a64.h | 2 +- test/a64/traces/sim-rev64-4s-trace-a64.h | 2 +- test/a64/traces/sim-rev64-8b-trace-a64.h | 2 +- test/a64/traces/sim-rev64-8h-trace-a64.h | 2 +- test/a64/traces/sim-rshrn-2s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-rshrn-4h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-rshrn-8b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-rshrn2-16b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-rshrn2-4s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-rshrn2-8h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-rsubhn-2s-trace-a64.h | 2 +- test/a64/traces/sim-rsubhn-4h-trace-a64.h | 2 +- test/a64/traces/sim-rsubhn-8b-trace-a64.h | 2 +- test/a64/traces/sim-rsubhn2-16b-trace-a64.h | 2 +- test/a64/traces/sim-rsubhn2-4s-trace-a64.h | 2 +- test/a64/traces/sim-rsubhn2-8h-trace-a64.h | 2 +- test/a64/traces/sim-saba-16b-trace-a64.h | 2 +- test/a64/traces/sim-saba-2s-trace-a64.h | 2 +- test/a64/traces/sim-saba-4h-trace-a64.h | 2 +- test/a64/traces/sim-saba-4s-trace-a64.h | 2 +- test/a64/traces/sim-saba-8b-trace-a64.h | 2 +- test/a64/traces/sim-saba-8h-trace-a64.h | 2 +- test/a64/traces/sim-sabal-2d-trace-a64.h | 2 +- test/a64/traces/sim-sabal-4s-trace-a64.h | 2 +- test/a64/traces/sim-sabal-8h-trace-a64.h | 2 +- test/a64/traces/sim-sabal2-2d-trace-a64.h | 2 +- test/a64/traces/sim-sabal2-4s-trace-a64.h | 2 +- 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test/a64/traces/sim-sqrshrn-2s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqrshrn-4h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqrshrn-8b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqrshrn-b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqrshrn-h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqrshrn-s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqrshrn2-16b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqrshrn2-4s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqrshrn2-8h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqrshrun-2s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqrshrun-4h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqrshrun-8b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqrshrun-b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqrshrun-h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqrshrun-s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqrshrun2-16b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqrshrun2-4s-2opimm-trace-a64.h | 2 +- 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test/a64/traces/sim-sqshl-h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqshl-h-trace-a64.h | 2 +- test/a64/traces/sim-sqshl-s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqshl-s-trace-a64.h | 2 +- test/a64/traces/sim-sqshlu-16b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqshlu-2d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqshlu-2s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqshlu-4h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqshlu-4s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqshlu-8b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqshlu-8h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqshlu-b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqshlu-d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqshlu-h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqshlu-s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqshrn-2s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqshrn-4h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sqshrn-8b-2opimm-trace-a64.h | 2 +- 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test/a64/traces/sim-sqsub-4h-trace-a64.h | 2 +- test/a64/traces/sim-sqsub-4s-trace-a64.h | 2 +- test/a64/traces/sim-sqsub-8b-trace-a64.h | 2 +- test/a64/traces/sim-sqsub-8h-trace-a64.h | 2 +- test/a64/traces/sim-sqsub-b-trace-a64.h | 2 +- test/a64/traces/sim-sqsub-d-trace-a64.h | 2 +- test/a64/traces/sim-sqsub-h-trace-a64.h | 2 +- test/a64/traces/sim-sqsub-s-trace-a64.h | 2 +- test/a64/traces/sim-sqxtn-2s-trace-a64.h | 2 +- test/a64/traces/sim-sqxtn-4h-trace-a64.h | 2 +- test/a64/traces/sim-sqxtn-8b-trace-a64.h | 2 +- test/a64/traces/sim-sqxtn-b-trace-a64.h | 2 +- test/a64/traces/sim-sqxtn-h-trace-a64.h | 2 +- test/a64/traces/sim-sqxtn-s-trace-a64.h | 2 +- test/a64/traces/sim-sqxtn2-16b-trace-a64.h | 2 +- test/a64/traces/sim-sqxtn2-4s-trace-a64.h | 2 +- test/a64/traces/sim-sqxtn2-8h-trace-a64.h | 2 +- test/a64/traces/sim-sqxtun-2s-trace-a64.h | 2 +- test/a64/traces/sim-sqxtun-4h-trace-a64.h | 2 +- test/a64/traces/sim-sqxtun-8b-trace-a64.h | 2 +- test/a64/traces/sim-sqxtun-b-trace-a64.h | 2 +- test/a64/traces/sim-sqxtun-h-trace-a64.h | 2 +- test/a64/traces/sim-sqxtun-s-trace-a64.h | 2 +- test/a64/traces/sim-sqxtun2-16b-trace-a64.h | 2 +- test/a64/traces/sim-sqxtun2-4s-trace-a64.h | 2 +- test/a64/traces/sim-sqxtun2-8h-trace-a64.h | 2 +- test/a64/traces/sim-srhadd-16b-trace-a64.h | 2 +- test/a64/traces/sim-srhadd-2s-trace-a64.h | 2 +- test/a64/traces/sim-srhadd-4h-trace-a64.h | 2 +- test/a64/traces/sim-srhadd-4s-trace-a64.h | 2 +- test/a64/traces/sim-srhadd-8b-trace-a64.h | 2 +- test/a64/traces/sim-srhadd-8h-trace-a64.h | 2 +- test/a64/traces/sim-sri-16b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sri-2d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sri-2s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sri-4h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sri-4s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sri-8b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sri-8h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sri-d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-srshl-16b-trace-a64.h | 2 +- test/a64/traces/sim-srshl-2d-trace-a64.h | 2 +- test/a64/traces/sim-srshl-2s-trace-a64.h | 2 +- test/a64/traces/sim-srshl-4h-trace-a64.h | 2 +- test/a64/traces/sim-srshl-4s-trace-a64.h | 2 +- test/a64/traces/sim-srshl-8b-trace-a64.h | 2 +- test/a64/traces/sim-srshl-8h-trace-a64.h | 2 +- test/a64/traces/sim-srshl-d-trace-a64.h | 2 +- test/a64/traces/sim-srshr-16b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-srshr-2d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-srshr-2s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-srshr-4h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-srshr-4s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-srshr-8b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-srshr-8h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-srshr-d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-srsra-16b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-srsra-2d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-srsra-2s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-srsra-4h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-srsra-4s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-srsra-8b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-srsra-8h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-srsra-d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sshl-16b-trace-a64.h | 2 +- test/a64/traces/sim-sshl-2d-trace-a64.h | 2 +- test/a64/traces/sim-sshl-2s-trace-a64.h | 2 +- test/a64/traces/sim-sshl-4h-trace-a64.h | 2 +- test/a64/traces/sim-sshl-4s-trace-a64.h | 2 +- test/a64/traces/sim-sshl-8b-trace-a64.h | 2 +- test/a64/traces/sim-sshl-8h-trace-a64.h | 2 +- test/a64/traces/sim-sshl-d-trace-a64.h | 2 +- test/a64/traces/sim-sshll-2d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sshll-4s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sshll-8h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sshll2-2d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sshll2-4s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sshll2-8h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sshr-16b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sshr-2d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sshr-2s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sshr-4h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sshr-4s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sshr-8b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sshr-8h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-sshr-d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-ssra-16b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-ssra-2d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-ssra-2s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-ssra-4h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-ssra-4s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-ssra-8b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-ssra-8h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-ssra-d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-ssubl-2d-trace-a64.h | 2 +- test/a64/traces/sim-ssubl-4s-trace-a64.h | 2 +- test/a64/traces/sim-ssubl-8h-trace-a64.h | 2 +- test/a64/traces/sim-ssubl2-2d-trace-a64.h | 2 +- test/a64/traces/sim-ssubl2-4s-trace-a64.h | 2 +- test/a64/traces/sim-ssubl2-8h-trace-a64.h | 2 +- test/a64/traces/sim-ssubw-2d-trace-a64.h | 2 +- test/a64/traces/sim-ssubw-4s-trace-a64.h | 2 +- test/a64/traces/sim-ssubw-8h-trace-a64.h | 2 +- test/a64/traces/sim-ssubw2-2d-trace-a64.h | 2 +- test/a64/traces/sim-ssubw2-4s-trace-a64.h | 2 +- test/a64/traces/sim-ssubw2-8h-trace-a64.h | 2 +- test/a64/traces/sim-sub-16b-trace-a64.h | 2 +- test/a64/traces/sim-sub-2d-trace-a64.h | 2 +- test/a64/traces/sim-sub-2s-trace-a64.h | 2 +- test/a64/traces/sim-sub-4h-trace-a64.h | 2 +- test/a64/traces/sim-sub-4s-trace-a64.h | 2 +- test/a64/traces/sim-sub-8b-trace-a64.h | 2 +- test/a64/traces/sim-sub-8h-trace-a64.h | 2 +- test/a64/traces/sim-sub-d-trace-a64.h | 2 +- test/a64/traces/sim-subhn-2s-trace-a64.h | 2 +- test/a64/traces/sim-subhn-4h-trace-a64.h | 2 +- test/a64/traces/sim-subhn-8b-trace-a64.h | 2 +- test/a64/traces/sim-subhn2-16b-trace-a64.h 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test/a64/traces/sim-urecpe-2s-trace-a64.h | 2 +- test/a64/traces/sim-urecpe-4s-trace-a64.h | 2 +- test/a64/traces/sim-urhadd-16b-trace-a64.h | 2 +- test/a64/traces/sim-urhadd-2s-trace-a64.h | 2 +- test/a64/traces/sim-urhadd-4h-trace-a64.h | 2 +- test/a64/traces/sim-urhadd-4s-trace-a64.h | 2 +- test/a64/traces/sim-urhadd-8b-trace-a64.h | 2 +- test/a64/traces/sim-urhadd-8h-trace-a64.h | 2 +- test/a64/traces/sim-urshl-16b-trace-a64.h | 2 +- test/a64/traces/sim-urshl-2d-trace-a64.h | 2 +- test/a64/traces/sim-urshl-2s-trace-a64.h | 2 +- test/a64/traces/sim-urshl-4h-trace-a64.h | 2 +- test/a64/traces/sim-urshl-4s-trace-a64.h | 2 +- test/a64/traces/sim-urshl-8b-trace-a64.h | 2 +- test/a64/traces/sim-urshl-8h-trace-a64.h | 2 +- test/a64/traces/sim-urshl-d-trace-a64.h | 2 +- test/a64/traces/sim-urshr-16b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-urshr-2d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-urshr-2s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-urshr-4h-2opimm-trace-a64.h | 2 +- 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test/a64/traces/sim-ushl-8b-trace-a64.h | 2 +- test/a64/traces/sim-ushl-8h-trace-a64.h | 2 +- test/a64/traces/sim-ushl-d-trace-a64.h | 2 +- test/a64/traces/sim-ushll-2d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-ushll-4s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-ushll-8h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-ushll2-2d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-ushll2-4s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-ushll2-8h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-ushr-16b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-ushr-2d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-ushr-2s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-ushr-4h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-ushr-4s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-ushr-8b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-ushr-8h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-ushr-d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-usqadd-16b-trace-a64.h | 2 +- test/a64/traces/sim-usqadd-2d-trace-a64.h | 2 +- test/a64/traces/sim-usqadd-2s-trace-a64.h | 2 +- test/a64/traces/sim-usqadd-4h-trace-a64.h | 2 +- test/a64/traces/sim-usqadd-4s-trace-a64.h | 2 +- test/a64/traces/sim-usqadd-8b-trace-a64.h | 2 +- test/a64/traces/sim-usqadd-8h-trace-a64.h | 2 +- test/a64/traces/sim-usqadd-b-trace-a64.h | 2 +- test/a64/traces/sim-usqadd-d-trace-a64.h | 2 +- test/a64/traces/sim-usqadd-h-trace-a64.h | 2 +- test/a64/traces/sim-usqadd-s-trace-a64.h | 2 +- test/a64/traces/sim-usra-16b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-usra-2d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-usra-2s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-usra-4h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-usra-4s-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-usra-8b-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-usra-8h-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-usra-d-2opimm-trace-a64.h | 2 +- test/a64/traces/sim-usubl-2d-trace-a64.h | 2 +- test/a64/traces/sim-usubl-4s-trace-a64.h | 2 +- test/a64/traces/sim-usubl-8h-trace-a64.h | 2 +- test/a64/traces/sim-usubl2-2d-trace-a64.h | 2 +- test/a64/traces/sim-usubl2-4s-trace-a64.h | 2 +- test/a64/traces/sim-usubl2-8h-trace-a64.h | 2 +- test/a64/traces/sim-usubw-2d-trace-a64.h | 2 +- test/a64/traces/sim-usubw-4s-trace-a64.h | 2 +- test/a64/traces/sim-usubw-8h-trace-a64.h | 2 +- test/a64/traces/sim-usubw2-2d-trace-a64.h | 2 +- test/a64/traces/sim-usubw2-4s-trace-a64.h | 2 +- test/a64/traces/sim-usubw2-8h-trace-a64.h | 2 +- test/a64/traces/sim-uzp1-16b-trace-a64.h | 2 +- test/a64/traces/sim-uzp1-2d-trace-a64.h | 2 +- test/a64/traces/sim-uzp1-2s-trace-a64.h | 2 +- test/a64/traces/sim-uzp1-4h-trace-a64.h | 2 +- test/a64/traces/sim-uzp1-4s-trace-a64.h | 2 +- test/a64/traces/sim-uzp1-8b-trace-a64.h | 2 +- test/a64/traces/sim-uzp1-8h-trace-a64.h | 2 +- test/a64/traces/sim-uzp2-16b-trace-a64.h | 2 +- test/a64/traces/sim-uzp2-2d-trace-a64.h | 2 +- test/a64/traces/sim-uzp2-2s-trace-a64.h | 2 +- test/a64/traces/sim-uzp2-4h-trace-a64.h | 2 +- test/a64/traces/sim-uzp2-4s-trace-a64.h | 2 +- test/a64/traces/sim-uzp2-8b-trace-a64.h | 2 +- test/a64/traces/sim-uzp2-8h-trace-a64.h | 2 +- test/a64/traces/sim-xtn-2s-trace-a64.h | 2 +- test/a64/traces/sim-xtn-4h-trace-a64.h | 2 +- test/a64/traces/sim-xtn-8b-trace-a64.h | 2 +- test/a64/traces/sim-xtn2-16b-trace-a64.h | 2 +- test/a64/traces/sim-xtn2-4s-trace-a64.h | 2 +- test/a64/traces/sim-xtn2-8h-trace-a64.h | 2 +- test/a64/traces/sim-zip1-16b-trace-a64.h | 2 +- test/a64/traces/sim-zip1-2d-trace-a64.h | 2 +- test/a64/traces/sim-zip1-2s-trace-a64.h | 2 +- test/a64/traces/sim-zip1-4h-trace-a64.h | 2 +- test/a64/traces/sim-zip1-4s-trace-a64.h | 2 +- test/a64/traces/sim-zip1-8b-trace-a64.h | 2 +- test/a64/traces/sim-zip1-8h-trace-a64.h | 2 +- test/a64/traces/sim-zip2-16b-trace-a64.h | 2 +- test/a64/traces/sim-zip2-2d-trace-a64.h | 2 +- test/a64/traces/sim-zip2-2s-trace-a64.h | 2 +- test/a64/traces/sim-zip2-4h-trace-a64.h | 2 +- test/a64/traces/sim-zip2-4s-trace-a64.h | 2 +- test/a64/traces/sim-zip2-8b-trace-a64.h | 2 +- test/a64/traces/sim-zip2-8h-trace-a64.h | 2 +- test/test-invalset.cc | 2 +- test/test-runner.cc | 2 +- test/test-runner.h | 2 +- test/test-utils.cc | 2 +- test/test-utils.h | 2 +- third_party/android/Android.mk.template | 2 +- third_party/android/generate_android_mk.py | 2 +- tools/clang_format.py | 2 +- tools/config.py | 2 +- tools/cross_build_gcc.sh | 2 +- tools/generate_simulator_traces.py | 4 ++-- tools/generate_test_trace_a64_reference.py | 2 +- tools/generate_tests.py | 2 +- tools/git.py | 2 +- tools/lint.py | 2 +- tools/make_instruction_doc.pl | 2 +- tools/printer.py | 2 +- tools/test.py | 2 +- tools/test_generator/data_types.py | 2 +- tools/test_generator/generator.py | 2 +- tools/test_generator/parser.py | 2 +- tools/threaded_tests.py | 2 +- tools/util.py | 2 +- tools/verify_assembler_traces.py | 2 +- 2737 files changed, 2746 insertions(+), 2738 deletions(-) create mode 100644 AUTHORS diff --git a/.clang-format b/.clang-format index 0a7e60c7..31e0b6ea 100644 --- a/.clang-format +++ b/.clang-format @@ -1,4 +1,4 @@ -# Copyright 2016, ARM Limited +# Copyright 2016, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/AUTHORS b/AUTHORS new file mode 100644 index 00000000..257ec9d3 --- /dev/null +++ b/AUTHORS @@ -0,0 +1,8 @@ +# Below is a list of people and organisations that have contributed to the VIXL +# project. Entries should be added to the list as: +# +# Name/Organization + +ARM Ltd. <*@arm.com> +Google Inc. <*@google.com> +Linaro <*@linaro.org> diff --git a/LICENCE b/LICENCE index 6f85a379..0acd8ebd 100644 --- a/LICENCE +++ b/LICENCE @@ -3,7 +3,7 @@ LICENCE The software in this repository is covered by the following licence. -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/SConstruct b/SConstruct index ccde2e56..074970fc 100644 --- a/SConstruct +++ b/SConstruct @@ -1,4 +1,4 @@ -# Copyright 2015, ARM Limited +# Copyright 2015, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/benchmarks/a64/bench-branch-link-masm.cc b/benchmarks/a64/bench-branch-link-masm.cc index 11608f9e..9495b5c0 100644 --- a/benchmarks/a64/bench-branch-link-masm.cc +++ b/benchmarks/a64/bench-branch-link-masm.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/benchmarks/a64/bench-branch-link.cc b/benchmarks/a64/bench-branch-link.cc index 4dc04954..76684f63 100644 --- a/benchmarks/a64/bench-branch-link.cc +++ b/benchmarks/a64/bench-branch-link.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/benchmarks/a64/bench-branch-masm.cc b/benchmarks/a64/bench-branch-masm.cc index 7fd1d105..22a54055 100644 --- a/benchmarks/a64/bench-branch-masm.cc +++ b/benchmarks/a64/bench-branch-masm.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/benchmarks/a64/bench-branch.cc b/benchmarks/a64/bench-branch.cc index 8976e7b2..43121db0 100644 --- a/benchmarks/a64/bench-branch.cc +++ b/benchmarks/a64/bench-branch.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/benchmarks/a64/bench-dataop.cc b/benchmarks/a64/bench-dataop.cc index b5c6faa3..a0d5dfe7 100644 --- a/benchmarks/a64/bench-dataop.cc +++ b/benchmarks/a64/bench-dataop.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a32/abs.cc b/examples/a32/abs.cc index f819ef38..50bf995e 100644 --- a/examples/a32/abs.cc +++ b/examples/a32/abs.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a32/disasm-a32.cc b/examples/a32/disasm-a32.cc index 28280c11..8a664ac4 100644 --- a/examples/a32/disasm-a32.cc +++ b/examples/a32/disasm-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a32/examples.h b/examples/a32/examples.h index 0e75cd59..e2af0194 100644 --- a/examples/a32/examples.h +++ b/examples/a32/examples.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a32/getting-started.cc b/examples/a32/getting-started.cc index 3b167d34..e7c78232 100644 --- a/examples/a32/getting-started.cc +++ b/examples/a32/getting-started.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a32/pi.cc b/examples/a32/pi.cc index ebea6260..b8f4bc92 100644 --- a/examples/a32/pi.cc +++ b/examples/a32/pi.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a32/switch.cc b/examples/a32/switch.cc index a7a00eae..689a9b27 100644 --- a/examples/a32/switch.cc +++ b/examples/a32/switch.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/abs.cc b/examples/a64/abs.cc index f9f746c9..5014d36c 100644 --- a/examples/a64/abs.cc +++ b/examples/a64/abs.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/add2-vectors.cc b/examples/a64/add2-vectors.cc index 3ec2b995..919606a8 100644 --- a/examples/a64/add2-vectors.cc +++ b/examples/a64/add2-vectors.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/add3-double.cc b/examples/a64/add3-double.cc index ded48f51..8590d481 100644 --- a/examples/a64/add3-double.cc +++ b/examples/a64/add3-double.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/add4-double.cc b/examples/a64/add4-double.cc index 897ee098..3a861d66 100644 --- a/examples/a64/add4-double.cc +++ b/examples/a64/add4-double.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/check-bounds.cc b/examples/a64/check-bounds.cc index 51149c03..9d2bcbad 100644 --- a/examples/a64/check-bounds.cc +++ b/examples/a64/check-bounds.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/crc-checksums.cc b/examples/a64/crc-checksums.cc index 1e664549..1e22245a 100644 --- a/examples/a64/crc-checksums.cc +++ b/examples/a64/crc-checksums.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/custom-disassembler.cc b/examples/a64/custom-disassembler.cc index a75e6d7a..1bf184bb 100644 --- a/examples/a64/custom-disassembler.cc +++ b/examples/a64/custom-disassembler.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/custom-disassembler.h b/examples/a64/custom-disassembler.h index adac833d..af310c12 100644 --- a/examples/a64/custom-disassembler.h +++ b/examples/a64/custom-disassembler.h @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/debugger.cc b/examples/a64/debugger.cc index 0b2bf7a0..1bff8a4b 100644 --- a/examples/a64/debugger.cc +++ b/examples/a64/debugger.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/examples.h b/examples/a64/examples.h index 4a18a760..4a49d1c4 100644 --- a/examples/a64/examples.h +++ b/examples/a64/examples.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/factorial-rec.cc b/examples/a64/factorial-rec.cc index 2a3c7c81..0dcec209 100644 --- a/examples/a64/factorial-rec.cc +++ b/examples/a64/factorial-rec.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/factorial.cc b/examples/a64/factorial.cc index ca87ddda..e7430060 100644 --- a/examples/a64/factorial.cc +++ b/examples/a64/factorial.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/getting-started.cc b/examples/a64/getting-started.cc index 4572ea63..465b276f 100644 --- a/examples/a64/getting-started.cc +++ b/examples/a64/getting-started.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/literal.cc b/examples/a64/literal.cc index 2c8782af..2b338763 100644 --- a/examples/a64/literal.cc +++ b/examples/a64/literal.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/neon-matrix-multiply.cc b/examples/a64/neon-matrix-multiply.cc index 9e0db396..0e25cfea 100644 --- a/examples/a64/neon-matrix-multiply.cc +++ b/examples/a64/neon-matrix-multiply.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/non-const-visitor.cc b/examples/a64/non-const-visitor.cc index e4422650..843b4625 100644 --- a/examples/a64/non-const-visitor.cc +++ b/examples/a64/non-const-visitor.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/non-const-visitor.h b/examples/a64/non-const-visitor.h index 1df30c9b..138a990e 100644 --- a/examples/a64/non-const-visitor.h +++ b/examples/a64/non-const-visitor.h @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/sum-array.cc b/examples/a64/sum-array.cc index 99e3f98e..2f64c3fe 100644 --- a/examples/a64/sum-array.cc +++ b/examples/a64/sum-array.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/swap-int32.cc b/examples/a64/swap-int32.cc index e2371864..861422db 100644 --- a/examples/a64/swap-int32.cc +++ b/examples/a64/swap-int32.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/examples/a64/swap4.cc b/examples/a64/swap4.cc index 7a933a6a..91e9d4cf 100644 --- a/examples/a64/swap4.cc +++ b/examples/a64/swap4.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a32/assembler-a32.cc b/src/a32/assembler-a32.cc index 6da161cb..a0b8722d 100644 --- a/src/a32/assembler-a32.cc +++ b/src/a32/assembler-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a32/assembler-a32.h b/src/a32/assembler-a32.h index 84a3d9f3..cd40ad40 100644 --- a/src/a32/assembler-a32.h +++ b/src/a32/assembler-a32.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a32/constants-a32.h b/src/a32/constants-a32.h index 75cb5474..4f5ef74b 100644 --- a/src/a32/constants-a32.h +++ b/src/a32/constants-a32.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a32/disasm-a32.cc b/src/a32/disasm-a32.cc index 4a0cedf8..1673f6c1 100644 --- a/src/a32/disasm-a32.cc +++ b/src/a32/disasm-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a32/disasm-a32.h b/src/a32/disasm-a32.h index c9e5749a..91f62c5a 100644 --- a/src/a32/disasm-a32.h +++ b/src/a32/disasm-a32.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a32/instructions-a32.cc b/src/a32/instructions-a32.cc index a35ffc3e..9fff4b04 100644 --- a/src/a32/instructions-a32.cc +++ b/src/a32/instructions-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a32/instructions-a32.h b/src/a32/instructions-a32.h index c95f92db..ff2a9066 100644 --- a/src/a32/instructions-a32.h +++ b/src/a32/instructions-a32.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a32/label-a32.h b/src/a32/label-a32.h index 8d0fb91b..57197dfb 100644 --- a/src/a32/label-a32.h +++ b/src/a32/label-a32.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a32/macro-assembler-a32.cc b/src/a32/macro-assembler-a32.cc index eb1d1964..cec06c7a 100644 --- a/src/a32/macro-assembler-a32.cc +++ b/src/a32/macro-assembler-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a32/macro-assembler-a32.h b/src/a32/macro-assembler-a32.h index 0860860c..f1c76045 100644 --- a/src/a32/macro-assembler-a32.h +++ b/src/a32/macro-assembler-a32.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a32/operand-a32.cc b/src/a32/operand-a32.cc index 7968992e..5d7b93fc 100644 --- a/src/a32/operand-a32.cc +++ b/src/a32/operand-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a32/operand-a32.h b/src/a32/operand-a32.h index a0521dbe..45b53340 100644 --- a/src/a32/operand-a32.h +++ b/src/a32/operand-a32.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/assembler-a64.cc b/src/a64/assembler-a64.cc index 9ec4cd2c..702b1183 100644 --- a/src/a64/assembler-a64.cc +++ b/src/a64/assembler-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/assembler-a64.h b/src/a64/assembler-a64.h index 3d94053a..f77fe0d0 100644 --- a/src/a64/assembler-a64.h +++ b/src/a64/assembler-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/constants-a64.h b/src/a64/constants-a64.h index 2ad581d1..911732a9 100644 --- a/src/a64/constants-a64.h +++ b/src/a64/constants-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/cpu-a64.cc b/src/a64/cpu-a64.cc index 895a1042..891c5124 100644 --- a/src/a64/cpu-a64.cc +++ b/src/a64/cpu-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/cpu-a64.h b/src/a64/cpu-a64.h index 986ac2f2..c253ddcd 100644 --- a/src/a64/cpu-a64.h +++ b/src/a64/cpu-a64.h @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/debugger-a64.cc b/src/a64/debugger-a64.cc index 48f63e04..cf3170ab 100644 --- a/src/a64/debugger-a64.cc +++ b/src/a64/debugger-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/debugger-a64.h b/src/a64/debugger-a64.h index 9f3f2e76..cb58266b 100644 --- a/src/a64/debugger-a64.h +++ b/src/a64/debugger-a64.h @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/decoder-a64.cc b/src/a64/decoder-a64.cc index 6d79b348..cd2c9a70 100644 --- a/src/a64/decoder-a64.cc +++ b/src/a64/decoder-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/decoder-a64.h b/src/a64/decoder-a64.h index 35f47ecb..de2f3e07 100644 --- a/src/a64/decoder-a64.h +++ b/src/a64/decoder-a64.h @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/disasm-a64.cc b/src/a64/disasm-a64.cc index 3ebbbea0..d0fcf1c4 100644 --- a/src/a64/disasm-a64.cc +++ b/src/a64/disasm-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/disasm-a64.h b/src/a64/disasm-a64.h index a8f8a099..f2ebb11e 100644 --- a/src/a64/disasm-a64.h +++ b/src/a64/disasm-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/instructions-a64.cc b/src/a64/instructions-a64.cc index 2ed79a76..202fb282 100644 --- a/src/a64/instructions-a64.cc +++ b/src/a64/instructions-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/instructions-a64.h b/src/a64/instructions-a64.h index fd4a24c4..b6523eb5 100644 --- a/src/a64/instructions-a64.h +++ b/src/a64/instructions-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/instrument-a64.cc b/src/a64/instrument-a64.cc index 4a77ee95..edddf43e 100644 --- a/src/a64/instrument-a64.cc +++ b/src/a64/instrument-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/instrument-a64.h b/src/a64/instrument-a64.h index 7d888e0c..f90ff23a 100644 --- a/src/a64/instrument-a64.h +++ b/src/a64/instrument-a64.h @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/logic-a64.cc b/src/a64/logic-a64.cc index 674f3cad..4a912350 100644 --- a/src/a64/logic-a64.cc +++ b/src/a64/logic-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/macro-assembler-a64.cc b/src/a64/macro-assembler-a64.cc index ea365e80..401d93ec 100644 --- a/src/a64/macro-assembler-a64.cc +++ b/src/a64/macro-assembler-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/macro-assembler-a64.h b/src/a64/macro-assembler-a64.h index fcf5ec61..48371835 100644 --- a/src/a64/macro-assembler-a64.h +++ b/src/a64/macro-assembler-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/simulator-a64.cc b/src/a64/simulator-a64.cc index 7044ebb3..05c4d9b8 100644 --- a/src/a64/simulator-a64.cc +++ b/src/a64/simulator-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/simulator-a64.h b/src/a64/simulator-a64.h index a9a1a1fc..64a33c6e 100644 --- a/src/a64/simulator-a64.h +++ b/src/a64/simulator-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/a64/simulator-constants-a64.h b/src/a64/simulator-constants-a64.h index 8400ae05..416cb317 100644 --- a/src/a64/simulator-constants-a64.h +++ b/src/a64/simulator-constants-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/code-buffer-vixl.cc b/src/code-buffer-vixl.cc index 522f9399..d2f14f54 100644 --- a/src/code-buffer-vixl.cc +++ b/src/code-buffer-vixl.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/code-buffer-vixl.h b/src/code-buffer-vixl.h index b9fc1ce4..4230dff3 100644 --- a/src/code-buffer-vixl.h +++ b/src/code-buffer-vixl.h @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/compiler-intrinsics-vixl.cc b/src/compiler-intrinsics-vixl.cc index 04735b57..ae182c7d 100644 --- a/src/compiler-intrinsics-vixl.cc +++ b/src/compiler-intrinsics-vixl.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/compiler-intrinsics-vixl.h b/src/compiler-intrinsics-vixl.h index 960937f0..b27f94eb 100644 --- a/src/compiler-intrinsics-vixl.h +++ b/src/compiler-intrinsics-vixl.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/globals-vixl.h b/src/globals-vixl.h index 60668f47..e3e4a865 100644 --- a/src/globals-vixl.h +++ b/src/globals-vixl.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/invalset-vixl.h b/src/invalset-vixl.h index 6ca72edc..8d74fdd6 100644 --- a/src/invalset-vixl.h +++ b/src/invalset-vixl.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/platform-vixl.h b/src/platform-vixl.h index ab588f07..f47ebb60 100644 --- a/src/platform-vixl.h +++ b/src/platform-vixl.h @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/utils-vixl.cc b/src/utils-vixl.cc index ad9f213b..0f754d85 100644 --- a/src/utils-vixl.cc +++ b/src/utils-vixl.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/utils-vixl.h b/src/utils-vixl.h index d19cbac6..06c7551e 100644 --- a/src/utils-vixl.h +++ b/src/utils-vixl.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-memop-immediate-512-a32.json b/test/a32/config/cond-rd-memop-immediate-512-a32.json index 8ca5b8b6..780b1d9b 100644 --- a/test/a32/config/cond-rd-memop-immediate-512-a32.json +++ b/test/a32/config/cond-rd-memop-immediate-512-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-memop-immediate-8192-a32.json b/test/a32/config/cond-rd-memop-immediate-8192-a32.json index 857c15dd..7f8ce86a 100644 --- a/test/a32/config/cond-rd-memop-immediate-8192-a32.json +++ b/test/a32/config/cond-rd-memop-immediate-8192-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-memop-rs-a32.json b/test/a32/config/cond-rd-memop-rs-a32.json index 74b89d84..4c7cb24a 100644 --- a/test/a32/config/cond-rd-memop-rs-a32.json +++ b/test/a32/config/cond-rd-memop-rs-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-memop-rs-shift-amount-1to31-a32.json b/test/a32/config/cond-rd-memop-rs-shift-amount-1to31-a32.json index 7a38b8cc..3ce98dee 100644 --- a/test/a32/config/cond-rd-memop-rs-shift-amount-1to31-a32.json +++ b/test/a32/config/cond-rd-memop-rs-shift-amount-1to31-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-memop-rs-shift-amount-1to32-a32.json b/test/a32/config/cond-rd-memop-rs-shift-amount-1to32-a32.json index da76f6d0..4aaf7e34 100644 --- a/test/a32/config/cond-rd-memop-rs-shift-amount-1to32-a32.json +++ b/test/a32/config/cond-rd-memop-rs-shift-amount-1to32-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-operand-const-a32.json b/test/a32/config/cond-rd-operand-const-a32.json index c9d25bd9..9ec2d3ac 100644 --- a/test/a32/config/cond-rd-operand-const-a32.json +++ b/test/a32/config/cond-rd-operand-const-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-operand-const-t32.json b/test/a32/config/cond-rd-operand-const-t32.json index 0cb4adf5..95d00338 100644 --- a/test/a32/config/cond-rd-operand-const-t32.json +++ b/test/a32/config/cond-rd-operand-const-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-operand-imm16-t32.json b/test/a32/config/cond-rd-operand-imm16-t32.json index bc18660c..21e7ee11 100644 --- a/test/a32/config/cond-rd-operand-imm16-t32.json +++ b/test/a32/config/cond-rd-operand-imm16-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-operand-rn-a32.json b/test/a32/config/cond-rd-operand-rn-a32.json index 6d39bbd6..e7c3b13d 100644 --- a/test/a32/config/cond-rd-operand-rn-a32.json +++ b/test/a32/config/cond-rd-operand-rn-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-operand-rn-ror-amount-a32.json b/test/a32/config/cond-rd-operand-rn-ror-amount-a32.json index 4ab52c61..3d56a519 100644 --- a/test/a32/config/cond-rd-operand-rn-ror-amount-a32.json +++ b/test/a32/config/cond-rd-operand-rn-ror-amount-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-operand-rn-ror-amount-t32.json b/test/a32/config/cond-rd-operand-rn-ror-amount-t32.json index c2c5ff6a..e60be68e 100644 --- a/test/a32/config/cond-rd-operand-rn-ror-amount-t32.json +++ b/test/a32/config/cond-rd-operand-rn-ror-amount-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-operand-rn-shift-amount-1to31-a32.json b/test/a32/config/cond-rd-operand-rn-shift-amount-1to31-a32.json index 3992c68e..a7aa610a 100644 --- a/test/a32/config/cond-rd-operand-rn-shift-amount-1to31-a32.json +++ b/test/a32/config/cond-rd-operand-rn-shift-amount-1to31-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-operand-rn-shift-amount-1to31-t32.json b/test/a32/config/cond-rd-operand-rn-shift-amount-1to31-t32.json index 24b662c6..d2011373 100644 --- a/test/a32/config/cond-rd-operand-rn-shift-amount-1to31-t32.json +++ b/test/a32/config/cond-rd-operand-rn-shift-amount-1to31-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-operand-rn-shift-amount-1to32-a32.json b/test/a32/config/cond-rd-operand-rn-shift-amount-1to32-a32.json index 13580fcf..815db196 100644 --- a/test/a32/config/cond-rd-operand-rn-shift-amount-1to32-a32.json +++ b/test/a32/config/cond-rd-operand-rn-shift-amount-1to32-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-operand-rn-shift-amount-1to32-t32.json b/test/a32/config/cond-rd-operand-rn-shift-amount-1to32-t32.json index 2f19d8bd..2855883a 100644 --- a/test/a32/config/cond-rd-operand-rn-shift-amount-1to32-t32.json +++ b/test/a32/config/cond-rd-operand-rn-shift-amount-1to32-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-operand-rn-shift-rs-a32.json b/test/a32/config/cond-rd-operand-rn-shift-rs-a32.json index 338ac4f3..882d37da 100644 --- a/test/a32/config/cond-rd-operand-rn-shift-rs-a32.json +++ b/test/a32/config/cond-rd-operand-rn-shift-rs-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-operand-rn-shift-rs-t32.json b/test/a32/config/cond-rd-operand-rn-shift-rs-t32.json index fc2958bc..e52520e6 100644 --- a/test/a32/config/cond-rd-operand-rn-shift-rs-t32.json +++ b/test/a32/config/cond-rd-operand-rn-shift-rs-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-operand-rn-t32.json b/test/a32/config/cond-rd-operand-rn-t32.json index 37e358bb..0729be42 100644 --- a/test/a32/config/cond-rd-operand-rn-t32.json +++ b/test/a32/config/cond-rd-operand-rn-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-pc-operand-imm12-t32.json b/test/a32/config/cond-rd-pc-operand-imm12-t32.json index 9800bcbf..09b4f4f3 100644 --- a/test/a32/config/cond-rd-pc-operand-imm12-t32.json +++ b/test/a32/config/cond-rd-pc-operand-imm12-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-pc-operand-imm8-t32.json b/test/a32/config/cond-rd-pc-operand-imm8-t32.json index 05a5d7a0..6ad44980 100644 --- a/test/a32/config/cond-rd-pc-operand-imm8-t32.json +++ b/test/a32/config/cond-rd-pc-operand-imm8-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-a32.json b/test/a32/config/cond-rd-rn-a32.json index 0b70e4be..6ea3d759 100644 --- a/test/a32/config/cond-rd-rn-a32.json +++ b/test/a32/config/cond-rd-rn-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-operand-const-a32.json b/test/a32/config/cond-rd-rn-operand-const-a32.json index 866bcfca..582871a4 100644 --- a/test/a32/config/cond-rd-rn-operand-const-a32.json +++ b/test/a32/config/cond-rd-rn-operand-const-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-operand-const-t32.json b/test/a32/config/cond-rd-rn-operand-const-t32.json index 4d739c77..4d72b5e7 100644 --- a/test/a32/config/cond-rd-rn-operand-const-t32.json +++ b/test/a32/config/cond-rd-rn-operand-const-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-operand-imm12-t32.json b/test/a32/config/cond-rd-rn-operand-imm12-t32.json index 32efca93..c4ac2f5b 100644 --- a/test/a32/config/cond-rd-rn-operand-imm12-t32.json +++ b/test/a32/config/cond-rd-rn-operand-imm12-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-operand-rm-a32.json b/test/a32/config/cond-rd-rn-operand-rm-a32.json index 8a078991..2b741947 100644 --- a/test/a32/config/cond-rd-rn-operand-rm-a32.json +++ b/test/a32/config/cond-rd-rn-operand-rm-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-operand-rm-ror-amount-a32.json b/test/a32/config/cond-rd-rn-operand-rm-ror-amount-a32.json index 8e3b77da..8092c11c 100644 --- a/test/a32/config/cond-rd-rn-operand-rm-ror-amount-a32.json +++ b/test/a32/config/cond-rd-rn-operand-rm-ror-amount-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-operand-rm-ror-amount-t32.json b/test/a32/config/cond-rd-rn-operand-rm-ror-amount-t32.json index e834306a..bb74af07 100644 --- a/test/a32/config/cond-rd-rn-operand-rm-ror-amount-t32.json +++ b/test/a32/config/cond-rd-rn-operand-rm-ror-amount-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to31-a32.json b/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to31-a32.json index 9c451172..5a62acef 100644 --- a/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to31-a32.json +++ b/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to31-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to31-t32.json b/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to31-t32.json index 826c5113..9419e095 100644 --- a/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to31-t32.json +++ b/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to31-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to32-a32.json b/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to32-a32.json index 04e17663..e173d307 100644 --- a/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to32-a32.json +++ b/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to32-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to32-t32.json b/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to32-t32.json index 4bbeb3cd..5749bdd6 100644 --- a/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to32-t32.json +++ b/test/a32/config/cond-rd-rn-operand-rm-shift-amount-1to32-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-operand-rm-shift-rs-a32.json b/test/a32/config/cond-rd-rn-operand-rm-shift-rs-a32.json index 6827ba1f..8a01da4e 100644 --- a/test/a32/config/cond-rd-rn-operand-rm-shift-rs-a32.json +++ b/test/a32/config/cond-rd-rn-operand-rm-shift-rs-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-operand-rm-t32.json b/test/a32/config/cond-rd-rn-operand-rm-t32.json index 2430ea2e..041988ae 100644 --- a/test/a32/config/cond-rd-rn-operand-rm-t32.json +++ b/test/a32/config/cond-rd-rn-operand-rm-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-rm-a32.json b/test/a32/config/cond-rd-rn-rm-a32.json index 186992bc..33b236fb 100644 --- a/test/a32/config/cond-rd-rn-rm-a32.json +++ b/test/a32/config/cond-rd-rn-rm-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-rm-t32.json b/test/a32/config/cond-rd-rn-rm-t32.json index 8f93e16a..e73f8b65 100644 --- a/test/a32/config/cond-rd-rn-rm-t32.json +++ b/test/a32/config/cond-rd-rn-rm-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-rn-t32.json b/test/a32/config/cond-rd-rn-t32.json index ee823787..c0fa0b9b 100644 --- a/test/a32/config/cond-rd-rn-t32.json +++ b/test/a32/config/cond-rd-rn-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rd-sp-operand-imm8-t32.json b/test/a32/config/cond-rd-sp-operand-imm8-t32.json index c82503d4..44a6da43 100644 --- a/test/a32/config/cond-rd-sp-operand-imm8-t32.json +++ b/test/a32/config/cond-rd-sp-operand-imm8-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rdlow-operand-imm8-t32.json b/test/a32/config/cond-rdlow-operand-imm8-t32.json index 875ac39c..240831fe 100644 --- a/test/a32/config/cond-rdlow-operand-imm8-t32.json +++ b/test/a32/config/cond-rdlow-operand-imm8-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rdlow-rnlow-operand-immediate-t32.json b/test/a32/config/cond-rdlow-rnlow-operand-immediate-t32.json index 73e68767..9c53053e 100644 --- a/test/a32/config/cond-rdlow-rnlow-operand-immediate-t32.json +++ b/test/a32/config/cond-rdlow-rnlow-operand-immediate-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-rdlow-rnlow-rmlow-t32.json b/test/a32/config/cond-rdlow-rnlow-rmlow-t32.json index 084a1cc4..0c056c44 100644 --- a/test/a32/config/cond-rdlow-rnlow-rmlow-t32.json +++ b/test/a32/config/cond-rdlow-rnlow-rmlow-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/cond-sp-sp-operand-imm7-t32.json b/test/a32/config/cond-sp-sp-operand-imm7-t32.json index a7ad7315..6d9b0429 100644 --- a/test/a32/config/cond-sp-sp-operand-imm7-t32.json +++ b/test/a32/config/cond-sp-sp-operand-imm7-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/data-types.json b/test/a32/config/data-types.json index e8f8c373..717cae69 100644 --- a/test/a32/config/data-types.json +++ b/test/a32/config/data-types.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/rd-rn-rm-a32.json b/test/a32/config/rd-rn-rm-a32.json index 9044c9d7..8465a008 100644 --- a/test/a32/config/rd-rn-rm-a32.json +++ b/test/a32/config/rd-rn-rm-a32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/rd-rn-rm-t32.json b/test/a32/config/rd-rn-rm-t32.json index 393717b6..832e3a8f 100644 --- a/test/a32/config/rd-rn-rm-t32.json +++ b/test/a32/config/rd-rn-rm-t32.json @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/template-assembler-a32.cc.in b/test/a32/config/template-assembler-a32.cc.in index 51b91d26..7f608fee 100644 --- a/test/a32/config/template-assembler-a32.cc.in +++ b/test/a32/config/template-assembler-a32.cc.in @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/config/template-simulator-a32.cc.in b/test/a32/config/template-simulator-a32.cc.in index 945c799b..48c8f814 100644 --- a/test/a32/config/template-simulator-a32.cc.in +++ b/test/a32/config/template-simulator-a32.cc.in @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-a32.cc b/test/a32/test-assembler-a32.cc index 2eff5ce6..525873a6 100644 --- a/test/a32/test-assembler-a32.cc +++ b/test/a32/test-assembler-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-memop-immediate-512-a32.cc b/test/a32/test-assembler-cond-rd-memop-immediate-512-a32.cc index 219db4e9..26ce6e1c 100644 --- a/test/a32/test-assembler-cond-rd-memop-immediate-512-a32.cc +++ b/test/a32/test-assembler-cond-rd-memop-immediate-512-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-memop-immediate-8192-a32.cc b/test/a32/test-assembler-cond-rd-memop-immediate-8192-a32.cc index 370575ee..360081fa 100644 --- a/test/a32/test-assembler-cond-rd-memop-immediate-8192-a32.cc +++ b/test/a32/test-assembler-cond-rd-memop-immediate-8192-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-memop-rs-a32.cc b/test/a32/test-assembler-cond-rd-memop-rs-a32.cc index 9aac9528..19d44bf8 100644 --- a/test/a32/test-assembler-cond-rd-memop-rs-a32.cc +++ b/test/a32/test-assembler-cond-rd-memop-rs-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc b/test/a32/test-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc index 20257555..1c46cba0 100644 --- a/test/a32/test-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc +++ b/test/a32/test-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc b/test/a32/test-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc index 554f1669..e6b77d14 100644 --- a/test/a32/test-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc +++ b/test/a32/test-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-const-a32.cc b/test/a32/test-assembler-cond-rd-operand-const-a32.cc index 190079dd..f39f57ed 100644 --- a/test/a32/test-assembler-cond-rd-operand-const-a32.cc +++ b/test/a32/test-assembler-cond-rd-operand-const-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-const-t32.cc b/test/a32/test-assembler-cond-rd-operand-const-t32.cc index 4c2707c2..4d703bfd 100644 --- a/test/a32/test-assembler-cond-rd-operand-const-t32.cc +++ b/test/a32/test-assembler-cond-rd-operand-const-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-imm16-t32.cc b/test/a32/test-assembler-cond-rd-operand-imm16-t32.cc index 2af27b3d..8ac6c19d 100644 --- a/test/a32/test-assembler-cond-rd-operand-imm16-t32.cc +++ b/test/a32/test-assembler-cond-rd-operand-imm16-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-a32.cc b/test/a32/test-assembler-cond-rd-operand-rn-a32.cc index e1521785..539a3117 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-a32.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-ror-amount-a32.cc b/test/a32/test-assembler-cond-rd-operand-rn-ror-amount-a32.cc index 1d7ddb17..563a4f64 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-ror-amount-a32.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-ror-amount-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-ror-amount-t32.cc b/test/a32/test-assembler-cond-rd-operand-rn-ror-amount-t32.cc index 8e3a9f11..6da504e3 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-ror-amount-t32.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-ror-amount-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc b/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc index ff852388..bd3d920b 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32-in-it-block.cc b/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32-in-it-block.cc index 0f7a7479..6aa8c070 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32-in-it-block.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32.cc b/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32.cc index 18aefb19..71e55d8c 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc b/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc index b9110ff7..30d39f40 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block.cc b/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block.cc index b7968dcd..ae7b003b 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32.cc b/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32.cc index e13992e6..672ef178 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-a32.cc b/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-a32.cc index 292de9cc..c9f4df77 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-a32.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block.cc b/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block.cc index 7664aa1b..e8a9cf34 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block.cc b/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block.cc index b4d6e853..46072c87 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-t32.cc b/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-t32.cc index 705bf4ee..3a621cd0 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-t32.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-shift-rs-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-t32-identical-low-registers-in-it-block.cc b/test/a32/test-assembler-cond-rd-operand-rn-t32-identical-low-registers-in-it-block.cc index 014263c6..de1a1789 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-t32-identical-low-registers-in-it-block.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-t32-identical-low-registers-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-t32-in-it-block.cc b/test/a32/test-assembler-cond-rd-operand-rn-t32-in-it-block.cc index 0bbefdf9..71aee3ab 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-t32-in-it-block.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-t32-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-t32-low-registers-in-it-block.cc b/test/a32/test-assembler-cond-rd-operand-rn-t32-low-registers-in-it-block.cc index a5927d37..e02ab2e7 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-t32-low-registers-in-it-block.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-t32-low-registers-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-operand-rn-t32.cc b/test/a32/test-assembler-cond-rd-operand-rn-t32.cc index 2e014936..7964d5a8 100644 --- a/test/a32/test-assembler-cond-rd-operand-rn-t32.cc +++ b/test/a32/test-assembler-cond-rd-operand-rn-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-pc-operand-imm12-t32.cc b/test/a32/test-assembler-cond-rd-pc-operand-imm12-t32.cc index 2b3b2e38..cfdb0e4a 100644 --- a/test/a32/test-assembler-cond-rd-pc-operand-imm12-t32.cc +++ b/test/a32/test-assembler-cond-rd-pc-operand-imm12-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-pc-operand-imm8-t32.cc b/test/a32/test-assembler-cond-rd-pc-operand-imm8-t32.cc index 60b0afe2..e0008099 100644 --- a/test/a32/test-assembler-cond-rd-pc-operand-imm8-t32.cc +++ b/test/a32/test-assembler-cond-rd-pc-operand-imm8-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-a32.cc b/test/a32/test-assembler-cond-rd-rn-a32.cc index 477ea7b9..d30ba555 100644 --- a/test/a32/test-assembler-cond-rd-rn-a32.cc +++ b/test/a32/test-assembler-cond-rd-rn-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-const-a32.cc b/test/a32/test-assembler-cond-rd-rn-operand-const-a32.cc index 86cbff83..2572bfad 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-const-a32.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-const-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-const-t32.cc b/test/a32/test-assembler-cond-rd-rn-operand-const-t32.cc index 727fb091..a0a5d0f1 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-const-t32.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-const-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-imm12-t32.cc b/test/a32/test-assembler-cond-rd-rn-operand-imm12-t32.cc index 2dc502da..beea28dc 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-imm12-t32.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-imm12-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-a32.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-a32.cc index 120c30f6..3c63fbf4 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-a32.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc index 6ee09397..c65a3fd4 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc index 5477ea9e..36220ebf 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc index 57244520..89ef7838 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc index 44b5299d..d5b4dde9 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc index 5efd10cb..dfc23a18 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc index 8a399ca3..7977c40c 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc index f02b8b93..8ac47a48 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block.cc index 1487fde7..d711f99d 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block.cc index b80f5525..1cb335cb 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block.cc index 0f710f62..61cc58ed 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-is-sp-in-it-block.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-is-sp-in-it-block.cc index 8eb851d8..4095143f 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-is-sp-in-it-block.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-is-sp-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-rn-is-sp-in-it-block.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-rn-is-sp-in-it-block.cc index f4bccbaf..2b61f100 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-rn-is-sp-in-it-block.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-t32-rn-is-sp-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-operand-rm-t32.cc b/test/a32/test-assembler-cond-rd-rn-operand-rm-t32.cc index c313ed27..75321814 100644 --- a/test/a32/test-assembler-cond-rd-rn-operand-rm-t32.cc +++ b/test/a32/test-assembler-cond-rd-rn-operand-rm-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-rm-a32.cc b/test/a32/test-assembler-cond-rd-rn-rm-a32.cc index 77b637db..3bf6a269 100644 --- a/test/a32/test-assembler-cond-rd-rn-rm-a32.cc +++ b/test/a32/test-assembler-cond-rd-rn-rm-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-rm-t32.cc b/test/a32/test-assembler-cond-rd-rn-rm-t32.cc index d6927a11..02e2a6aa 100644 --- a/test/a32/test-assembler-cond-rd-rn-rm-t32.cc +++ b/test/a32/test-assembler-cond-rd-rn-rm-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-rn-t32.cc b/test/a32/test-assembler-cond-rd-rn-t32.cc index 2143ecc8..367f9863 100644 --- a/test/a32/test-assembler-cond-rd-rn-t32.cc +++ b/test/a32/test-assembler-cond-rd-rn-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rd-sp-operand-imm8-t32.cc b/test/a32/test-assembler-cond-rd-sp-operand-imm8-t32.cc index c1a9a9aa..8d3090e7 100644 --- a/test/a32/test-assembler-cond-rd-sp-operand-imm8-t32.cc +++ b/test/a32/test-assembler-cond-rd-sp-operand-imm8-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rdlow-operand-imm8-t32-in-it-block.cc b/test/a32/test-assembler-cond-rdlow-operand-imm8-t32-in-it-block.cc index 19340a1f..4b5bcaf1 100644 --- a/test/a32/test-assembler-cond-rdlow-operand-imm8-t32-in-it-block.cc +++ b/test/a32/test-assembler-cond-rdlow-operand-imm8-t32-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rdlow-operand-imm8-t32.cc b/test/a32/test-assembler-cond-rdlow-operand-imm8-t32.cc index f745581d..0ecab756 100644 --- a/test/a32/test-assembler-cond-rdlow-operand-imm8-t32.cc +++ b/test/a32/test-assembler-cond-rdlow-operand-imm8-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block.cc b/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block.cc index 57c99821..7b602174 100644 --- a/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block.cc +++ b/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3.cc b/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3.cc index 244d826f..8f336894 100644 --- a/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3.cc +++ b/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block.cc b/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block.cc index b2de652d..a017855b 100644 --- a/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block.cc +++ b/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8.cc b/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8.cc index aaf59397..79ca6f72 100644 --- a/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8.cc +++ b/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block.cc b/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block.cc index 09c4b297..09a2cdfb 100644 --- a/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block.cc +++ b/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero.cc b/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero.cc index 1acb3593..649ba25e 100644 --- a/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero.cc +++ b/test/a32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block.cc b/test/a32/test-assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block.cc index 310e92bf..5e2a4db1 100644 --- a/test/a32/test-assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block.cc +++ b/test/a32/test-assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-rdlow-rnlow-rmlow-t32.cc b/test/a32/test-assembler-cond-rdlow-rnlow-rmlow-t32.cc index 2ff46832..31128720 100644 --- a/test/a32/test-assembler-cond-rdlow-rnlow-rmlow-t32.cc +++ b/test/a32/test-assembler-cond-rdlow-rnlow-rmlow-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-cond-sp-sp-operand-imm7-t32.cc b/test/a32/test-assembler-cond-sp-sp-operand-imm7-t32.cc index efa2b1b5..2d73076f 100644 --- a/test/a32/test-assembler-cond-sp-sp-operand-imm7-t32.cc +++ b/test/a32/test-assembler-cond-sp-sp-operand-imm7-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-rd-rn-rm-a32.cc b/test/a32/test-assembler-rd-rn-rm-a32.cc index 75c39a89..58b69cd4 100644 --- a/test/a32/test-assembler-rd-rn-rm-a32.cc +++ b/test/a32/test-assembler-rd-rn-rm-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-assembler-rd-rn-rm-t32.cc b/test/a32/test-assembler-rd-rn-rm-t32.cc index d4a5b438..6e71708f 100644 --- a/test/a32/test-assembler-rd-rn-rm-t32.cc +++ b/test/a32/test-assembler-rd-rn-rm-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-disasm-a32.cc b/test/a32/test-disasm-a32.cc index 38e3ef80..7679b8fa 100644 --- a/test/a32/test-disasm-a32.cc +++ b/test/a32/test-disasm-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-memop-immediate-512-a32.cc b/test/a32/test-simulator-cond-rd-memop-immediate-512-a32.cc index 3bafd82b..eebc757d 100644 --- a/test/a32/test-simulator-cond-rd-memop-immediate-512-a32.cc +++ b/test/a32/test-simulator-cond-rd-memop-immediate-512-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-memop-immediate-8192-a32.cc b/test/a32/test-simulator-cond-rd-memop-immediate-8192-a32.cc index 1875c3e2..2ab6bc00 100644 --- a/test/a32/test-simulator-cond-rd-memop-immediate-8192-a32.cc +++ b/test/a32/test-simulator-cond-rd-memop-immediate-8192-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-memop-rs-a32.cc b/test/a32/test-simulator-cond-rd-memop-rs-a32.cc index b13911bb..6ddc2e4a 100644 --- a/test/a32/test-simulator-cond-rd-memop-rs-a32.cc +++ b/test/a32/test-simulator-cond-rd-memop-rs-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc b/test/a32/test-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc index 05ca3a3d..2b362ca3 100644 --- a/test/a32/test-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc +++ b/test/a32/test-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc b/test/a32/test-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc index 3ca7a2a4..3550f41d 100644 --- a/test/a32/test-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc +++ b/test/a32/test-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-operand-const-a32.cc b/test/a32/test-simulator-cond-rd-operand-const-a32.cc index e7feedee..dce994a4 100644 --- a/test/a32/test-simulator-cond-rd-operand-const-a32.cc +++ b/test/a32/test-simulator-cond-rd-operand-const-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-operand-const-t32.cc b/test/a32/test-simulator-cond-rd-operand-const-t32.cc index 685e61df..4d1eb5db 100644 --- a/test/a32/test-simulator-cond-rd-operand-const-t32.cc +++ b/test/a32/test-simulator-cond-rd-operand-const-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-operand-imm16-t32.cc b/test/a32/test-simulator-cond-rd-operand-imm16-t32.cc index ee206135..273d67c4 100644 --- a/test/a32/test-simulator-cond-rd-operand-imm16-t32.cc +++ b/test/a32/test-simulator-cond-rd-operand-imm16-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-operand-rn-a32.cc b/test/a32/test-simulator-cond-rd-operand-rn-a32.cc index 44a68f6c..8c68aa5b 100644 --- a/test/a32/test-simulator-cond-rd-operand-rn-a32.cc +++ b/test/a32/test-simulator-cond-rd-operand-rn-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-operand-rn-ror-amount-a32.cc b/test/a32/test-simulator-cond-rd-operand-rn-ror-amount-a32.cc index 5c2c1353..d066af05 100644 --- a/test/a32/test-simulator-cond-rd-operand-rn-ror-amount-a32.cc +++ b/test/a32/test-simulator-cond-rd-operand-rn-ror-amount-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-operand-rn-ror-amount-t32.cc b/test/a32/test-simulator-cond-rd-operand-rn-ror-amount-t32.cc index 652bc19c..7e365040 100644 --- a/test/a32/test-simulator-cond-rd-operand-rn-ror-amount-t32.cc +++ b/test/a32/test-simulator-cond-rd-operand-rn-ror-amount-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc b/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc index 372097e0..a426cfec 100644 --- a/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc +++ b/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc b/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc index 244ca013..98cebe83 100644 --- a/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc +++ b/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc b/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc index 58898e4d..048a4d6e 100644 --- a/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc +++ b/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc b/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc index 64069a64..33a46d26 100644 --- a/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc +++ b/test/a32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-operand-rn-shift-rs-a32.cc b/test/a32/test-simulator-cond-rd-operand-rn-shift-rs-a32.cc index 9eb9ab15..c2c1010b 100644 --- a/test/a32/test-simulator-cond-rd-operand-rn-shift-rs-a32.cc +++ b/test/a32/test-simulator-cond-rd-operand-rn-shift-rs-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-operand-rn-shift-rs-t32.cc b/test/a32/test-simulator-cond-rd-operand-rn-shift-rs-t32.cc index ce47fd79..49a5af61 100644 --- a/test/a32/test-simulator-cond-rd-operand-rn-shift-rs-t32.cc +++ b/test/a32/test-simulator-cond-rd-operand-rn-shift-rs-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-operand-rn-t32.cc b/test/a32/test-simulator-cond-rd-operand-rn-t32.cc index 1dd23768..799e90ef 100644 --- a/test/a32/test-simulator-cond-rd-operand-rn-t32.cc +++ b/test/a32/test-simulator-cond-rd-operand-rn-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-a32.cc b/test/a32/test-simulator-cond-rd-rn-a32.cc index 0ebb165c..b3612a32 100644 --- a/test/a32/test-simulator-cond-rd-rn-a32.cc +++ b/test/a32/test-simulator-cond-rd-rn-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-operand-const-a32.cc b/test/a32/test-simulator-cond-rd-rn-operand-const-a32.cc index e4b9e8eb..b95a0538 100644 --- a/test/a32/test-simulator-cond-rd-rn-operand-const-a32.cc +++ b/test/a32/test-simulator-cond-rd-rn-operand-const-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-operand-const-t32.cc b/test/a32/test-simulator-cond-rd-rn-operand-const-t32.cc index c5be86e9..e21bdc16 100644 --- a/test/a32/test-simulator-cond-rd-rn-operand-const-t32.cc +++ b/test/a32/test-simulator-cond-rd-rn-operand-const-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-operand-imm12-t32.cc b/test/a32/test-simulator-cond-rd-rn-operand-imm12-t32.cc index 1033c374..3c9b7cef 100644 --- a/test/a32/test-simulator-cond-rd-rn-operand-imm12-t32.cc +++ b/test/a32/test-simulator-cond-rd-rn-operand-imm12-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-operand-rm-a32.cc b/test/a32/test-simulator-cond-rd-rn-operand-rm-a32.cc index b0a0d514..2d12bfa2 100644 --- a/test/a32/test-simulator-cond-rd-rn-operand-rm-a32.cc +++ b/test/a32/test-simulator-cond-rd-rn-operand-rm-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc b/test/a32/test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc index eeb53e0d..e8fb0f3d 100644 --- a/test/a32/test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc +++ b/test/a32/test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc b/test/a32/test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc index 61a7501d..8e00e2eb 100644 --- a/test/a32/test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc +++ b/test/a32/test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc b/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc index 273a2c78..ae5c9759 100644 --- a/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc +++ b/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc b/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc index 99577328..889edb42 100644 --- a/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc +++ b/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc b/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc index 2ce9a442..60194fa2 100644 --- a/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc +++ b/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc b/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc index 825e3bcc..3943cfda 100644 --- a/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc +++ b/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc b/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc index 25799313..06db8a08 100644 --- a/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc +++ b/test/a32/test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-operand-rm-t32.cc b/test/a32/test-simulator-cond-rd-rn-operand-rm-t32.cc index 2db1a971..b1c972b2 100644 --- a/test/a32/test-simulator-cond-rd-rn-operand-rm-t32.cc +++ b/test/a32/test-simulator-cond-rd-rn-operand-rm-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-rm-a32-ge.cc b/test/a32/test-simulator-cond-rd-rn-rm-a32-ge.cc index 9def547e..d7ff20df 100644 --- a/test/a32/test-simulator-cond-rd-rn-rm-a32-ge.cc +++ b/test/a32/test-simulator-cond-rd-rn-rm-a32-ge.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-rm-a32-q.cc b/test/a32/test-simulator-cond-rd-rn-rm-a32-q.cc index 6c0d4d81..a08979c3 100644 --- a/test/a32/test-simulator-cond-rd-rn-rm-a32-q.cc +++ b/test/a32/test-simulator-cond-rd-rn-rm-a32-q.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-rm-a32-sel.cc b/test/a32/test-simulator-cond-rd-rn-rm-a32-sel.cc index 7dcc8f59..486fd808 100644 --- a/test/a32/test-simulator-cond-rd-rn-rm-a32-sel.cc +++ b/test/a32/test-simulator-cond-rd-rn-rm-a32-sel.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-rm-a32.cc b/test/a32/test-simulator-cond-rd-rn-rm-a32.cc index c902d0f7..b97d3cc6 100644 --- a/test/a32/test-simulator-cond-rd-rn-rm-a32.cc +++ b/test/a32/test-simulator-cond-rd-rn-rm-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-rm-t32-ge.cc b/test/a32/test-simulator-cond-rd-rn-rm-t32-ge.cc index 6ab46934..7a07133c 100644 --- a/test/a32/test-simulator-cond-rd-rn-rm-t32-ge.cc +++ b/test/a32/test-simulator-cond-rd-rn-rm-t32-ge.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-rm-t32-q.cc b/test/a32/test-simulator-cond-rd-rn-rm-t32-q.cc index 036be0cf..992ca561 100644 --- a/test/a32/test-simulator-cond-rd-rn-rm-t32-q.cc +++ b/test/a32/test-simulator-cond-rd-rn-rm-t32-q.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-rm-t32-sel.cc b/test/a32/test-simulator-cond-rd-rn-rm-t32-sel.cc index 9bec2908..50467c41 100644 --- a/test/a32/test-simulator-cond-rd-rn-rm-t32-sel.cc +++ b/test/a32/test-simulator-cond-rd-rn-rm-t32-sel.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-rm-t32.cc b/test/a32/test-simulator-cond-rd-rn-rm-t32.cc index 89a9e8aa..fab30bc9 100644 --- a/test/a32/test-simulator-cond-rd-rn-rm-t32.cc +++ b/test/a32/test-simulator-cond-rd-rn-rm-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rd-rn-t32.cc b/test/a32/test-simulator-cond-rd-rn-t32.cc index 5c910deb..d441af4b 100644 --- a/test/a32/test-simulator-cond-rd-rn-t32.cc +++ b/test/a32/test-simulator-cond-rd-rn-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rdlow-operand-imm8-t32.cc b/test/a32/test-simulator-cond-rdlow-operand-imm8-t32.cc index d6501840..24f4f4af 100644 --- a/test/a32/test-simulator-cond-rdlow-operand-imm8-t32.cc +++ b/test/a32/test-simulator-cond-rdlow-operand-imm8-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rdlow-rnlow-operand-immediate-t32.cc b/test/a32/test-simulator-cond-rdlow-rnlow-operand-immediate-t32.cc index d1686a31..4d75e27b 100644 --- a/test/a32/test-simulator-cond-rdlow-rnlow-operand-immediate-t32.cc +++ b/test/a32/test-simulator-cond-rdlow-rnlow-operand-immediate-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-cond-rdlow-rnlow-rmlow-t32.cc b/test/a32/test-simulator-cond-rdlow-rnlow-rmlow-t32.cc index deadca49..5cf12440 100644 --- a/test/a32/test-simulator-cond-rdlow-rnlow-rmlow-t32.cc +++ b/test/a32/test-simulator-cond-rdlow-rnlow-rmlow-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-rd-rn-rm-a32.cc b/test/a32/test-simulator-rd-rn-rm-a32.cc index b3b1075e..afc8a58e 100644 --- a/test/a32/test-simulator-rd-rn-rm-a32.cc +++ b/test/a32/test-simulator-rd-rn-rm-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-simulator-rd-rn-rm-t32.cc b/test/a32/test-simulator-rd-rn-rm-t32.cc index 098752f6..a55380bc 100644 --- a/test/a32/test-simulator-rd-rn-rm-t32.cc +++ b/test/a32/test-simulator-rd-rn-rm-t32.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-utils-a32.cc b/test/a32/test-utils-a32.cc index 13ff9241..0837baa5 100644 --- a/test/a32/test-utils-a32.cc +++ b/test/a32/test-utils-a32.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/test-utils-a32.h b/test/a32/test-utils-a32.h index 7d238b75..d4e78876 100644 --- a/test/a32/test-utils-a32.h +++ b/test/a32/test-utils-a32.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-ldrh.h b/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-ldrh.h index 774371d7..0e3c4d94 100644 --- a/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-ldrh.h +++ b/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-ldrh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-ldrsb.h b/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-ldrsb.h index a5d0a530..ea09d7f4 100644 --- a/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-ldrsb.h +++ b/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-ldrsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-ldrsh.h b/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-ldrsh.h index a941c156..6c803f30 100644 --- a/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-ldrsh.h +++ b/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-ldrsh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-strh.h b/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-strh.h index d57a37b6..f2162b05 100644 --- a/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-strh.h +++ b/test/a32/traces/assembler-cond-rd-memop-immediate-512-a32-strh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-ldr.h b/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-ldr.h index 4b1e89da..a0551acc 100644 --- a/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-ldr.h +++ b/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-ldr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-ldrb.h b/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-ldrb.h index 98f8b04d..e892fd84 100644 --- a/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-ldrb.h +++ b/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-ldrb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-str.h b/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-str.h index a5fe23ac..48420a69 100644 --- a/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-str.h +++ b/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-str.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-strb.h b/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-strb.h index bd924413..28907f35 100644 --- a/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-strb.h +++ b/test/a32/traces/assembler-cond-rd-memop-immediate-8192-a32-strb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldr.h b/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldr.h index 0e89be3a..f7acdec6 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldr.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrb.h b/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrb.h index 2bb5d010..deb0d774 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrb.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrh.h b/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrh.h index 50b241dd..af38f446 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrh.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrsb.h b/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrsb.h index a1ac6b3b..fa11b093 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrsb.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrsh.h b/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrsh.h index 83f04941..b65dbdb7 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrsh.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-a32-ldrsh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-a32-str.h b/test/a32/traces/assembler-cond-rd-memop-rs-a32-str.h index ff1793c2..3aa10f6b 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-a32-str.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-a32-str.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-a32-strb.h b/test/a32/traces/assembler-cond-rd-memop-rs-a32-strb.h index c4639852..0af6f63a 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-a32-strb.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-a32-strb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-a32-strh.h b/test/a32/traces/assembler-cond-rd-memop-rs-a32-strh.h index 591a1b18..bb58d50f 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-a32-strh.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-a32-strh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-ldr.h b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-ldr.h index c27875ff..f966626d 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-ldr.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-ldr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-ldrb.h b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-ldrb.h index 832d3118..a7950781 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-ldrb.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-ldrb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-str.h b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-str.h index 4ae30c99..9fd7e505 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-str.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-str.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-strb.h b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-strb.h index 966e66e8..57cc690b 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-strb.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to31-a32-strb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-ldr.h b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-ldr.h index acf146b1..d9b620b5 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-ldr.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-ldr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-ldrb.h b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-ldrb.h index 16387b2a..03ad4638 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-ldrb.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-ldrb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-str.h b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-str.h index e70d9a21..189c4921 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-str.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-str.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-strb.h b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-strb.h index 46337066..e19adca4 100644 --- a/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-strb.h +++ b/test/a32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-a32-strb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-a32-cmn.h b/test/a32/traces/assembler-cond-rd-operand-const-a32-cmn.h index 6b95d71e..391faf7e 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-a32-cmn.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-a32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-a32-cmp.h b/test/a32/traces/assembler-cond-rd-operand-const-a32-cmp.h index 28247d5d..33785a7b 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-a32-cmp.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-a32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-a32-mov.h b/test/a32/traces/assembler-cond-rd-operand-const-a32-mov.h index 4c181722..31c221c0 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-a32-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-a32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-a32-movs.h b/test/a32/traces/assembler-cond-rd-operand-const-a32-movs.h index 9df01fd7..52baa580 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-a32-movs.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-a32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-a32-mvn.h b/test/a32/traces/assembler-cond-rd-operand-const-a32-mvn.h index 4fd1bcd0..fd8d73de 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-a32-mvn.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-a32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-a32-mvns.h b/test/a32/traces/assembler-cond-rd-operand-const-a32-mvns.h index 62d50511..533e5e9c 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-a32-mvns.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-a32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-a32-teq.h b/test/a32/traces/assembler-cond-rd-operand-const-a32-teq.h index 3711ca2a..e8cebe7f 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-a32-teq.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-a32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-a32-tst.h b/test/a32/traces/assembler-cond-rd-operand-const-a32-tst.h index c114ffd7..1097c426 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-a32-tst.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-a32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-t32-cmn.h b/test/a32/traces/assembler-cond-rd-operand-const-t32-cmn.h index 6a59e834..3ff558d3 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-t32-cmn.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-t32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-t32-cmp.h b/test/a32/traces/assembler-cond-rd-operand-const-t32-cmp.h index 1bd80fcb..d835ad88 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-t32-cmp.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-t32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-t32-mov.h b/test/a32/traces/assembler-cond-rd-operand-const-t32-mov.h index 0da56c14..27ea59c6 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-t32-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-t32-movs.h b/test/a32/traces/assembler-cond-rd-operand-const-t32-movs.h index cc74dabb..263336a1 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-t32-movs.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-t32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-t32-mvn.h b/test/a32/traces/assembler-cond-rd-operand-const-t32-mvn.h index d7cf20e2..2264151c 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-t32-mvn.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-t32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-t32-mvns.h b/test/a32/traces/assembler-cond-rd-operand-const-t32-mvns.h index 3e4da4f0..42db2f0b 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-t32-mvns.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-t32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-t32-teq.h b/test/a32/traces/assembler-cond-rd-operand-const-t32-teq.h index 5a4b983b..7cbc9411 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-t32-teq.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-t32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-const-t32-tst.h b/test/a32/traces/assembler-cond-rd-operand-const-t32-tst.h index 36e5003c..c17e23a0 100644 --- a/test/a32/traces/assembler-cond-rd-operand-const-t32-tst.h +++ b/test/a32/traces/assembler-cond-rd-operand-const-t32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-imm16-t32-mov.h b/test/a32/traces/assembler-cond-rd-operand-imm16-t32-mov.h index 64ed5030..d4562307 100644 --- a/test/a32/traces/assembler-cond-rd-operand-imm16-t32-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-imm16-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-imm16-t32-movt.h b/test/a32/traces/assembler-cond-rd-operand-imm16-t32-movt.h index be5ebb69..28e14f73 100644 --- a/test/a32/traces/assembler-cond-rd-operand-imm16-t32-movt.h +++ b/test/a32/traces/assembler-cond-rd-operand-imm16-t32-movt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-imm16-t32-movw.h b/test/a32/traces/assembler-cond-rd-operand-imm16-t32-movw.h index c3e0332b..5ea149b1 100644 --- a/test/a32/traces/assembler-cond-rd-operand-imm16-t32-movw.h +++ b/test/a32/traces/assembler-cond-rd-operand-imm16-t32-movw.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-cmn.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-cmn.h index 584cb698..48152c97 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-cmn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-cmp.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-cmp.h index cf10bd3b..d9610d4e 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-cmp.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-mov.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-mov.h index 875d7818..9ec88e29 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-movs.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-movs.h index 153f4a3f..4cd302f8 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-movs.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-mvn.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-mvn.h index b9482e80..81cf7f1a 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-mvn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-mvns.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-mvns.h index dc434e6d..d32c391b 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-mvns.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-sxtb.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-sxtb.h index 0dae920e..c294795b 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-sxtb.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-sxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-sxtb16.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-sxtb16.h index 0e030612..49637a02 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-sxtb16.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-sxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-sxth.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-sxth.h index 98d7124c..f5697250 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-sxth.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-sxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-teq.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-teq.h index bc0933a3..0cc016cc 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-teq.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-tst.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-tst.h index f73efbba..137fb854 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-tst.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-uxtb.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-uxtb.h index 0a66c330..83c2bdc4 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-uxtb.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-uxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-uxtb16.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-uxtb16.h index 4694ec5b..858424f8 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-uxtb16.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-uxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-a32-uxth.h b/test/a32/traces/assembler-cond-rd-operand-rn-a32-uxth.h index d916f6ba..89d72ff2 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-a32-uxth.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-a32-uxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-sxtb.h b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-sxtb.h index 9abe5b18..bc8ea439 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-sxtb.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-sxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-sxtb16.h b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-sxtb16.h index 6cf2682e..ddf0266a 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-sxtb16.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-sxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-sxth.h b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-sxth.h index 25275540..976bf619 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-sxth.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-sxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-uxtb.h b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-uxtb.h index 76650b51..0b6e3a78 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-uxtb.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-uxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-uxtb16.h b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-uxtb16.h index 2761b1db..432aa75a 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-uxtb16.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-uxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-uxth.h b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-uxth.h index c8476778..719a4971 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-uxth.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-a32-uxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-sxtb.h b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-sxtb.h index fc72ece5..5a4fcaa7 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-sxtb.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-sxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-sxtb16.h b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-sxtb16.h index 1ec36897..d8b0ec05 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-sxtb16.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-sxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-sxth.h b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-sxth.h index 21aca6eb..c355a996 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-sxth.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-sxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-uxtb.h b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-uxtb.h index c42be764..6d91ab8c 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-uxtb.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-uxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-uxtb16.h b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-uxtb16.h index 23bc4ca9..18345a02 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-uxtb16.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-uxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-uxth.h b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-uxth.h index be594ca6..19195e25 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-uxth.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-uxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-cmn.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-cmn.h index 1a1dad2d..0e82822b 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-cmn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-cmp.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-cmp.h index 1825f92b..bc50a5f4 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-cmp.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-mov.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-mov.h index 6ecd30fc..e69ac7c2 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-movs.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-movs.h index 201fa984..bd9c3e77 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-movs.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-mvn.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-mvn.h index 5b9824e0..457d6c42 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-mvn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-mvns.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-mvns.h index 3eb3983b..939b52be 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-mvns.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-teq.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-teq.h index d7dcb7a7..d799585b 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-teq.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-tst.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-tst.h index b1283a3a..e72bb54d 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-tst.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-cmn.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-cmn.h index 0a2ff44d..44babec7 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-cmn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-cmp.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-cmp.h index 8c927217..a0a12be7 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-cmp.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-in-it-block-mov.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-in-it-block-mov.h index 81c9728e..7a19b8c5 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-in-it-block-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-in-it-block-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-mov.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-mov.h index 4778f56d..3e7c9da4 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-movs.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-movs.h index f9011546..6ddee1a5 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-movs.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-mvn.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-mvn.h index 28d96627..12c81301 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-mvn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-mvns.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-mvns.h index 5e536c9a..37d2ff7d 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-mvns.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-teq.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-teq.h index 2abb975d..a0a73e38 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-teq.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-tst.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-tst.h index 95cb43ba..1b7cb258 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-tst.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-cmn.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-cmn.h index 66cfa780..9ab93dd1 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-cmn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-cmp.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-cmp.h index f76b9a55..eb91f993 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-cmp.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mov.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mov.h index a81caa20..e3e4d6a2 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-movs.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-movs.h index 33dfbce6..3433aec6 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-movs.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mvn.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mvn.h index 88f5357b..f796e59f 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mvn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mvns.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mvns.h index d4a00784..612cf4a0 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mvns.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-teq.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-teq.h index 71f4d990..fb183faa 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-teq.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-tst.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-tst.h index 098edbec..85d234cb 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-tst.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-cmn.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-cmn.h index cbca445e..2d66248e 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-cmn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-cmp.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-cmp.h index 55343411..dfdcf544 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-cmp.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block-mov.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block-mov.h index e4cf7ecf..a71897a3 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-mov.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-mov.h index c3452f29..27b63bd6 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-movs.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-movs.h index 31e1c6bc..98987a84 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-movs.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-mvn.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-mvn.h index 920e85c3..07d870cd 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-mvn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-mvns.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-mvns.h index 6028a472..6859a52b 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-mvns.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-teq.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-teq.h index 36c86a04..7d9ff435 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-teq.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-tst.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-tst.h index 2fc53fc4..3769d7ff 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-tst.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-cmn.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-cmn.h index d462d196..3591a5b2 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-cmn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-cmp.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-cmp.h index d926b4c7..9531d8ed 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-cmp.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-mov.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-mov.h index e9d43b91..1329e302 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-movs.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-movs.h index 8d02be83..731065e3 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-movs.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-mvn.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-mvn.h index f4f3ace9..517b79a4 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-mvn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-mvns.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-mvns.h index 523459cb..d8f2dd9c 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-mvns.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-teq.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-teq.h index 7de00bdd..f3e061f7 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-teq.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-tst.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-tst.h index 8a74887c..2520be2e 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-tst.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block-mov.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block-mov.h index a1d50867..da907edd 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-mov.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-mov.h index b22ade14..2c58d325 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-movs.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-movs.h index 11ac516f..d047737b 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-movs.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block-movs.h b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block-movs.h index 1af03422..104ac252 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block-movs.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-cmn.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-cmn.h index a087de4e..34bfdb11 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-cmn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-cmp.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-cmp.h index 7e2c4840..d3c32f79 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-cmp.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-identical-low-registers-in-it-block-mvn.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-identical-low-registers-in-it-block-mvn.h index f8493589..dd9e66cf 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-identical-low-registers-in-it-block-mvn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-identical-low-registers-in-it-block-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-in-it-block-cmp.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-in-it-block-cmp.h index abdf330c..0fda62d2 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-in-it-block-cmp.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-in-it-block-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-in-it-block-mov.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-in-it-block-mov.h index cf280ddd..25889a3a 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-in-it-block-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-in-it-block-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-low-registers-in-it-block-cmn.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-low-registers-in-it-block-cmn.h index f8516b69..5d8d426e 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-low-registers-in-it-block-cmn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-low-registers-in-it-block-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-low-registers-in-it-block-tst.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-low-registers-in-it-block-tst.h index 5632d8fc..35e8ff60 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-low-registers-in-it-block-tst.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-low-registers-in-it-block-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-mov.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-mov.h index 33e05897..99e2c04e 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-mov.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-movs.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-movs.h index 9214fe84..d7f8ce02 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-movs.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-mvn.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-mvn.h index 116f63ff..85f1afd7 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-mvn.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-mvns.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-mvns.h index a214e7ef..3003069a 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-mvns.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-sxtb.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-sxtb.h index 79909f96..6597ea01 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-sxtb.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-sxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-sxtb16.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-sxtb16.h index a41bee44..a35b88d3 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-sxtb16.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-sxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-sxth.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-sxth.h index a050350b..ab383f84 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-sxth.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-sxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-teq.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-teq.h index 23bf0072..2e68a09f 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-teq.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-tst.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-tst.h index 83298e0f..e95add8c 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-tst.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-uxtb.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-uxtb.h index c5c6af35..fdaa8855 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-uxtb.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-uxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-uxtb16.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-uxtb16.h index 14de22cc..bb369338 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-uxtb16.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-uxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-operand-rn-t32-uxth.h b/test/a32/traces/assembler-cond-rd-operand-rn-t32-uxth.h index b4107bfb..417776f4 100644 --- a/test/a32/traces/assembler-cond-rd-operand-rn-t32-uxth.h +++ b/test/a32/traces/assembler-cond-rd-operand-rn-t32-uxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-pc-operand-imm12-t32-add.h b/test/a32/traces/assembler-cond-rd-pc-operand-imm12-t32-add.h index 2f45b818..a942174a 100644 --- a/test/a32/traces/assembler-cond-rd-pc-operand-imm12-t32-add.h +++ b/test/a32/traces/assembler-cond-rd-pc-operand-imm12-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-pc-operand-imm12-t32-addw.h b/test/a32/traces/assembler-cond-rd-pc-operand-imm12-t32-addw.h index ca270fca..6d347606 100644 --- a/test/a32/traces/assembler-cond-rd-pc-operand-imm12-t32-addw.h +++ b/test/a32/traces/assembler-cond-rd-pc-operand-imm12-t32-addw.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-pc-operand-imm12-t32-sub.h b/test/a32/traces/assembler-cond-rd-pc-operand-imm12-t32-sub.h index 6a12b430..472aff5a 100644 --- a/test/a32/traces/assembler-cond-rd-pc-operand-imm12-t32-sub.h +++ b/test/a32/traces/assembler-cond-rd-pc-operand-imm12-t32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-pc-operand-imm8-t32-add.h b/test/a32/traces/assembler-cond-rd-pc-operand-imm8-t32-add.h index 1272dbce..5dd7a17e 100644 --- a/test/a32/traces/assembler-cond-rd-pc-operand-imm8-t32-add.h +++ b/test/a32/traces/assembler-cond-rd-pc-operand-imm8-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-a32-clz.h b/test/a32/traces/assembler-cond-rd-rn-a32-clz.h index 02101b8a..eb2b70da 100644 --- a/test/a32/traces/assembler-cond-rd-rn-a32-clz.h +++ b/test/a32/traces/assembler-cond-rd-rn-a32-clz.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-a32-rbit.h b/test/a32/traces/assembler-cond-rd-rn-a32-rbit.h index e20e383c..9f885855 100644 --- a/test/a32/traces/assembler-cond-rd-rn-a32-rbit.h +++ b/test/a32/traces/assembler-cond-rd-rn-a32-rbit.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-a32-rev.h b/test/a32/traces/assembler-cond-rd-rn-a32-rev.h index d3ec573b..70ee1458 100644 --- a/test/a32/traces/assembler-cond-rd-rn-a32-rev.h +++ b/test/a32/traces/assembler-cond-rd-rn-a32-rev.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-a32-rev16.h b/test/a32/traces/assembler-cond-rd-rn-a32-rev16.h index a038f632..4d6f79fa 100644 --- a/test/a32/traces/assembler-cond-rd-rn-a32-rev16.h +++ b/test/a32/traces/assembler-cond-rd-rn-a32-rev16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-a32-revsh.h b/test/a32/traces/assembler-cond-rd-rn-a32-revsh.h index f99035f7..ca6c5e45 100644 --- a/test/a32/traces/assembler-cond-rd-rn-a32-revsh.h +++ b/test/a32/traces/assembler-cond-rd-rn-a32-revsh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-a32-rrx.h b/test/a32/traces/assembler-cond-rd-rn-a32-rrx.h index ee48ca35..4116c2ac 100644 --- a/test/a32/traces/assembler-cond-rd-rn-a32-rrx.h +++ b/test/a32/traces/assembler-cond-rd-rn-a32-rrx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-a32-rrxs.h b/test/a32/traces/assembler-cond-rd-rn-a32-rrxs.h index b4d820e8..70e7be3c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-a32-rrxs.h +++ b/test/a32/traces/assembler-cond-rd-rn-a32-rrxs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-adc.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-adc.h index 9dec5c46..0395b035 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-adc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-adcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-adcs.h index 2bc3ce28..cd78ca4d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-adcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-add.h index 32c66435..5386c099 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-adds.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-adds.h index b7403c2f..2ee21b65 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-adds.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-and.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-and.h index 98714b3e..c979ffab 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-and.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-ands.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-ands.h index 2722a0d7..24733e1c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-ands.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-bic.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-bic.h index 2ceee062..ea481b0f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-bic.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-bics.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-bics.h index 8c97602b..c005f47d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-bics.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-eor.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-eor.h index baf5d76b..8ab502bf 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-eor.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-eors.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-eors.h index b6365b3e..1c68eefc 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-eors.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-orr.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-orr.h index c2af11bc..3a57fd84 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-orr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-orrs.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-orrs.h index 7421c33b..bb7d9bc2 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-orrs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rsb.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rsb.h index 328d5912..121ffd8a 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rsb.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rsbs.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rsbs.h index 00436ae4..18999614 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rsbs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rsc.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rsc.h index f308a898..04280d95 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rsc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rsc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rscs.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rscs.h index 1e61341f..d2c769ed 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rscs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-rscs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-sbc.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-sbc.h index a61af212..82982905 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-sbc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-sbcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-sbcs.h index 029d0046..9c09bfff 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-sbcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-sub.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-sub.h index 1dd2ea2c..09cdc80f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-sub.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-subs.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-subs.h index ffdf6529..8be38ecb 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-subs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-a32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-adc.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-adc.h index 387b92be..b41f5296 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-adc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-adcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-adcs.h index 83f2c8f0..2b715655 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-adcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-add.h index 4c8a79c4..7690f8d0 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-adds.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-adds.h index 5068907f..7d3bb671 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-adds.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-and.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-and.h index 83369e3e..a9a7ef85 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-and.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-ands.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-ands.h index 75fa6e5b..238fd96e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-ands.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-bic.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-bic.h index a3b932e7..b95b896f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-bic.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-bics.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-bics.h index 9aa877f3..853b4293 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-bics.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-eor.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-eor.h index 51d6781d..8839c899 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-eor.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-eors.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-eors.h index 0359e3a3..e301510a 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-eors.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orn.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orn.h index 860cb503..be9526c1 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orn.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orns.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orns.h index 3655db0b..b4caa32f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orns.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orr.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orr.h index ca1ec1f1..38208545 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orrs.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orrs.h index 9056c90b..fbebbb0e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orrs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-rsb.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-rsb.h index 80cfea81..6146d3b6 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-rsb.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-rsbs.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-rsbs.h index 61f1c11d..a0bf583b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-rsbs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-sbc.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-sbc.h index dd731bc1..51c791a0 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-sbc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-sbcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-sbcs.h index 6295b63c..9c6d4a9c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-sbcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-sub.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-sub.h index 61292f7c..390ac3a4 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-sub.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-subs.h b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-subs.h index 47aa4c29..facd3171 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-subs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-const-t32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-add.h index 6ed6bd84..091ec1ab 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-addw.h b/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-addw.h index 73948859..64f0f217 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-addw.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-addw.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-sub.h b/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-sub.h index cd9853eb..dec54647 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-sub.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-subw.h b/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-subw.h index 43a5ae67..99a68a84 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-subw.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-imm12-t32-subw.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-adc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-adc.h index d8f8a8af..74a6ccff 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-adc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-adcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-adcs.h index 245d190b..ed6e5306 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-adcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-add.h index 9aa15e40..25614b38 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-adds.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-adds.h index 4431ac66..0fc2d090 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-adds.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-and.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-and.h index becf032c..b6e91b4d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-and.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-ands.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-ands.h index d19ba2e0..b1b9a164 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-ands.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-asr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-asr.h index 82721488..c293fd51 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-asr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-asr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-asrs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-asrs.h index e57d3d67..5bd6bbfb 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-asrs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-asrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-bic.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-bic.h index d2501ad3..70004f1a 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-bic.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-bics.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-bics.h index 6b98b310..d75dfcbf 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-bics.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-eor.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-eor.h index 52232dd3..f769b816 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-eor.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-eors.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-eors.h index 70786f69..03d2892c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-eors.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsl.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsl.h index d22866c0..94890edf 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsl.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsl.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsls.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsls.h index 22bc127e..65f63188 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsls.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsls.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsr.h index 022fc465..c78e9ce9 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsrs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsrs.h index a0725bc2..912e1f76 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsrs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-lsrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-orr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-orr.h index 42f4c07a..29559890 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-orr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-orrs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-orrs.h index 1170c31b..2161670d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-orrs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-ror.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-ror.h index 3176ff88..f2410698 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-ror.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-ror.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rors.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rors.h index ed602876..b1fc222f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rors.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsb.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsb.h index 362041c4..65d816de 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsb.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsbs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsbs.h index 6318c80e..7be11d45 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsbs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsc.h index be196868..ba9f6c0b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rsc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rscs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rscs.h index b5371c5d..be1010d1 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rscs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-rscs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sbc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sbc.h index baa6ca43..23dec971 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sbc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sbcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sbcs.h index 30e1b97b..77ba121c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sbcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sub.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sub.h index 075b9aa4..324b6ec6 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sub.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-subs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-subs.h index 204b9e17..476aa7e9 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-subs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sxtab.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sxtab.h index 6d16f46f..f9a58b5d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sxtab.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sxtab16.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sxtab16.h index d69fbcbc..848a6916 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sxtab16.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sxtah.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sxtah.h index 69cb6d0d..31a6b18f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sxtah.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-sxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-uxtab.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-uxtab.h index 0ad0efa0..97abba74 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-uxtab.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-uxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-uxtab16.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-uxtab16.h index 42f9c8f5..4682d6d0 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-uxtab16.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-uxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-uxtah.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-uxtah.h index 496fd3fd..7a6000b9 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-uxtah.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-a32-uxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtab.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtab.h index d9b09975..8620faf7 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtab.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtab16.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtab16.h index d80aa4e9..dfdc3d72 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtab16.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtah.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtah.h index fdc40968..c18ff1f2 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtah.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-sxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtab.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtab.h index 856abafe..1834b859 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtab.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtab16.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtab16.h index 0c1fd1ec..2bdab213 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtab16.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtah.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtah.h index e35cf740..059ba54c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtah.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-a32-uxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtab.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtab.h index bb36ee97..c713e1e5 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtab.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtab16.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtab16.h index 02d954f8..276b4c9f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtab16.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtah.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtah.h index 6b3420af..0e05637f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtah.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-sxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtab.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtab.h index c83d1c5c..88e218b5 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtab.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtab16.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtab16.h index 10167a21..489630f8 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtab16.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtah.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtah.h index 16935694..75c0cf25 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtah.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-ror-amount-t32-uxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adc.h index 698c2532..e0e984bc 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adcs.h index ce82ed0d..5cfce16e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-add.h index a0ed70d8..0c2978f7 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adds.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adds.h index e51d8fb3..fe943e34 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adds.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-and.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-and.h index df7c0280..950ae91b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-and.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-ands.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-ands.h index bfa5e3f6..d40f7d8c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-ands.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bic.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bic.h index 81e99d58..2301b10f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bic.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bics.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bics.h index ab791cc3..8dc24e2b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bics.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eor.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eor.h index 34f7090b..7d0c3d3c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eor.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eors.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eors.h index f137e62f..136c5177 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eors.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orr.h index fb6292ad..f6f60683 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orrs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orrs.h index 480e37db..03c6663a 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orrs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsb.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsb.h index 5bbd14c3..b064d027 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsb.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsbs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsbs.h index cbe13323..04dc99f4 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsbs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsc.h index 54bfe53a..7f2ee910 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rscs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rscs.h index a42d0732..67884b95 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rscs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rscs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbc.h index 85500c3b..d71c46d1 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbcs.h index 213ef8d0..74b5feec 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sub.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sub.h index d2b4483c..1bf1da94 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sub.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-subs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-subs.h index c0c5fb22..a2e7568d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-subs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adc.h index 85557cff..cbc4deb0 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adcs.h index bc0b203b..aefc8d1b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-add.h index f8276125..b321e7f7 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adds.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adds.h index 3a0e0cf2..8f1a0f51 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adds.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-and.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-and.h index 2f83b0ec..f517d54f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-and.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-ands.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-ands.h index beddd6cb..8dfb1a9d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-ands.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bic.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bic.h index aa692f92..bffb06ee 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bic.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bics.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bics.h index 5a71e1c7..4f6a6dd1 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bics.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eor.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eor.h index 3f3c8698..e02e499e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eor.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eors.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eors.h index 1dae9f9d..0223c53a 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eors.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orn.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orn.h index 2d66b7b6..100a8caa 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orn.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orns.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orns.h index 0dcad939..23679474 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orns.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orr.h index dde6b596..7e1a5e51 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orrs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orrs.h index c7ac0a16..53f9e343 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orrs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsb.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsb.h index c31fc089..bb1ff815 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsb.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsbs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsbs.h index 172b4df7..cba716be 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsbs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbc.h index 8bf9cb41..081f763d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbcs.h index f92b1077..e5190788 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sub.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sub.h index 6560bfd8..d9032d14 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sub.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-subs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-subs.h index ba19bae7..436ad35d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-subs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adc.h index ae41188a..1b1408ee 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adcs.h index 5c2a27e8..bcd38874 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-add.h index 944653f2..709e6820 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adds.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adds.h index fd6342f3..8ee7578f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adds.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-and.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-and.h index 46f79dab..e3e6aa4b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-and.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-ands.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-ands.h index 639370bd..794a4b9b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-ands.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bic.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bic.h index 21ef02ca..7cb824f4 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bic.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bics.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bics.h index 1e8a8a5d..bb109500 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bics.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eor.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eor.h index b409ed9b..87e5c5c2 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eor.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eors.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eors.h index 58bf5ecc..229ea236 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eors.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orr.h index 42831723..63039857 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orrs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orrs.h index 93750d5b..7246f567 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orrs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsb.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsb.h index 5460ab94..b2f629ab 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsb.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsbs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsbs.h index 4cb526a4..49ca1bef 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsbs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsc.h index d9d8b6a8..724239cf 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rscs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rscs.h index e5279273..3d89f841 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rscs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rscs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbc.h index bd267b8e..4cf9bbfe 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbcs.h index 7e1ae527..f89bfdca 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sub.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sub.h index fc09993e..5ab189ab 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sub.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-subs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-subs.h index 93623dcd..83db9753 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-subs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adc.h index a38de423..7fe20faa 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adcs.h index 9191d14f..8c6946f6 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-add.h index 71828af2..940c8996 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adds.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adds.h index a9d2ce2e..d911a63b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adds.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-and.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-and.h index f8008708..21a3513d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-and.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-ands.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-ands.h index 190722c6..967ac350 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-ands.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bic.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bic.h index 4adff4d7..fb908ab5 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bic.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bics.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bics.h index 331568e7..b29bac3a 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bics.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eor.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eor.h index ca2ae6df..31e770f2 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eor.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eors.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eors.h index a9324381..5e33737f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eors.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orn.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orn.h index b1eae848..f1fe595c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orn.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orns.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orns.h index f520e119..ad479878 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orns.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orr.h index 6ebf66db..0003183d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orrs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orrs.h index c3be8d7e..10934534 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orrs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsb.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsb.h index 772987b1..8a3b96ca 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsb.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsbs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsbs.h index 3286f66d..d16211a8 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsbs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbc.h index 2ee4759e..1614f421 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbcs.h index b9bf2f7a..f9c0a809 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sub.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sub.h index e8cfb069..e236b59e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sub.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-subs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-subs.h index 8743dc8b..04c68122 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-subs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-adc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-adc.h index 30b26c16..d21904bc 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-adc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-adcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-adcs.h index 3c2445db..22c711fd 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-adcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-add.h index 8b1efda3..5c64fe36 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-adds.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-adds.h index 22ba7c53..5f875157 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-adds.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-and.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-and.h index 9b6b4641..20b49e23 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-and.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-ands.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-ands.h index 045ec56d..92e1f693 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-ands.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-bic.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-bic.h index ace8064f..8d2b6f74 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-bic.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-bics.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-bics.h index 5fbdd62f..ac84fd25 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-bics.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-eor.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-eor.h index 86e8d6c6..801729b1 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-eor.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-eors.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-eors.h index 4ef0419f..7f19a3d2 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-eors.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-orr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-orr.h index 9e3b544d..2ebefaff 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-orr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-orrs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-orrs.h index bf7a2a80..6d570a5c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-orrs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsb.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsb.h index e8d89e4e..ca73dc8f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsb.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsbs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsbs.h index 6d0d2212..73e635c5 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsbs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsc.h index a897f304..55a8808e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rsc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rscs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rscs.h index 7131aef5..839dd383 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rscs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-rscs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-sbc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-sbc.h index 664472f9..db9a82bf 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-sbc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-sbcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-sbcs.h index f03cbd5a..12783a68 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-sbcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-sub.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-sub.h index 280ab069..d220c9f7 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-sub.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-subs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-subs.h index 05f044de..cb021e37 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-subs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-shift-rs-a32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-adc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-adc.h index 60b19db9..0d3b4dba 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-adc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-adcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-adcs.h index 679ff151..8fb00ae3 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-adcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-add.h index 7e1c148d..4eb5e9dc 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-adds.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-adds.h index b75d9631..f3958498 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-adds.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block-add.h index ab918646..bc774080 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block-sub.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block-sub.h index 8b19fa94..6e714210 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block-sub.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-adc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-adc.h index c9ef8cf6..17d6dd08 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-adc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-and.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-and.h index 6ab9dab7..61fe1ada 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-and.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-asr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-asr.h index 14937009..9103c886 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-asr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-asr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-bic.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-bic.h index f253d29c..fdd6b5dd 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-bic.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-eor.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-eor.h index 0eaddbbe..9608b86f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-eor.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-lsl.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-lsl.h index 9934dfc0..0daadfe1 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-lsl.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-lsl.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-lsr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-lsr.h index 3005d80b..4df122e5 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-lsr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-lsr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-orr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-orr.h index c104f661..3637fd3d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-orr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-ror.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-ror.h index d2b8a6d9..edb06c72 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-ror.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-ror.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-sbc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-sbc.h index b70efe78..90cf8389 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-sbc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-and.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-and.h index 2e14d4d8..982aeeda 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-and.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-ands.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-ands.h index b8b30bf2..c222c10e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-ands.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-asr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-asr.h index 38483e96..337df389 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-asr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-asr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-asrs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-asrs.h index e8518046..f3ead3bc 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-asrs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-asrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-bic.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-bic.h index c973d236..6a4bb0de 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-bic.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-bics.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-bics.h index ee214ad5..826917f8 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-bics.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-eor.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-eor.h index b0d05474..dcec4be8 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-eor.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-eors.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-eors.h index 17a0c78d..363aa7c1 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-eors.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsl.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsl.h index 45dcef39..1cc90e45 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsl.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsl.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsls.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsls.h index 6926066f..6ee3bf7d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsls.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsls.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsr.h index 70e2126f..f8c6bce8 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsrs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsrs.h index 1119893b..bc654c9c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsrs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-lsrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orn.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orn.h index 5e556e1e..4657faa5 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orn.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orns.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orns.h index d3371de6..c45d0631 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orns.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orr.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orr.h index dd428ec3..f8baba56 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orr.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orrs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orrs.h index 268232e8..1a30c903 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orrs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block-add.h index 43a194a7..95e83055 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-is-sp-in-it-block-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-is-sp-in-it-block-add.h index 4bc8899f..11d2eafa 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-is-sp-in-it-block-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-is-sp-in-it-block-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rn-is-sp-in-it-block-add.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rn-is-sp-in-it-block-add.h index 5c78b490..89cfd482 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rn-is-sp-in-it-block-add.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rn-is-sp-in-it-block-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-ror.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-ror.h index dc82b96a..03e2d98b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-ror.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-ror.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rors.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rors.h index 89cc1383..f4464d93 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rors.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rsb.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rsb.h index 1b682269..05dda63b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rsb.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rsbs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rsbs.h index 6f3766c1..95fc9b64 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rsbs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sbc.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sbc.h index 101aa327..1ae20bae 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sbc.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sbcs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sbcs.h index 9a944702..4b4084e0 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sbcs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sub.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sub.h index 407154f9..cc6df5ef 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sub.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-subs.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-subs.h index 0449cb7c..112f9c3e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-subs.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sxtab.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sxtab.h index cbd88aaa..b0cc5fc8 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sxtab.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sxtab16.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sxtab16.h index 70151a32..65313437 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sxtab16.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sxtah.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sxtah.h index 6a113b59..643c99c9 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sxtah.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-sxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-uxtab.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-uxtab.h index 26f96ea5..8ebfd51d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-uxtab.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-uxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-uxtab16.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-uxtab16.h index 479ccf1d..83595677 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-uxtab16.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-uxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-uxtah.h b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-uxtah.h index f8f74eb1..0a46e04c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-uxtah.h +++ b/test/a32/traces/assembler-cond-rd-rn-operand-rm-t32-uxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-mul.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-mul.h index 7950d918..a4359590 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-mul.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-mul.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-muls.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-muls.h index d45d27df..dba67420 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-muls.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-muls.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd.h index ebdaee80..e05e3cda 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd16.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd16.h index 324adaa0..5c13b104 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd8.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd8.h index 9186f887..e7b3c868 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qasx.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qasx.h index 67661fef..51842c5f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qasx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qdadd.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qdadd.h index 476aa507..ba82771f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qdadd.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qdadd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qdsub.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qdsub.h index 20010c3a..b1bbff46 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qdsub.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qdsub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsax.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsax.h index 333e1783..ca164236 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsax.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub.h index 73c1ecbe..241d99cd 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub16.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub16.h index 33062344..862bc3eb 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub8.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub8.h index fbad2446..2f75679c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-qsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-sadd16.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-sadd16.h index ecffeaec..757d6b17 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-sadd16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-sadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-sadd8.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-sadd8.h index dc337512..f6af34f8 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-sadd8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-sadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-sasx.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-sasx.h index bc6e652c..2fedea23 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-sasx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-sasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-sdiv.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-sdiv.h index 47cf6c04..77697596 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-sdiv.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-sdiv.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-sel.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-sel.h index 78b1ad79..59bfc3b1 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-sel.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-sel.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-shadd16.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-shadd16.h index fff22cc9..4ff8f1b3 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-shadd16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-shadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-shadd8.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-shadd8.h index eaa57fd5..a1a48662 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-shadd8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-shadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-shasx.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-shasx.h index d0ddd25d..692e5511 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-shasx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-shasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-shsax.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-shsax.h index 093f0c41..0b98da0b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-shsax.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-shsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-shsub16.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-shsub16.h index e58a95bc..cf3cf385 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-shsub16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-shsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-shsub8.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-shsub8.h index b62809de..96ffb553 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-shsub8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-shsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smmul.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smmul.h index eeb66c8d..e6806994 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smmul.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smmul.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smmulr.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smmulr.h index 52b94426..e5f26f6f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smmulr.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smmulr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smuad.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smuad.h index d2ec3b52..6e9ddec5 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smuad.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smuad.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smuadx.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smuadx.h index 46470f7b..91a68d53 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smuadx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smuadx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulbb.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulbb.h index 914621fd..14ab3e77 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulbb.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulbb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulbt.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulbt.h index ad307592..b7b12f33 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulbt.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulbt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smultb.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smultb.h index d5dcbd69..57fbb2a0 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smultb.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smultb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smultt.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smultt.h index 1f3e16ef..b9857c3f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smultt.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smultt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulwb.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulwb.h index b5e7c644..bb83919a 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulwb.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulwb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulwt.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulwt.h index 6b013959..334ede54 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulwt.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smulwt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smusd.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smusd.h index 5984b180..8a86cc60 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smusd.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smusd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smusdx.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smusdx.h index dd939787..25c17f03 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-smusdx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-smusdx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-ssax.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-ssax.h index d745c7b9..8e474400 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-ssax.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-ssax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-ssub16.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-ssub16.h index c681c321..887b04ac 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-ssub16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-ssub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-ssub8.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-ssub8.h index 5011d521..2f34d09d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-ssub8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-ssub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uadd16.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uadd16.h index 33f9c37c..07d1b222 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uadd16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uadd8.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uadd8.h index ee4e94d5..f1d4612d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uadd8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uasx.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uasx.h index 91150c1b..0fa32ddf 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uasx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-udiv.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-udiv.h index bb8f6242..6fb0c1df 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-udiv.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-udiv.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhadd16.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhadd16.h index f59a0969..964225fe 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhadd16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhadd8.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhadd8.h index d6674f92..659140ba 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhadd8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhasx.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhasx.h index 65b96c88..a94763a4 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhasx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsax.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsax.h index 948504a1..25e93203 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsax.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsub16.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsub16.h index f9c12dd6..3516e634 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsub16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsub8.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsub8.h index 31c1517e..e751d897 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsub8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uhsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqadd16.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqadd16.h index 4286fc44..8faec293 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqadd16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqadd8.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqadd8.h index bd359d5b..a7da6b7f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqadd8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqasx.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqasx.h index 305ce43a..bae64776 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqasx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsax.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsax.h index cc4abe2a..abe81366 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsax.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsub16.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsub16.h index a8ae6ced..43d2c526 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsub16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsub8.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsub8.h index 7c589adc..7955679e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsub8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-uqsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-usad8.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-usad8.h index ba64f95c..8efd2223 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-usad8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-usad8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-usax.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-usax.h index 9bf41ad0..f6f91d3b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-usax.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-usax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-usub16.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-usub16.h index 17ad79a0..b129d0d7 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-usub16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-usub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-a32-usub8.h b/test/a32/traces/assembler-cond-rd-rn-rm-a32-usub8.h index 6133c9ed..c00f7d22 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-a32-usub8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-a32-usub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-mul.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-mul.h index 85f012dd..28fe7d45 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-mul.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-mul.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd.h index 005b9f06..f3ec878c 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd16.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd16.h index d3ec8e81..a551d38e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd8.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd8.h index 700ad62b..527ef1e4 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qasx.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qasx.h index 79c2cc49..8d1c27e0 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qasx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qdadd.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qdadd.h index 9579f60e..fac2f83d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qdadd.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qdadd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qdsub.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qdsub.h index 34cae2ac..ccfbe4b0 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qdsub.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qdsub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsax.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsax.h index 141d8228..b3ec21ed 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsax.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub.h index 6d1f30cc..63b6cc71 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub16.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub16.h index 026d843f..cac44ccf 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub8.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub8.h index d5e8fcf5..3251bc2f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-qsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-sadd16.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-sadd16.h index 5ff90261..09abd6ff 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-sadd16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-sadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-sadd8.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-sadd8.h index 4d828c2a..e293db70 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-sadd8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-sadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-sasx.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-sasx.h index 3f50fb5b..3ba5f458 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-sasx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-sasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-sdiv.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-sdiv.h index 6d987d84..f427af14 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-sdiv.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-sdiv.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-sel.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-sel.h index 957dc2b2..609a4cb0 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-sel.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-sel.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-shadd16.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-shadd16.h index ee1cc9d1..9502b305 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-shadd16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-shadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-shadd8.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-shadd8.h index b499ef0d..8def748d 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-shadd8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-shadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-shasx.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-shasx.h index 8d11bc20..bc887dc4 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-shasx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-shasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-shsax.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-shsax.h index 5553863e..3c04b8b1 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-shsax.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-shsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-shsub16.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-shsub16.h index f87cf1a6..95b48517 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-shsub16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-shsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-shsub8.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-shsub8.h index 149b2399..e5bd0ca3 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-shsub8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-shsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smmul.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smmul.h index 2dd3f038..edf3e200 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smmul.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smmul.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smmulr.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smmulr.h index 27df603c..164c2ae0 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smmulr.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smmulr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smuad.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smuad.h index 479a1b2b..736b1ec1 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smuad.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smuad.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smuadx.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smuadx.h index 1d701a47..7d830bfd 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smuadx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smuadx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulbb.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulbb.h index 004c8682..9f2e6126 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulbb.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulbb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulbt.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulbt.h index f81588a1..95c9dbe1 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulbt.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulbt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smultb.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smultb.h index cddfddde..5b974223 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smultb.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smultb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smultt.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smultt.h index 89846861..f0f47154 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smultt.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smultt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulwb.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulwb.h index df05c490..9cba5703 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulwb.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulwb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulwt.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulwt.h index dbdc02ee..9287fe4e 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulwt.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smulwt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smusd.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smusd.h index 2addbd91..a85b2478 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smusd.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smusd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smusdx.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smusdx.h index 99be8c1c..e7eb92ea 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-smusdx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-smusdx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-ssax.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-ssax.h index 08b5caf3..81f8d437 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-ssax.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-ssax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-ssub16.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-ssub16.h index 59a5a841..10bf2bfe 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-ssub16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-ssub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-ssub8.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-ssub8.h index e4291693..236a9179 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-ssub8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-ssub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uadd16.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uadd16.h index 874a2e16..9eef63fb 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uadd16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uadd8.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uadd8.h index b49dc7bc..d7de9d41 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uadd8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uasx.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uasx.h index 581a02af..f28cef54 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uasx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-udiv.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-udiv.h index e252b48b..aa49b5a6 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-udiv.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-udiv.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhadd16.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhadd16.h index 101522f4..e7f284ee 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhadd16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhadd8.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhadd8.h index f068fd93..fa778bc6 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhadd8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhasx.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhasx.h index 26f822c5..dfb783df 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhasx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsax.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsax.h index ef17c0e2..caf8b627 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsax.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsub16.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsub16.h index b7bcfb36..561e4084 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsub16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsub8.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsub8.h index e5bfc24e..81ba0db0 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsub8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uhsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqadd16.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqadd16.h index c491c573..5a2a9734 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqadd16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqadd8.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqadd8.h index 8b8ee51f..0c020867 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqadd8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqasx.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqasx.h index cf8f1304..3192bb35 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqasx.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsax.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsax.h index f914067d..1da61182 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsax.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsub16.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsub16.h index fc35046f..4cb5c4de 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsub16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsub8.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsub8.h index 01f3f5e7..e555ec8a 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsub8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-uqsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-usad8.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-usad8.h index a275e6e9..5eabbb1b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-usad8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-usad8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-usax.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-usax.h index b315795b..2426db73 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-usax.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-usax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-usub16.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-usub16.h index fba54b81..33297e80 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-usub16.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-usub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-rm-t32-usub8.h b/test/a32/traces/assembler-cond-rd-rn-rm-t32-usub8.h index 9dac8d9c..807ef7f0 100644 --- a/test/a32/traces/assembler-cond-rd-rn-rm-t32-usub8.h +++ b/test/a32/traces/assembler-cond-rd-rn-rm-t32-usub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-t32-clz.h b/test/a32/traces/assembler-cond-rd-rn-t32-clz.h index d65ed2b2..0658d7d4 100644 --- a/test/a32/traces/assembler-cond-rd-rn-t32-clz.h +++ b/test/a32/traces/assembler-cond-rd-rn-t32-clz.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-t32-rbit.h b/test/a32/traces/assembler-cond-rd-rn-t32-rbit.h index 78674175..fc6efbf3 100644 --- a/test/a32/traces/assembler-cond-rd-rn-t32-rbit.h +++ b/test/a32/traces/assembler-cond-rd-rn-t32-rbit.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-t32-rev.h b/test/a32/traces/assembler-cond-rd-rn-t32-rev.h index 9bc93cc2..ee932f26 100644 --- a/test/a32/traces/assembler-cond-rd-rn-t32-rev.h +++ b/test/a32/traces/assembler-cond-rd-rn-t32-rev.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-t32-rev16.h b/test/a32/traces/assembler-cond-rd-rn-t32-rev16.h index 966834a6..a0410226 100644 --- a/test/a32/traces/assembler-cond-rd-rn-t32-rev16.h +++ b/test/a32/traces/assembler-cond-rd-rn-t32-rev16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-t32-revsh.h b/test/a32/traces/assembler-cond-rd-rn-t32-revsh.h index a0d4ba72..545f3d0f 100644 --- a/test/a32/traces/assembler-cond-rd-rn-t32-revsh.h +++ b/test/a32/traces/assembler-cond-rd-rn-t32-revsh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-t32-rrx.h b/test/a32/traces/assembler-cond-rd-rn-t32-rrx.h index 42dc0b49..025a141b 100644 --- a/test/a32/traces/assembler-cond-rd-rn-t32-rrx.h +++ b/test/a32/traces/assembler-cond-rd-rn-t32-rrx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-rn-t32-rrxs.h b/test/a32/traces/assembler-cond-rd-rn-t32-rrxs.h index bb7744ff..fd6d45b3 100644 --- a/test/a32/traces/assembler-cond-rd-rn-t32-rrxs.h +++ b/test/a32/traces/assembler-cond-rd-rn-t32-rrxs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rd-sp-operand-imm8-t32-add.h b/test/a32/traces/assembler-cond-rd-sp-operand-imm8-t32-add.h index 212327d4..9bcac96b 100644 --- a/test/a32/traces/assembler-cond-rd-sp-operand-imm8-t32-add.h +++ b/test/a32/traces/assembler-cond-rd-sp-operand-imm8-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-cmp.h b/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-cmp.h index 5d0c5713..f05c712c 100644 --- a/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-cmp.h +++ b/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-in-it-block-cmp.h b/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-in-it-block-cmp.h index 2cf5c244..6c28249d 100644 --- a/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-in-it-block-cmp.h +++ b/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-in-it-block-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-in-it-block-mov.h b/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-in-it-block-mov.h index aa13a88a..d50e03b8 100644 --- a/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-in-it-block-mov.h +++ b/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-in-it-block-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-mov.h b/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-mov.h index 7b0ba803..fb859afe 100644 --- a/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-mov.h +++ b/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-movs.h b/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-movs.h index 472455fa..0d55a3b4 100644 --- a/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-movs.h +++ b/test/a32/traces/assembler-cond-rdlow-operand-imm8-t32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-adds.h b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-adds.h index f9de6f49..eef6744b 100644 --- a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-adds.h +++ b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block-add.h b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block-add.h index 136b6f9a..76fca09c 100644 --- a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block-add.h +++ b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block-sub.h b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block-sub.h index 9e779c29..cefa239f 100644 --- a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block-sub.h +++ b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-subs.h b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-subs.h index fb5b17f4..06dfa6e6 100644 --- a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-subs.h +++ b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-adds.h b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-adds.h index 7229de63..c0aa75b1 100644 --- a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-adds.h +++ b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block-add.h b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block-add.h index a6339f7f..b09ad48b 100644 --- a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block-add.h +++ b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block-sub.h b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block-sub.h index 59767bd4..093aef4c 100644 --- a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block-sub.h +++ b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-subs.h b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-subs.h index 40ff206d..42ab0dee 100644 --- a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-subs.h +++ b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block-rsb.h b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block-rsb.h index a4eda89f..c245714c 100644 --- a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block-rsb.h +++ b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-rsbs.h b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-rsbs.h index cadc411f..a3a1d10a 100644 --- a/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-rsbs.h +++ b/test/a32/traces/assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block-mul.h b/test/a32/traces/assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block-mul.h index daa497de..f8020ba1 100644 --- a/test/a32/traces/assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block-mul.h +++ b/test/a32/traces/assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block-mul.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-rdlow-rnlow-rmlow-t32-muls.h b/test/a32/traces/assembler-cond-rdlow-rnlow-rmlow-t32-muls.h index 2f27a3be..29c0a203 100644 --- a/test/a32/traces/assembler-cond-rdlow-rnlow-rmlow-t32-muls.h +++ b/test/a32/traces/assembler-cond-rdlow-rnlow-rmlow-t32-muls.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-sp-sp-operand-imm7-t32-add.h b/test/a32/traces/assembler-cond-sp-sp-operand-imm7-t32-add.h index 48faeebc..27118b81 100644 --- a/test/a32/traces/assembler-cond-sp-sp-operand-imm7-t32-add.h +++ b/test/a32/traces/assembler-cond-sp-sp-operand-imm7-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-cond-sp-sp-operand-imm7-t32-sub.h b/test/a32/traces/assembler-cond-sp-sp-operand-imm7-t32-sub.h index e7e0eb88..adf26a47 100644 --- a/test/a32/traces/assembler-cond-sp-sp-operand-imm7-t32-sub.h +++ b/test/a32/traces/assembler-cond-sp-sp-operand-imm7-t32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-rd-rn-rm-a32-crc32b.h b/test/a32/traces/assembler-rd-rn-rm-a32-crc32b.h index 8aec6f3d..4e8b3117 100644 --- a/test/a32/traces/assembler-rd-rn-rm-a32-crc32b.h +++ b/test/a32/traces/assembler-rd-rn-rm-a32-crc32b.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-rd-rn-rm-a32-crc32cb.h b/test/a32/traces/assembler-rd-rn-rm-a32-crc32cb.h index 4d15396b..6b7bc453 100644 --- a/test/a32/traces/assembler-rd-rn-rm-a32-crc32cb.h +++ b/test/a32/traces/assembler-rd-rn-rm-a32-crc32cb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-rd-rn-rm-a32-crc32ch.h b/test/a32/traces/assembler-rd-rn-rm-a32-crc32ch.h index 5fb2377b..5d40af5b 100644 --- a/test/a32/traces/assembler-rd-rn-rm-a32-crc32ch.h +++ b/test/a32/traces/assembler-rd-rn-rm-a32-crc32ch.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-rd-rn-rm-a32-crc32cw.h b/test/a32/traces/assembler-rd-rn-rm-a32-crc32cw.h index 38a4a656..c031a2d4 100644 --- a/test/a32/traces/assembler-rd-rn-rm-a32-crc32cw.h +++ b/test/a32/traces/assembler-rd-rn-rm-a32-crc32cw.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-rd-rn-rm-a32-crc32h.h b/test/a32/traces/assembler-rd-rn-rm-a32-crc32h.h index ea66ed92..cc2067a4 100644 --- a/test/a32/traces/assembler-rd-rn-rm-a32-crc32h.h +++ b/test/a32/traces/assembler-rd-rn-rm-a32-crc32h.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-rd-rn-rm-a32-crc32w.h b/test/a32/traces/assembler-rd-rn-rm-a32-crc32w.h index c52512da..2d60b1dd 100644 --- a/test/a32/traces/assembler-rd-rn-rm-a32-crc32w.h +++ b/test/a32/traces/assembler-rd-rn-rm-a32-crc32w.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-rd-rn-rm-t32-crc32b.h b/test/a32/traces/assembler-rd-rn-rm-t32-crc32b.h index 5095a307..8cf0a863 100644 --- a/test/a32/traces/assembler-rd-rn-rm-t32-crc32b.h +++ b/test/a32/traces/assembler-rd-rn-rm-t32-crc32b.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-rd-rn-rm-t32-crc32cb.h b/test/a32/traces/assembler-rd-rn-rm-t32-crc32cb.h index 7f5c110a..f4c136d5 100644 --- a/test/a32/traces/assembler-rd-rn-rm-t32-crc32cb.h +++ b/test/a32/traces/assembler-rd-rn-rm-t32-crc32cb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-rd-rn-rm-t32-crc32ch.h b/test/a32/traces/assembler-rd-rn-rm-t32-crc32ch.h index 89eb75fc..2764d7cd 100644 --- a/test/a32/traces/assembler-rd-rn-rm-t32-crc32ch.h +++ b/test/a32/traces/assembler-rd-rn-rm-t32-crc32ch.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-rd-rn-rm-t32-crc32cw.h b/test/a32/traces/assembler-rd-rn-rm-t32-crc32cw.h index 1d4825d7..fbcc6a7a 100644 --- a/test/a32/traces/assembler-rd-rn-rm-t32-crc32cw.h +++ b/test/a32/traces/assembler-rd-rn-rm-t32-crc32cw.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-rd-rn-rm-t32-crc32h.h b/test/a32/traces/assembler-rd-rn-rm-t32-crc32h.h index b8c25ce5..68bcda7c 100644 --- a/test/a32/traces/assembler-rd-rn-rm-t32-crc32h.h +++ b/test/a32/traces/assembler-rd-rn-rm-t32-crc32h.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/assembler-rd-rn-rm-t32-crc32w.h b/test/a32/traces/assembler-rd-rn-rm-t32-crc32w.h index 870d8834..9dfa6191 100644 --- a/test/a32/traces/assembler-rd-rn-rm-t32-crc32w.h +++ b/test/a32/traces/assembler-rd-rn-rm-t32-crc32w.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-ldrh.h b/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-ldrh.h index c999c9e4..f2b028ce 100644 --- a/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-ldrh.h +++ b/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-ldrh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-ldrsb.h b/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-ldrsb.h index 7db75c1d..68a5e05a 100644 --- a/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-ldrsb.h +++ b/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-ldrsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-ldrsh.h b/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-ldrsh.h index 2025e2d2..2ced3bb2 100644 --- a/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-ldrsh.h +++ b/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-ldrsh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-strh.h b/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-strh.h index e46ba84d..816c3739 100644 --- a/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-strh.h +++ b/test/a32/traces/simulator-cond-rd-memop-immediate-512-a32-strh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-ldr.h b/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-ldr.h index 38311195..62ffe5bd 100644 --- a/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-ldr.h +++ b/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-ldr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-ldrb.h b/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-ldrb.h index b8f177a6..a892db61 100644 --- a/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-ldrb.h +++ b/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-ldrb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-str.h b/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-str.h index 608b90d4..d52bd1f3 100644 --- a/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-str.h +++ b/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-str.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-strb.h b/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-strb.h index 6743c04c..5b63cf77 100644 --- a/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-strb.h +++ b/test/a32/traces/simulator-cond-rd-memop-immediate-8192-a32-strb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldr.h b/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldr.h index 051bdcea..ec2fb68e 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldr.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrb.h b/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrb.h index 35d69156..c86918eb 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrb.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrh.h b/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrh.h index 3cb038d6..9d14899b 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrh.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrsb.h b/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrsb.h index a33650e8..5502f5a4 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrsb.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrsh.h b/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrsh.h index e0c55fce..840a5843 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrsh.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-a32-ldrsh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-a32-str.h b/test/a32/traces/simulator-cond-rd-memop-rs-a32-str.h index dad8f166..1ebb8f62 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-a32-str.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-a32-str.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-a32-strb.h b/test/a32/traces/simulator-cond-rd-memop-rs-a32-strb.h index 97e82ae9..ddefd468 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-a32-strb.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-a32-strb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-a32-strh.h b/test/a32/traces/simulator-cond-rd-memop-rs-a32-strh.h index ed640dd6..eb990ff0 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-a32-strh.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-a32-strh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-ldr.h b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-ldr.h index 31789523..507ee223 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-ldr.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-ldr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-ldrb.h b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-ldrb.h index bd0f8804..a7d43a33 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-ldrb.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-ldrb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-str.h b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-str.h index f7d4ca77..b6726bdb 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-str.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-str.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-strb.h b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-strb.h index f6d4c354..68c110ff 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-strb.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to31-a32-strb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-ldr.h b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-ldr.h index b0ce0ab1..c0ef071e 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-ldr.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-ldr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-ldrb.h b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-ldrb.h index 154ecf0f..fd84eaca 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-ldrb.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-ldrb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-str.h b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-str.h index 0209b858..482e83dd 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-str.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-str.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-strb.h b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-strb.h index 6634ed4d..3b77afbd 100644 --- a/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-strb.h +++ b/test/a32/traces/simulator-cond-rd-memop-rs-shift-amount-1to32-a32-strb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-a32-cmn.h b/test/a32/traces/simulator-cond-rd-operand-const-a32-cmn.h index 773b9258..46b5aeb5 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-a32-cmn.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-a32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-a32-cmp.h b/test/a32/traces/simulator-cond-rd-operand-const-a32-cmp.h index dda511ab..61b08a50 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-a32-cmp.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-a32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-a32-mov.h b/test/a32/traces/simulator-cond-rd-operand-const-a32-mov.h index a57915c0..84c341f9 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-a32-mov.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-a32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-a32-movs.h b/test/a32/traces/simulator-cond-rd-operand-const-a32-movs.h index c75856e8..b78cdbea 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-a32-movs.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-a32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-a32-mvn.h b/test/a32/traces/simulator-cond-rd-operand-const-a32-mvn.h index 8ddaf3ac..a22fbd86 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-a32-mvn.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-a32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-a32-mvns.h b/test/a32/traces/simulator-cond-rd-operand-const-a32-mvns.h index fb100533..ef85fadb 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-a32-mvns.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-a32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-a32-teq.h b/test/a32/traces/simulator-cond-rd-operand-const-a32-teq.h index 45190401..320f5280 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-a32-teq.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-a32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-a32-tst.h b/test/a32/traces/simulator-cond-rd-operand-const-a32-tst.h index c9ca5d64..cdd945aa 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-a32-tst.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-a32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-t32-cmn.h b/test/a32/traces/simulator-cond-rd-operand-const-t32-cmn.h index 1b872a40..ff83eb37 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-t32-cmn.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-t32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-t32-cmp.h b/test/a32/traces/simulator-cond-rd-operand-const-t32-cmp.h index 62626f88..14aad86d 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-t32-cmp.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-t32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-t32-mov.h b/test/a32/traces/simulator-cond-rd-operand-const-t32-mov.h index 6f81aec7..6022cbfc 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-t32-mov.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-t32-movs.h b/test/a32/traces/simulator-cond-rd-operand-const-t32-movs.h index a38073a4..6502b9c4 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-t32-movs.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-t32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-t32-mvn.h b/test/a32/traces/simulator-cond-rd-operand-const-t32-mvn.h index 8964d365..f8d9a7ac 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-t32-mvn.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-t32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-t32-mvns.h b/test/a32/traces/simulator-cond-rd-operand-const-t32-mvns.h index d2413456..fead00b9 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-t32-mvns.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-t32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-t32-teq.h b/test/a32/traces/simulator-cond-rd-operand-const-t32-teq.h index 10110781..1cb54b85 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-t32-teq.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-t32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-const-t32-tst.h b/test/a32/traces/simulator-cond-rd-operand-const-t32-tst.h index 605948af..2c33e765 100644 --- a/test/a32/traces/simulator-cond-rd-operand-const-t32-tst.h +++ b/test/a32/traces/simulator-cond-rd-operand-const-t32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-imm16-t32-mov.h b/test/a32/traces/simulator-cond-rd-operand-imm16-t32-mov.h index 7c386051..f229d5e2 100644 --- a/test/a32/traces/simulator-cond-rd-operand-imm16-t32-mov.h +++ b/test/a32/traces/simulator-cond-rd-operand-imm16-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-imm16-t32-movt.h b/test/a32/traces/simulator-cond-rd-operand-imm16-t32-movt.h index 1ddacf35..f9ff9af6 100644 --- a/test/a32/traces/simulator-cond-rd-operand-imm16-t32-movt.h +++ b/test/a32/traces/simulator-cond-rd-operand-imm16-t32-movt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-imm16-t32-movw.h b/test/a32/traces/simulator-cond-rd-operand-imm16-t32-movw.h index 5eed6060..cdde9fc8 100644 --- a/test/a32/traces/simulator-cond-rd-operand-imm16-t32-movw.h +++ b/test/a32/traces/simulator-cond-rd-operand-imm16-t32-movw.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-cmn.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-cmn.h index b1e8d305..f3aa3eee 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-cmn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-cmp.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-cmp.h index 05f804e2..34cad612 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-cmp.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-mov.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-mov.h index 3fc8bbd3..8ba62c0e 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-mov.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-movs.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-movs.h index 2b16be90..d92b2b76 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-movs.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-mvn.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-mvn.h index ee4e45c7..47631b01 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-mvn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-mvns.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-mvns.h index 8fade2cd..36f8fb40 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-mvns.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-sxtb.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-sxtb.h index 8af186bc..a8f63bd6 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-sxtb.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-sxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-sxtb16.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-sxtb16.h index 2912bc86..57e3ab74 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-sxtb16.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-sxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-sxth.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-sxth.h index e60a698e..afa112ba 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-sxth.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-sxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-teq.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-teq.h index 8f3bf349..1d49edad 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-teq.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-tst.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-tst.h index a799e8ed..939caba1 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-tst.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-uxtb.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-uxtb.h index 25a3ac5c..090cc6ba 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-uxtb.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-uxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-uxtb16.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-uxtb16.h index ab9cc1cf..5d8615da 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-uxtb16.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-uxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-a32-uxth.h b/test/a32/traces/simulator-cond-rd-operand-rn-a32-uxth.h index 29c89585..242ffab9 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-a32-uxth.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-a32-uxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxtb.h b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxtb.h index e9361007..ac5752ca 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxtb.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxtb16.h b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxtb16.h index 303cc11b..36c627fe 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxtb16.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxth.h b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxth.h index 64249d10..e716fc2f 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxth.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxtb.h b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxtb.h index af6e3a62..ed94a3da 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxtb.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxtb16.h b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxtb16.h index 28e430a3..9b01b9bc 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxtb16.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxth.h b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxth.h index 8598bb75..b5590a26 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxth.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxtb.h b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxtb.h index 88239382..f6c315da 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxtb.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxtb16.h b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxtb16.h index 96ef8c26..1ddc21bd 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxtb16.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxth.h b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxth.h index 95ddba40..0b7ed755 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxth.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxtb.h b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxtb.h index c3358ff4..a6d6210c 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxtb.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxtb16.h b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxtb16.h index d920dc7d..6d549bce 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxtb16.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxth.h b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxth.h index b0549c3b..c4e22bb1 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxth.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-cmn.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-cmn.h index 0b708bc0..c61b491e 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-cmn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-cmp.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-cmp.h index 32006eeb..815bc601 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-cmp.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mov.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mov.h index cc81204a..7e3b1da6 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mov.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-movs.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-movs.h index d170e47d..5e1f0e20 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-movs.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mvn.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mvn.h index 0686119d..7546c541 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mvn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mvns.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mvns.h index 5c7afe89..1912a29e 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mvns.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-teq.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-teq.h index dbbfb631..de8ef29c 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-teq.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-tst.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-tst.h index bb283d10..40a96484 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-tst.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-cmn.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-cmn.h index 5557d45d..426c08c3 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-cmn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-cmp.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-cmp.h index b1da5a0e..f4e9f64c 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-cmp.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-mov.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-mov.h index 859431f4..71081310 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-mov.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-movs.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-movs.h index 6ad692ce..13306f97 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-movs.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-mvn.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-mvn.h index ca3f5c4f..c71f41de 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-mvn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-mvns.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-mvns.h index 758a37e4..5d7ba5c8 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-mvns.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-teq.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-teq.h index b871ecb4..720b7af4 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-teq.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-tst.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-tst.h index a13c599f..970e0185 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-tst.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-t32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-cmn.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-cmn.h index f57a5e55..b4eee5f6 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-cmn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-cmp.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-cmp.h index 817d4d25..2a1f4638 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-cmp.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mov.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mov.h index 1fd9db2b..4ed8cc1d 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mov.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-movs.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-movs.h index 4120414a..f13f2c65 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-movs.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mvn.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mvn.h index ac7f56ac..7bb9ea9e 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mvn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mvns.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mvns.h index 1a7d9a59..fd4dc852 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mvns.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-teq.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-teq.h index 746aa395..6913f921 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-teq.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-tst.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-tst.h index 845f2d65..2a1566be 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-tst.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-a32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-cmn.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-cmn.h index 93f91fa1..78f95320 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-cmn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-cmp.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-cmp.h index 9182c040..83beb4cf 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-cmp.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-mov.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-mov.h index eb79603f..5f5cb440 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-mov.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-movs.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-movs.h index fc5c15d8..059a5038 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-movs.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-mvn.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-mvn.h index 4b81a317..bea52899 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-mvn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-mvns.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-mvns.h index cb04a6e8..229bea7a 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-mvns.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-teq.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-teq.h index eb2f3696..a2cc63ad 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-teq.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-tst.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-tst.h index 5301c759..7539409a 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-tst.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-t32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-cmn.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-cmn.h index fa9eebd3..670188e1 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-cmn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-cmp.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-cmp.h index ff44d9f8..786e7673 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-cmp.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-mov.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-mov.h index 6f8c7af6..71788e4a 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-mov.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-movs.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-movs.h index f639c17f..5355a4f8 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-movs.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-mvn.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-mvn.h index 9cf061de..1ebcea70 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-mvn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-mvns.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-mvns.h index a1f91dac..339ad400 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-mvns.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-teq.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-teq.h index f77d4f67..81d38c9c 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-teq.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-tst.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-tst.h index f67bb220..250d3690 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-tst.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-a32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-t32-mov.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-t32-mov.h index a6adbdd7..c6d0a012 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-t32-mov.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-t32-movs.h b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-t32-movs.h index 20f3eec7..1d6b6d40 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-t32-movs.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-shift-rs-t32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-cmn.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-cmn.h index 8f320bb5..8605890d 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-cmn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-cmn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-cmp.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-cmp.h index 8b457675..c8072e5f 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-cmp.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-mov.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-mov.h index a278840c..fe1945b2 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-mov.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-movs.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-movs.h index 98faa239..f56e8842 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-movs.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-mvn.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-mvn.h index 3b102d6a..6a0806e8 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-mvn.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-mvn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-mvns.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-mvns.h index 832d9602..5de82847 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-mvns.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-mvns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-sxtb.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-sxtb.h index f8f5ee0d..553f386d 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-sxtb.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-sxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-sxtb16.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-sxtb16.h index a9733ff4..9e7418a0 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-sxtb16.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-sxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-sxth.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-sxth.h index 568bdf90..a6ade4d6 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-sxth.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-sxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-teq.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-teq.h index 6b7ef132..6b986b61 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-teq.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-teq.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-tst.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-tst.h index 12fad7ce..c5602027 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-tst.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-tst.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-uxtb.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-uxtb.h index c0ec74e4..c1639607 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-uxtb.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-uxtb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-uxtb16.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-uxtb16.h index fc821a9b..6bd8ae02 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-uxtb16.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-uxtb16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-operand-rn-t32-uxth.h b/test/a32/traces/simulator-cond-rd-operand-rn-t32-uxth.h index 83231f93..7cbfda49 100644 --- a/test/a32/traces/simulator-cond-rd-operand-rn-t32-uxth.h +++ b/test/a32/traces/simulator-cond-rd-operand-rn-t32-uxth.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-a32-clz.h b/test/a32/traces/simulator-cond-rd-rn-a32-clz.h index e77eb7fe..dfdd3335 100644 --- a/test/a32/traces/simulator-cond-rd-rn-a32-clz.h +++ b/test/a32/traces/simulator-cond-rd-rn-a32-clz.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-a32-rbit.h b/test/a32/traces/simulator-cond-rd-rn-a32-rbit.h index 6b7ba0b9..54ce0a5d 100644 --- a/test/a32/traces/simulator-cond-rd-rn-a32-rbit.h +++ b/test/a32/traces/simulator-cond-rd-rn-a32-rbit.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-a32-rev.h b/test/a32/traces/simulator-cond-rd-rn-a32-rev.h index 7a362c10..ace283ce 100644 --- a/test/a32/traces/simulator-cond-rd-rn-a32-rev.h +++ b/test/a32/traces/simulator-cond-rd-rn-a32-rev.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-a32-rev16.h b/test/a32/traces/simulator-cond-rd-rn-a32-rev16.h index 6d716593..fcd3488a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-a32-rev16.h +++ b/test/a32/traces/simulator-cond-rd-rn-a32-rev16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-a32-revsh.h b/test/a32/traces/simulator-cond-rd-rn-a32-revsh.h index e54c8999..4ef51687 100644 --- a/test/a32/traces/simulator-cond-rd-rn-a32-revsh.h +++ b/test/a32/traces/simulator-cond-rd-rn-a32-revsh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-a32-rrx.h b/test/a32/traces/simulator-cond-rd-rn-a32-rrx.h index 1f6d23aa..4d831868 100644 --- a/test/a32/traces/simulator-cond-rd-rn-a32-rrx.h +++ b/test/a32/traces/simulator-cond-rd-rn-a32-rrx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-a32-rrxs.h b/test/a32/traces/simulator-cond-rd-rn-a32-rrxs.h index b938eb2c..3f7be61f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-a32-rrxs.h +++ b/test/a32/traces/simulator-cond-rd-rn-a32-rrxs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-adc.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-adc.h index 6b581e12..775599be 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-adc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-adcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-adcs.h index d2e29f95..da65a08a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-adcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-add.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-add.h index 947a04a0..293aa443 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-add.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-adds.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-adds.h index ee7e2d9a..f2389893 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-adds.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-and.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-and.h index d7a8ad7c..3358ce99 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-and.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-ands.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-ands.h index d206ded9..99417052 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-ands.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-bic.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-bic.h index 0b83999d..a6b28de5 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-bic.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-bics.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-bics.h index 50adbf71..0db9ac20 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-bics.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-eor.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-eor.h index 2fe6acd8..0c667c80 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-eor.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-eors.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-eors.h index 7c863eb7..3ed354a2 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-eors.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-orr.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-orr.h index e29c7246..eff44db7 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-orr.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-orrs.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-orrs.h index 7eeeecc0..69230355 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-orrs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rsb.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rsb.h index 1a5a82a7..007fbf07 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rsb.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rsbs.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rsbs.h index 5a75838e..c57a65f3 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rsbs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rsc.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rsc.h index 806c5c70..82fed333 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rsc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rsc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rscs.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rscs.h index 45eb16be..b37cf4f7 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rscs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-rscs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-sbc.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-sbc.h index 03b38ebc..b59bce08 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-sbc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-sbcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-sbcs.h index 48e4a4d6..8a2d84e8 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-sbcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-sub.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-sub.h index a1cc2bc6..9a74da4c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-sub.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-subs.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-subs.h index d9e8d83a..348d7c98 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-subs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-a32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-adc.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-adc.h index effa05a0..96c5ccde 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-adc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-adcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-adcs.h index 156e77b4..ac8ef3cd 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-adcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-add.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-add.h index 092a2139..d58ecac7 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-add.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-adds.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-adds.h index 9dc4fa10..8cab82f2 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-adds.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-and.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-and.h index dbc72eca..64db0c16 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-and.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-ands.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-ands.h index 8af5a00d..79571007 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-ands.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-bic.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-bic.h index 0e0e5796..d69b9180 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-bic.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-bics.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-bics.h index 5b8e54d2..6246301c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-bics.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-eor.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-eor.h index c02c6374..c6f1a0df 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-eor.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-eors.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-eors.h index 24dff9d5..26cf5501 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-eors.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orn.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orn.h index 6889a903..57f8be29 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orn.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orns.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orns.h index 7568d10f..85ac0331 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orns.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orr.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orr.h index 4ecce0d2..9a4f7859 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orr.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orrs.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orrs.h index f2eeb202..0e54057b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orrs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-rsb.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-rsb.h index b57fdb51..0d6f3f53 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-rsb.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-rsbs.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-rsbs.h index f972b3d0..7b423882 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-rsbs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-sbc.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-sbc.h index 4ed37291..4f67efbe 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-sbc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-sbcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-sbcs.h index 8d37e8c5..a538c196 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-sbcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-sub.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-sub.h index d07440a1..6c26ab1e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-sub.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-subs.h b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-subs.h index 85f2aa25..8d82f15d 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-subs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-const-t32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-add.h b/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-add.h index 82d2e63f..cf8b906a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-add.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-addw.h b/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-addw.h index 9618586e..8993dd88 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-addw.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-addw.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-sub.h b/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-sub.h index ec83d317..376e737b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-sub.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-subw.h b/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-subw.h index dc5cf309..3dabcc61 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-subw.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-imm12-t32-subw.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-adc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-adc.h index 9d7ad8e6..1c5871ae 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-adc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-adcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-adcs.h index 3d3c10f9..1f9deda6 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-adcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-add.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-add.h index da32c220..a8fb908b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-add.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-adds.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-adds.h index 35f68aea..cc4c35de 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-adds.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-and.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-and.h index 891cc791..a96a6b0a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-and.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-ands.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-ands.h index 881c4391..945c55e4 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-ands.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-asr.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-asr.h index 35810d33..24b3e25e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-asr.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-asr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-asrs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-asrs.h index e549f3ca..95aa4c63 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-asrs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-asrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-bic.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-bic.h index 2c2e2f16..e346c070 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-bic.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-bics.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-bics.h index 6bbad20a..57585cf8 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-bics.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-eor.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-eor.h index 8d599768..6043e4c7 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-eor.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-eors.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-eors.h index 295d2cfd..f9d9dea6 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-eors.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsl.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsl.h index b9f3b541..4fd2736a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsl.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsl.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsls.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsls.h index 77bed180..f1289aef 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsls.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsls.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsr.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsr.h index b16a300b..7b6badb1 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsr.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsrs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsrs.h index ad50c204..d46cab5b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsrs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-lsrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-orr.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-orr.h index b2e2dd15..1f9d1b1b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-orr.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-orrs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-orrs.h index a5fd47ad..1006b14d 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-orrs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-ror.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-ror.h index 51025967..971de840 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-ror.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-ror.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rors.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rors.h index ed9884dc..5eee2842 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rors.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsb.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsb.h index 400e2562..05f8c914 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsb.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsbs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsbs.h index eb25114c..3b3dbf0e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsbs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsc.h index 9a5971f9..70d54648 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rsc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rscs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rscs.h index 405f819b..f7062632 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rscs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-rscs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sbc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sbc.h index 988afe8a..7d274818 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sbc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sbcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sbcs.h index ea5f1cd0..4095c599 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sbcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sub.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sub.h index 153849d5..7a7fff03 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sub.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-subs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-subs.h index 91b5f4b6..8cc73101 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-subs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sxtab.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sxtab.h index 3e3363dd..18d9ad0e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sxtab.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sxtab16.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sxtab16.h index fec3ba41..6b355e1a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sxtab16.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sxtah.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sxtah.h index 3ae945d9..7e36d0c9 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sxtah.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-sxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-uxtab.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-uxtab.h index 4b50a713..12034185 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-uxtab.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-uxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-uxtab16.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-uxtab16.h index 66d79d27..f2e2535c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-uxtab16.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-uxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-uxtah.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-uxtah.h index 41e4aeff..0a54621c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-uxtah.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-a32-uxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-sxtab.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-sxtab.h index e3047224..b5016563 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-sxtab.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-sxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-sxtab16.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-sxtab16.h index 0701e287..830485cd 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-sxtab16.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-sxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-sxtah.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-sxtah.h index 096645a4..1ede536c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-sxtah.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-sxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-uxtab.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-uxtab.h index 701dc5d3..fc12b0ce 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-uxtab.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-uxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-uxtab16.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-uxtab16.h index 6b356da4..b8a9f7bd 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-uxtab16.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-uxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-uxtah.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-uxtah.h index a43c33a7..aad0e84f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-uxtah.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-a32-uxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-sxtab.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-sxtab.h index 94d0544c..c5e4c977 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-sxtab.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-sxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-sxtab16.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-sxtab16.h index 8a4ce6f2..e466f7da 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-sxtab16.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-sxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-sxtah.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-sxtah.h index c553ff66..b9044f7d 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-sxtah.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-sxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-uxtab.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-uxtab.h index 2a7b97ea..dccde9ba 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-uxtab.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-uxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-uxtab16.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-uxtab16.h index ec60af72..a3737f0f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-uxtab16.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-uxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-uxtah.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-uxtah.h index 2c6716bc..7aa082d5 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-uxtah.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-ror-amount-t32-uxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adc.h index 32899858..dae283ba 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adcs.h index b9925a3b..62cfad15 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-add.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-add.h index 3b7f053a..b39ffed8 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-add.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adds.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adds.h index ab35ac35..22315b78 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adds.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-and.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-and.h index e0905f06..1da64119 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-and.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-ands.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-ands.h index 9e798f4e..a488c0c1 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-ands.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bic.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bic.h index e3a155da..3a5e5d03 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bic.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bics.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bics.h index 5a486b72..5fa2eba4 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bics.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eor.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eor.h index 1f95de8b..d21348c6 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eor.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eors.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eors.h index fca30ea6..23608d87 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eors.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orr.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orr.h index ea16ebfd..aeddaccb 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orr.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orrs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orrs.h index 76c37d2d..591c765f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orrs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsb.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsb.h index 6673ad1c..ed87db41 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsb.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsbs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsbs.h index 38186dbd..0fd35603 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsbs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsc.h index 5e1154cc..1f8fe73d 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rsc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rscs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rscs.h index 95d407ea..e12a8f0d 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rscs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-rscs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbc.h index 2dce3479..e7fae129 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbcs.h index 85ff3692..3d3fcd8e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sub.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sub.h index 3cc1a9de..c94ba176 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sub.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-subs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-subs.h index e4fbec0e..496c3bf0 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-subs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adc.h index 9248ee74..7328c538 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adcs.h index cb5d6cf8..bc5085a9 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-add.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-add.h index 4e2f4811..384fb6d5 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-add.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adds.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adds.h index 361bf224..6fecaaa2 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adds.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-and.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-and.h index c98f8369..b30a4742 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-and.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-ands.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-ands.h index bd765b0d..87e506dd 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-ands.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bic.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bic.h index d93cd3c7..bf525431 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bic.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bics.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bics.h index ea5c43cc..638a33f2 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bics.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eor.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eor.h index f4b96c6a..54532964 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eor.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eors.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eors.h index d6bbbd1a..ef6e81c0 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eors.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orn.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orn.h index 0413a571..58a73281 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orn.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orns.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orns.h index feab30ff..003c8830 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orns.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orr.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orr.h index 9d9b11b2..4a846297 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orr.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orrs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orrs.h index 78c6379e..35d8afef 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orrs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsb.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsb.h index 216db14a..be57ffe7 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsb.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsbs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsbs.h index 563ddb20..24e997c2 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsbs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbc.h index ee693430..83d2b319 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbcs.h index 294d5827..874d6391 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sub.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sub.h index c2c5c174..5063cd31 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sub.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-subs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-subs.h index 3a89a26d..44758011 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-subs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adc.h index 220499eb..99b04b3d 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adcs.h index adf40d3c..5d9bc8fc 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-add.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-add.h index 71037332..ce7d53b5 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-add.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adds.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adds.h index f288da82..429589ad 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adds.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-and.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-and.h index f22c031e..192190e7 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-and.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-ands.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-ands.h index d0441f1a..95a9cacf 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-ands.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bic.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bic.h index 5ff951be..f9247793 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bic.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bics.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bics.h index b641d135..60ba3785 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bics.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eor.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eor.h index c051b9e0..052e8dc0 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eor.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eors.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eors.h index 44dcf617..9a8ff41f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eors.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orr.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orr.h index 5109a253..a148f2bd 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orr.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orrs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orrs.h index 404791d9..03ca8738 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orrs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsb.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsb.h index 814a4921..8057f1df 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsb.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsbs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsbs.h index 472b9c69..de327b7c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsbs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsc.h index eb45ebc5..661f44c8 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rsc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rscs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rscs.h index fa5e5b33..694cde33 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rscs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-rscs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbc.h index 0d13ecc8..4b117927 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbcs.h index 8f115260..b86abac3 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sub.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sub.h index ca5c83b4..89f3b3b1 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sub.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-subs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-subs.h index 57151f5a..61c4fbcf 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-subs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adc.h index 1017e958..e19686b6 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adcs.h index 3c006f5d..2ca357e2 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-add.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-add.h index c97fd9ca..0dad5a33 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-add.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adds.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adds.h index 3719eb30..3ce46f8f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adds.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-and.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-and.h index 2a0c1df0..f767a630 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-and.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-ands.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-ands.h index cd362aaf..fd54e3ca 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-ands.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bic.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bic.h index 3b9dd28a..496ef030 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bic.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bics.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bics.h index ccac5264..a1efcb72 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bics.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eor.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eor.h index 047885f9..77b8b48e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eor.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eors.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eors.h index a61c31b3..f4519362 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eors.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orn.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orn.h index dbf701bb..27ec4cbd 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orn.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orns.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orns.h index 0bbb2f14..b3bf4fa0 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orns.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orr.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orr.h index da02658a..5ab53cbe 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orr.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orrs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orrs.h index aa46e848..c4a2e79a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orrs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsb.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsb.h index 59478c85..cfc7ed69 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsb.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsbs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsbs.h index f41429c2..37cd20a7 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsbs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbc.h index e3409ae7..8b4bf60b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbcs.h index 0ba213e0..b256f606 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sub.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sub.h index 737dd787..b94d061c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sub.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-subs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-subs.h index fb2f48e9..16f17e63 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-subs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-adc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-adc.h index 19bc5b54..153893b1 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-adc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-adcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-adcs.h index eed34684..a8d0897a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-adcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-add.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-add.h index ab40291e..e7a981b8 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-add.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-adds.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-adds.h index e7f87219..2ddd637e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-adds.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-and.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-and.h index 53bda18d..6da7f72c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-and.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-ands.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-ands.h index 7dab661c..f7563b9b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-ands.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-bic.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-bic.h index c91853e8..fa2107f1 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-bic.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-bics.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-bics.h index e41cd9bc..60a350ae 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-bics.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-eor.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-eor.h index 8b7568c7..8bcc93e5 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-eor.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-eors.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-eors.h index 7fb99875..2837496f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-eors.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-orr.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-orr.h index 8541b0a4..dd0f947e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-orr.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-orrs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-orrs.h index adf4ebe1..4d1b87cc 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-orrs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rsb.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rsb.h index 8c75e0ce..65cd0a6e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rsb.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rsbs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rsbs.h index 2aec94ab..7be5d60a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rsbs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rsc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rsc.h index 041bbf1c..6fc0a9cb 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rsc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rsc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rscs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rscs.h index d8fc7ee3..615ef47b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rscs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-rscs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-sbc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-sbc.h index ed037549..eab02846 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-sbc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-sbcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-sbcs.h index b10e6b36..d00fa00d 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-sbcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-sub.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-sub.h index 83628bc0..12a9b8b6 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-sub.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-subs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-subs.h index 6fdd2441..62077f13 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-subs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-shift-rs-a32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-adc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-adc.h index 5843149f..a57d0117 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-adc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-adc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-adcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-adcs.h index 61fdd282..b354d064 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-adcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-adcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-add.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-add.h index 887955ae..5511bb42 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-add.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-adds.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-adds.h index 2958462c..fee9d518 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-adds.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-and.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-and.h index 244fc710..ab8de315 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-and.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-and.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-ands.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-ands.h index 499ae4ca..9e50e4c8 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-ands.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-ands.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-asr.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-asr.h index 965775a3..709ece29 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-asr.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-asr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-asrs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-asrs.h index d1abe402..d5305faf 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-asrs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-asrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-bic.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-bic.h index 1fc5fccd..84e85be3 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-bic.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-bic.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-bics.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-bics.h index 91c9f0e9..6cc642f7 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-bics.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-bics.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-eor.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-eor.h index 589d016b..b4bb441a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-eor.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-eor.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-eors.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-eors.h index 2450c9f7..ee4bd681 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-eors.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-eors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsl.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsl.h index 1beb281e..d895031f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsl.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsl.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsls.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsls.h index 0d9ded52..7ce64137 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsls.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsls.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsr.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsr.h index 11289bfc..e234b7e9 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsr.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsrs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsrs.h index b4cc440d..7d69702e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsrs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-lsrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orn.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orn.h index 6f515635..ea92b595 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orn.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orn.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orns.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orns.h index 7d4168f1..0cdab54e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orns.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orns.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orr.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orr.h index ce8ad029..b27160ca 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orr.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orrs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orrs.h index 10822e73..9b1d0045 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orrs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-orrs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-ror.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-ror.h index d1dcad7f..d97f06a0 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-ror.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-ror.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-rors.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-rors.h index 294ad4c8..b2eb9a39 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-rors.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-rors.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-rsb.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-rsb.h index 48cc6b10..5b89e19d 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-rsb.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-rsbs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-rsbs.h index 9dcad8cc..53b8ab70 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-rsbs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sbc.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sbc.h index 825307b9..fdbf6f65 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sbc.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sbc.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sbcs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sbcs.h index c4ca7662..1d414f29 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sbcs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sbcs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sub.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sub.h index 30a9c8df..1cad52a6 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sub.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-subs.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-subs.h index 48bf1967..1a16d4e9 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-subs.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sxtab.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sxtab.h index ef46f2e3..9a385d58 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sxtab.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sxtab16.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sxtab16.h index 102aa687..163d8f9b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sxtab16.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sxtah.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sxtah.h index 8602d275..fc98b063 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sxtah.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-sxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-uxtab.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-uxtab.h index 36094c73..eb635ce1 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-uxtab.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-uxtab.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-uxtab16.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-uxtab16.h index 702e4a74..ea63b351 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-uxtab16.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-uxtab16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-uxtah.h b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-uxtah.h index 1027e596..18790a1a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-uxtah.h +++ b/test/a32/traces/simulator-cond-rd-rn-operand-rm-t32-uxtah.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-sadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-sadd16.h index d049755a..01f3773b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-sadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-sadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-sadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-sadd8.h index 993cd221..11890055 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-sadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-sadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-sasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-sasx.h index 92b5a040..0f27047b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-sasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-sasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-ssax.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-ssax.h index b74754f6..ff807764 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-ssax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-ssax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-ssub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-ssub16.h index baf8d8f3..8c10c89e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-ssub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-ssub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-ssub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-ssub8.h index c0e6d11a..d2230c9d 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-ssub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-ssub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-uadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-uadd16.h index c08c868c..a644732f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-uadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-uadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-uadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-uadd8.h index c9070e3a..066a5e1b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-uadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-uadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-uasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-uasx.h index 10deeb9f..9893fbd4 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-uasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-uasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-usax.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-usax.h index e6c62549..7cf64e00 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-usax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-usax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-usub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-usub16.h index 04fb0699..63b43e6d 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-usub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-usub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-usub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-usub8.h index c3bb1fb5..31a931ab 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-usub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ge-usub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-mul.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-mul.h index e20ac132..663424d4 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-mul.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-mul.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-muls.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-muls.h index af9dbc61..29356c25 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-muls.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-muls.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qadd.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qadd.h index 90814523..8b363d12 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qadd.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qadd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qdadd.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qdadd.h index daa93b63..2e01bf92 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qdadd.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qdadd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qdsub.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qdsub.h index 0d56d5bb..efb61dd0 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qdsub.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qdsub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qsub.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qsub.h index 18e1fe74..757763b9 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qsub.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-q-qsub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qadd.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qadd.h index 89f6e078..ef2451d7 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qadd.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qadd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qadd16.h index 6a7baf39..480704d6 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qadd8.h index 1d677c52..87d403fc 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qasx.h index 05324055..5c3695c8 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qdadd.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qdadd.h index 58df5b2e..9e227a85 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qdadd.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qdadd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qdsub.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qdsub.h index eedda3fd..19abad07 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qdsub.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qdsub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsax.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsax.h index d3687a32..47f15cec 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsub.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsub.h index e122392d..59c2c665 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsub.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsub16.h index 675fee67..5124ba37 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsub8.h index 36e431a2..bd048dc8 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-qsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-sadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-sadd16.h index 4433c87d..6f4c9771 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-sadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-sadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-sadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-sadd8.h index 6c7bf47e..ec5b1702 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-sadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-sadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-sasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-sasx.h index 8c5aad10..9e00b6e0 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-sasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-sasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-sdiv.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-sdiv.h index 1abe506f..0a13ddde 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-sdiv.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-sdiv.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-sel-sel.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-sel-sel.h index 9e819041..df20a6ae 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-sel-sel.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-sel-sel.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-sel.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-sel.h index 90a43507..a9b82901 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-sel.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-sel.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-shadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-shadd16.h index b2895713..5fdb4b67 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-shadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-shadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-shadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-shadd8.h index 69df782e..9e6d5abe 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-shadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-shadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-shasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-shasx.h index 30c686a0..bb3384e7 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-shasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-shasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-shsax.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-shsax.h index 4c4ca18f..2cac732c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-shsax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-shsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-shsub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-shsub16.h index 377b563e..99a80fe7 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-shsub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-shsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-shsub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-shsub8.h index 99063c5d..253c2c68 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-shsub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-shsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smmul.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smmul.h index 70aa1a27..136b2df4 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smmul.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smmul.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smmulr.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smmulr.h index b9c02746..5f6f182c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smmulr.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smmulr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smuad.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smuad.h index 64e6713e..86445b1b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smuad.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smuad.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -9,7 +9,7 @@ // * Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution. -// * Neither the name of ARM Limited nor the names of its contributors may be +// * Neither the name of VIXL authors // used to endorse or promote products derived from this software without // specific prior written permission. // diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smuadx.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smuadx.h index 17d3fdcd..e18b748f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smuadx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smuadx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulbb.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulbb.h index 1527e33f..694bdb11 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulbb.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulbb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulbt.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulbt.h index 51be51a3..b2a59676 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulbt.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulbt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smultb.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smultb.h index 9580101a..84ee62ff 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smultb.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smultb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smultt.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smultt.h index 227e49cb..8fa1fd9e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smultt.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smultt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulwb.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulwb.h index 3e7aef6a..ba65199e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulwb.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulwb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulwt.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulwt.h index fbdb9107..d6b944c2 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulwt.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smulwt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smusd.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smusd.h index 98c5c706..75bbeb23 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smusd.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smusd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smusdx.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smusdx.h index 468269cc..32db2295 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-smusdx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-smusdx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ssax.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ssax.h index 901ed993..10000532 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ssax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ssax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ssub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ssub16.h index 2bbcd8c0..9475b860 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ssub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ssub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ssub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ssub8.h index a3f20b17..27172cec 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-ssub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-ssub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uadd16.h index cc27f036..add8a4c8 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uadd8.h index 9e033f1f..25a1b0ee 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uasx.h index 273a9965..a0d379c0 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-udiv.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-udiv.h index 7a8500c5..1b5588d1 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-udiv.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-udiv.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhadd16.h index 1d457b2f..3603b2b4 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhadd8.h index af5b7800..299a2486 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhasx.h index 6a138f9d..56c71d44 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhsax.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhsax.h index 31564173..b3c6cbf6 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhsax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhsub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhsub16.h index 09b6b370..b51101c5 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhsub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhsub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhsub8.h index b762e563..2679f3ff 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhsub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uhsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqadd16.h index 1182c2d3..f5cb8434 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqadd8.h index 4db7d934..9c4598f3 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqasx.h index 25a0837a..98dd525f 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsax.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsax.h index edc5ddbd..ba6718b3 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsub16.h index 2d65ca89..04d18a9b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsub8.h index 3d47555b..7d1b0095 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-uqsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-usad8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-usad8.h index 6eb76a06..98dd1054 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-usad8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-usad8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-usax.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-usax.h index 86fe3e44..89d67802 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-usax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-usax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-usub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-usub16.h index aed36fb9..770802c9 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-usub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-usub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-a32-usub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-a32-usub8.h index 5ee2c704..378b883e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-a32-usub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-a32-usub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sadd16.h index 16814ff0..2e594127 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sadd8.h index de10bdde..5c23587d 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sasx.h index e0f5276e..93d49ec2 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-sasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssax.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssax.h index 2150b866..8943d754 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssub16.h index 5bed137f..6d88a15b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssub8.h index a8f1d4e1..cc889843 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-ssub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uadd16.h index 840cff09..39b727cd 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uadd8.h index 10de0d31..560a5de9 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uasx.h index 9a5a8cc7..dd3c3e01 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-uasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usax.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usax.h index 84734ee8..dee45736 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usub16.h index 2d29ac54..b7222fa5 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usub8.h index 1543f617..4552f478 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ge-usub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-mul.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-mul.h index 0910cf5a..17d87897 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-mul.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-mul.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qadd.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qadd.h index bad678e8..c66c9aab 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qadd.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qadd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qdadd.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qdadd.h index f9230957..76d2be20 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qdadd.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qdadd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qdsub.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qdsub.h index 5bfd9248..58e9d0de 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qdsub.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qdsub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qsub.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qsub.h index 56152f6b..8186e0ce 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qsub.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-q-qsub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd.h index c4fcfe51..febd3330 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd16.h index e0132f6a..c1d8d691 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd8.h index 4f624398..86cff070 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qasx.h index 36b07846..60661423 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qdadd.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qdadd.h index dee8f418..c2c592f5 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qdadd.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qdadd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qdsub.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qdsub.h index 875cd26a..78f6b6cb 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qdsub.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qdsub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsax.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsax.h index f6284fcb..2f6da6e3 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsub.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsub.h index aa48a20d..141f3460 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsub.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsub16.h index eaebc7bd..5c7504db 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsub8.h index 4645c1f0..d88cf1d3 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-qsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-sadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-sadd16.h index 412b0eb5..a59ec5ff 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-sadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-sadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-sadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-sadd8.h index cd2b7d33..c4096571 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-sadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-sadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-sasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-sasx.h index ebbdf65d..ace3ccc5 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-sasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-sasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-sdiv.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-sdiv.h index a0e87064..b5f2c261 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-sdiv.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-sdiv.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-sel-sel.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-sel-sel.h index dd636eb8..50022793 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-sel-sel.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-sel-sel.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-sel.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-sel.h index dc8ffbed..c5d123a2 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-sel.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-sel.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-shadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-shadd16.h index 9e1d6a00..560cfb09 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-shadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-shadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-shadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-shadd8.h index 9862dde2..8a3a9274 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-shadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-shadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-shasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-shasx.h index a863368b..a2d0c14c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-shasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-shasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-shsax.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-shsax.h index 349a4118..e88cf802 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-shsax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-shsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-shsub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-shsub16.h index 72e31152..33af5ec4 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-shsub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-shsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-shsub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-shsub8.h index 1c2eaf47..71d6292e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-shsub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-shsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smmul.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smmul.h index 13981795..482d59f8 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smmul.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smmul.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smmulr.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smmulr.h index 70384afd..64376c70 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smmulr.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smmulr.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smuad.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smuad.h index 480abcc7..26b4d6f8 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smuad.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smuad.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smuadx.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smuadx.h index 9f32f560..24db2c03 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smuadx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smuadx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulbb.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulbb.h index b4508391..a3bc1d0c 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulbb.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulbb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulbt.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulbt.h index 1972a222..b958b659 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulbt.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulbt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smultb.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smultb.h index bc10c21c..811e5358 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smultb.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smultb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smultt.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smultt.h index 6402354c..3c51879e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smultt.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smultt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulwb.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulwb.h index 02e1bcef..115d93d9 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulwb.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulwb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulwt.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulwt.h index f89c6151..27a72cc9 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulwt.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smulwt.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smusd.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smusd.h index bda70642..1e028e54 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smusd.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smusd.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smusdx.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smusdx.h index 746d23b4..cadf0dbc 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-smusdx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-smusdx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ssax.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ssax.h index e3949541..03857b55 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ssax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ssax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ssub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ssub16.h index f6f36c40..38178fde 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ssub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ssub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ssub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ssub8.h index cc32cfb9..726c2104 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-ssub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-ssub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uadd16.h index c0022be7..11a3d105 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uadd8.h index 9282653a..c63b77c8 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uasx.h index 1f3f307c..a712edeb 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-udiv.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-udiv.h index e109b4dd..61d85aff 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-udiv.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-udiv.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhadd16.h index 7feffe47..de979215 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhadd8.h index 98e89939..f29907fe 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhasx.h index 7170dec4..afed7116 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsax.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsax.h index 630cf5ec..e0d693fc 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsub16.h index 1793f561..ba93b5fd 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsub8.h index 290e3ac8..dbd19da5 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uhsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqadd16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqadd16.h index 7ba1cdd3..4f0feb51 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqadd16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqadd16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqadd8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqadd8.h index 7559e962..62c162d5 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqadd8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqadd8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqasx.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqasx.h index 58c7a64b..c38ff0ab 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqasx.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqasx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsax.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsax.h index 8e479094..69e6736d 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsub16.h index e72b2eaa..faa60839 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsub8.h index 8b85fe66..3491c7bc 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-uqsub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-usad8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-usad8.h index c02290c8..fd6f20c7 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-usad8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-usad8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-usax.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-usax.h index 189440e9..4dc7ecf0 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-usax.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-usax.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-usub16.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-usub16.h index 5e3f18dc..b4fb418b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-usub16.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-usub16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-rm-t32-usub8.h b/test/a32/traces/simulator-cond-rd-rn-rm-t32-usub8.h index d180a405..2406c8ab 100644 --- a/test/a32/traces/simulator-cond-rd-rn-rm-t32-usub8.h +++ b/test/a32/traces/simulator-cond-rd-rn-rm-t32-usub8.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-t32-clz.h b/test/a32/traces/simulator-cond-rd-rn-t32-clz.h index 2b63f2dd..0b22536a 100644 --- a/test/a32/traces/simulator-cond-rd-rn-t32-clz.h +++ b/test/a32/traces/simulator-cond-rd-rn-t32-clz.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-t32-rbit.h b/test/a32/traces/simulator-cond-rd-rn-t32-rbit.h index 5fa87538..4d2d8163 100644 --- a/test/a32/traces/simulator-cond-rd-rn-t32-rbit.h +++ b/test/a32/traces/simulator-cond-rd-rn-t32-rbit.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-t32-rev.h b/test/a32/traces/simulator-cond-rd-rn-t32-rev.h index 1e76f8fa..9d13aee7 100644 --- a/test/a32/traces/simulator-cond-rd-rn-t32-rev.h +++ b/test/a32/traces/simulator-cond-rd-rn-t32-rev.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-t32-rev16.h b/test/a32/traces/simulator-cond-rd-rn-t32-rev16.h index bf1e411a..225e2ab7 100644 --- a/test/a32/traces/simulator-cond-rd-rn-t32-rev16.h +++ b/test/a32/traces/simulator-cond-rd-rn-t32-rev16.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-t32-revsh.h b/test/a32/traces/simulator-cond-rd-rn-t32-revsh.h index b0b5bc0c..79a6050e 100644 --- a/test/a32/traces/simulator-cond-rd-rn-t32-revsh.h +++ b/test/a32/traces/simulator-cond-rd-rn-t32-revsh.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-t32-rrx.h b/test/a32/traces/simulator-cond-rd-rn-t32-rrx.h index 29f61c1b..91ab272b 100644 --- a/test/a32/traces/simulator-cond-rd-rn-t32-rrx.h +++ b/test/a32/traces/simulator-cond-rd-rn-t32-rrx.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rd-rn-t32-rrxs.h b/test/a32/traces/simulator-cond-rd-rn-t32-rrxs.h index 94438b80..72a1bdf5 100644 --- a/test/a32/traces/simulator-cond-rd-rn-t32-rrxs.h +++ b/test/a32/traces/simulator-cond-rd-rn-t32-rrxs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rdlow-operand-imm8-t32-cmp.h b/test/a32/traces/simulator-cond-rdlow-operand-imm8-t32-cmp.h index 9a8607d0..dbbe4763 100644 --- a/test/a32/traces/simulator-cond-rdlow-operand-imm8-t32-cmp.h +++ b/test/a32/traces/simulator-cond-rdlow-operand-imm8-t32-cmp.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rdlow-operand-imm8-t32-mov.h b/test/a32/traces/simulator-cond-rdlow-operand-imm8-t32-mov.h index 660d3ece..ab16e2a9 100644 --- a/test/a32/traces/simulator-cond-rdlow-operand-imm8-t32-mov.h +++ b/test/a32/traces/simulator-cond-rdlow-operand-imm8-t32-mov.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rdlow-operand-imm8-t32-movs.h b/test/a32/traces/simulator-cond-rdlow-operand-imm8-t32-movs.h index b558f329..ae320b94 100644 --- a/test/a32/traces/simulator-cond-rdlow-operand-imm8-t32-movs.h +++ b/test/a32/traces/simulator-cond-rdlow-operand-imm8-t32-movs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-add.h b/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-add.h index 1d3e166e..1d759c60 100644 --- a/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-add.h +++ b/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-add.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-adds.h b/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-adds.h index dadc2b40..5bbc6f79 100644 --- a/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-adds.h +++ b/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-adds.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-rsb.h b/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-rsb.h index 35ae6b2f..7e22f824 100644 --- a/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-rsb.h +++ b/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-rsb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-rsbs.h b/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-rsbs.h index 76948c2b..583f3533 100644 --- a/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-rsbs.h +++ b/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-rsbs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-sub.h b/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-sub.h index 8addd9af..60b5c254 100644 --- a/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-sub.h +++ b/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-sub.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-subs.h b/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-subs.h index b1e32e3e..067aa5fc 100644 --- a/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-subs.h +++ b/test/a32/traces/simulator-cond-rdlow-rnlow-operand-immediate-t32-subs.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rdlow-rnlow-rmlow-t32-mul.h b/test/a32/traces/simulator-cond-rdlow-rnlow-rmlow-t32-mul.h index 645beb3b..fd2bc318 100644 --- a/test/a32/traces/simulator-cond-rdlow-rnlow-rmlow-t32-mul.h +++ b/test/a32/traces/simulator-cond-rdlow-rnlow-rmlow-t32-mul.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-cond-rdlow-rnlow-rmlow-t32-muls.h b/test/a32/traces/simulator-cond-rdlow-rnlow-rmlow-t32-muls.h index a9054d6e..e7cc07f2 100644 --- a/test/a32/traces/simulator-cond-rdlow-rnlow-rmlow-t32-muls.h +++ b/test/a32/traces/simulator-cond-rdlow-rnlow-rmlow-t32-muls.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-rd-rn-rm-a32-crc32b.h b/test/a32/traces/simulator-rd-rn-rm-a32-crc32b.h index 9e91f17a..21883378 100644 --- a/test/a32/traces/simulator-rd-rn-rm-a32-crc32b.h +++ b/test/a32/traces/simulator-rd-rn-rm-a32-crc32b.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-rd-rn-rm-a32-crc32cb.h b/test/a32/traces/simulator-rd-rn-rm-a32-crc32cb.h index c215a544..bcca24a1 100644 --- a/test/a32/traces/simulator-rd-rn-rm-a32-crc32cb.h +++ b/test/a32/traces/simulator-rd-rn-rm-a32-crc32cb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-rd-rn-rm-a32-crc32ch.h b/test/a32/traces/simulator-rd-rn-rm-a32-crc32ch.h index 2e5f520f..e97e9d8e 100644 --- a/test/a32/traces/simulator-rd-rn-rm-a32-crc32ch.h +++ b/test/a32/traces/simulator-rd-rn-rm-a32-crc32ch.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-rd-rn-rm-a32-crc32cw.h b/test/a32/traces/simulator-rd-rn-rm-a32-crc32cw.h index 565a99ff..da87ca09 100644 --- a/test/a32/traces/simulator-rd-rn-rm-a32-crc32cw.h +++ b/test/a32/traces/simulator-rd-rn-rm-a32-crc32cw.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-rd-rn-rm-a32-crc32h.h b/test/a32/traces/simulator-rd-rn-rm-a32-crc32h.h index aa1fbc3f..c0c74f56 100644 --- a/test/a32/traces/simulator-rd-rn-rm-a32-crc32h.h +++ b/test/a32/traces/simulator-rd-rn-rm-a32-crc32h.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-rd-rn-rm-a32-crc32w.h b/test/a32/traces/simulator-rd-rn-rm-a32-crc32w.h index 947e2887..6f8f5f8e 100644 --- a/test/a32/traces/simulator-rd-rn-rm-a32-crc32w.h +++ b/test/a32/traces/simulator-rd-rn-rm-a32-crc32w.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-rd-rn-rm-t32-crc32b.h b/test/a32/traces/simulator-rd-rn-rm-t32-crc32b.h index 7f9d69bf..c7e49e89 100644 --- a/test/a32/traces/simulator-rd-rn-rm-t32-crc32b.h +++ b/test/a32/traces/simulator-rd-rn-rm-t32-crc32b.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-rd-rn-rm-t32-crc32cb.h b/test/a32/traces/simulator-rd-rn-rm-t32-crc32cb.h index 53b5c0f5..a873f030 100644 --- a/test/a32/traces/simulator-rd-rn-rm-t32-crc32cb.h +++ b/test/a32/traces/simulator-rd-rn-rm-t32-crc32cb.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-rd-rn-rm-t32-crc32ch.h b/test/a32/traces/simulator-rd-rn-rm-t32-crc32ch.h index f7fe6e3b..69030185 100644 --- a/test/a32/traces/simulator-rd-rn-rm-t32-crc32ch.h +++ b/test/a32/traces/simulator-rd-rn-rm-t32-crc32ch.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-rd-rn-rm-t32-crc32cw.h b/test/a32/traces/simulator-rd-rn-rm-t32-crc32cw.h index b7482f1a..ddff36af 100644 --- a/test/a32/traces/simulator-rd-rn-rm-t32-crc32cw.h +++ b/test/a32/traces/simulator-rd-rn-rm-t32-crc32cw.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-rd-rn-rm-t32-crc32h.h b/test/a32/traces/simulator-rd-rn-rm-t32-crc32h.h index 2f7ebbaf..88311021 100644 --- a/test/a32/traces/simulator-rd-rn-rm-t32-crc32h.h +++ b/test/a32/traces/simulator-rd-rn-rm-t32-crc32h.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a32/traces/simulator-rd-rn-rm-t32-crc32w.h b/test/a32/traces/simulator-rd-rn-rm-t32-crc32w.h index ea64a1df..f8435531 100644 --- a/test/a32/traces/simulator-rd-rn-rm-t32-crc32w.h +++ b/test/a32/traces/simulator-rd-rn-rm-t32-crc32w.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/examples/test-examples.cc b/test/a64/examples/test-examples.cc index 69b06781..0be10314 100644 --- a/test/a64/examples/test-examples.cc +++ b/test/a64/examples/test-examples.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/test-assembler-a64.cc b/test/a64/test-assembler-a64.cc index 2925c6da..0ea99d9e 100644 --- a/test/a64/test-assembler-a64.cc +++ b/test/a64/test-assembler-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/test-disasm-a64.cc b/test/a64/test-disasm-a64.cc index 87905405..5eae18f7 100644 --- a/test/a64/test-disasm-a64.cc +++ b/test/a64/test-disasm-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/test-fuzz-a64.cc b/test/a64/test-fuzz-a64.cc index f876fa80..2008314c 100644 --- a/test/a64/test-fuzz-a64.cc +++ b/test/a64/test-fuzz-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/test-simulator-a64.cc b/test/a64/test-simulator-a64.cc index 71822887..2167a882 100644 --- a/test/a64/test-simulator-a64.cc +++ b/test/a64/test-simulator-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/test-simulator-inputs-a64.h b/test/a64/test-simulator-inputs-a64.h index fd169994..50d37a51 100644 --- a/test/a64/test-simulator-inputs-a64.h +++ b/test/a64/test-simulator-inputs-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/test-simulator-traces-a64.h b/test/a64/test-simulator-traces-a64.h index 61c472ba..f46ded95 100644 --- a/test/a64/test-simulator-traces-a64.h +++ b/test/a64/test-simulator-traces-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/test-trace-a64.cc b/test/a64/test-trace-a64.cc index 8932fcb1..a0599a72 100644 --- a/test/a64/test-trace-a64.cc +++ b/test/a64/test-trace-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2016, ARM Limited +// Copyright 2016, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/test-utils-a64.cc b/test/a64/test-utils-a64.cc index ae3220d9..28953023 100644 --- a/test/a64/test-utils-a64.cc +++ b/test/a64/test-utils-a64.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/test-utils-a64.h b/test/a64/test-utils-a64.h index 7151e34c..8c691c5d 100644 --- a/test/a64/test-utils-a64.h +++ b/test/a64/test-utils-a64.h @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-abs-16b-trace-a64.h b/test/a64/traces/sim-abs-16b-trace-a64.h index 13f1e53f..2fd2e998 100644 --- a/test/a64/traces/sim-abs-16b-trace-a64.h +++ b/test/a64/traces/sim-abs-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-abs-2d-trace-a64.h b/test/a64/traces/sim-abs-2d-trace-a64.h index d57992f1..566aec59 100644 --- a/test/a64/traces/sim-abs-2d-trace-a64.h +++ b/test/a64/traces/sim-abs-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-abs-2s-trace-a64.h b/test/a64/traces/sim-abs-2s-trace-a64.h index 7fdc95e0..f679cf76 100644 --- a/test/a64/traces/sim-abs-2s-trace-a64.h +++ b/test/a64/traces/sim-abs-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-abs-4h-trace-a64.h b/test/a64/traces/sim-abs-4h-trace-a64.h index d556a111..3a268662 100644 --- a/test/a64/traces/sim-abs-4h-trace-a64.h +++ b/test/a64/traces/sim-abs-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-abs-4s-trace-a64.h b/test/a64/traces/sim-abs-4s-trace-a64.h index 78048f83..84b237a1 100644 --- a/test/a64/traces/sim-abs-4s-trace-a64.h +++ b/test/a64/traces/sim-abs-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-abs-8b-trace-a64.h b/test/a64/traces/sim-abs-8b-trace-a64.h index 4418df68..16e56405 100644 --- a/test/a64/traces/sim-abs-8b-trace-a64.h +++ b/test/a64/traces/sim-abs-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-abs-8h-trace-a64.h b/test/a64/traces/sim-abs-8h-trace-a64.h index 25b35c4c..46719405 100644 --- a/test/a64/traces/sim-abs-8h-trace-a64.h +++ b/test/a64/traces/sim-abs-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-abs-d-trace-a64.h b/test/a64/traces/sim-abs-d-trace-a64.h index 28568922..fea73c10 100644 --- a/test/a64/traces/sim-abs-d-trace-a64.h +++ b/test/a64/traces/sim-abs-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-add-16b-trace-a64.h b/test/a64/traces/sim-add-16b-trace-a64.h index 6fb0fff7..03fadc77 100644 --- a/test/a64/traces/sim-add-16b-trace-a64.h +++ b/test/a64/traces/sim-add-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-add-2d-trace-a64.h b/test/a64/traces/sim-add-2d-trace-a64.h index f1e9cdcb..1d7962e0 100644 --- a/test/a64/traces/sim-add-2d-trace-a64.h +++ b/test/a64/traces/sim-add-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-add-2s-trace-a64.h b/test/a64/traces/sim-add-2s-trace-a64.h index d69a4686..64234fb7 100644 --- a/test/a64/traces/sim-add-2s-trace-a64.h +++ b/test/a64/traces/sim-add-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-add-4h-trace-a64.h b/test/a64/traces/sim-add-4h-trace-a64.h index ce69d680..76c2d299 100644 --- a/test/a64/traces/sim-add-4h-trace-a64.h +++ b/test/a64/traces/sim-add-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-add-4s-trace-a64.h b/test/a64/traces/sim-add-4s-trace-a64.h index 693aa412..702243f6 100644 --- a/test/a64/traces/sim-add-4s-trace-a64.h +++ b/test/a64/traces/sim-add-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-add-8b-trace-a64.h b/test/a64/traces/sim-add-8b-trace-a64.h index b356c886..2bf45ea6 100644 --- a/test/a64/traces/sim-add-8b-trace-a64.h +++ b/test/a64/traces/sim-add-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-add-8h-trace-a64.h b/test/a64/traces/sim-add-8h-trace-a64.h index 423008be..21e2d063 100644 --- a/test/a64/traces/sim-add-8h-trace-a64.h +++ b/test/a64/traces/sim-add-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-add-d-trace-a64.h b/test/a64/traces/sim-add-d-trace-a64.h index 33dd37cf..5374424c 100644 --- a/test/a64/traces/sim-add-d-trace-a64.h +++ b/test/a64/traces/sim-add-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addhn-2s-trace-a64.h b/test/a64/traces/sim-addhn-2s-trace-a64.h index 670a8abd..a265a020 100644 --- a/test/a64/traces/sim-addhn-2s-trace-a64.h +++ b/test/a64/traces/sim-addhn-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addhn-4h-trace-a64.h b/test/a64/traces/sim-addhn-4h-trace-a64.h index 11ca8eb6..8960d159 100644 --- a/test/a64/traces/sim-addhn-4h-trace-a64.h +++ b/test/a64/traces/sim-addhn-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addhn-8b-trace-a64.h b/test/a64/traces/sim-addhn-8b-trace-a64.h index b151c2cf..da6dadbd 100644 --- a/test/a64/traces/sim-addhn-8b-trace-a64.h +++ b/test/a64/traces/sim-addhn-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addhn2-16b-trace-a64.h b/test/a64/traces/sim-addhn2-16b-trace-a64.h index bd48236a..336c99ec 100644 --- a/test/a64/traces/sim-addhn2-16b-trace-a64.h +++ b/test/a64/traces/sim-addhn2-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addhn2-4s-trace-a64.h b/test/a64/traces/sim-addhn2-4s-trace-a64.h index 255dfb91..03f17b6f 100644 --- a/test/a64/traces/sim-addhn2-4s-trace-a64.h +++ b/test/a64/traces/sim-addhn2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addhn2-8h-trace-a64.h b/test/a64/traces/sim-addhn2-8h-trace-a64.h index 4888d3b2..baabc1b9 100644 --- a/test/a64/traces/sim-addhn2-8h-trace-a64.h +++ b/test/a64/traces/sim-addhn2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addp-16b-trace-a64.h b/test/a64/traces/sim-addp-16b-trace-a64.h index d0301507..5667c632 100644 --- a/test/a64/traces/sim-addp-16b-trace-a64.h +++ b/test/a64/traces/sim-addp-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addp-2d-trace-a64.h b/test/a64/traces/sim-addp-2d-trace-a64.h index 663117d3..d829ffa3 100644 --- a/test/a64/traces/sim-addp-2d-trace-a64.h +++ b/test/a64/traces/sim-addp-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addp-2s-trace-a64.h b/test/a64/traces/sim-addp-2s-trace-a64.h index 16dc9974..ca1a5bbc 100644 --- a/test/a64/traces/sim-addp-2s-trace-a64.h +++ b/test/a64/traces/sim-addp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addp-4h-trace-a64.h b/test/a64/traces/sim-addp-4h-trace-a64.h index 7ed86535..ce86cbe0 100644 --- a/test/a64/traces/sim-addp-4h-trace-a64.h +++ b/test/a64/traces/sim-addp-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addp-4s-trace-a64.h b/test/a64/traces/sim-addp-4s-trace-a64.h index e4b1a21f..1d964f8e 100644 --- a/test/a64/traces/sim-addp-4s-trace-a64.h +++ b/test/a64/traces/sim-addp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addp-8b-trace-a64.h b/test/a64/traces/sim-addp-8b-trace-a64.h index 23f7d2d8..61003088 100644 --- a/test/a64/traces/sim-addp-8b-trace-a64.h +++ b/test/a64/traces/sim-addp-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addp-8h-trace-a64.h b/test/a64/traces/sim-addp-8h-trace-a64.h index cd26d6ab..2542f5cb 100644 --- a/test/a64/traces/sim-addp-8h-trace-a64.h +++ b/test/a64/traces/sim-addp-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addp-scalar-trace-a64.h b/test/a64/traces/sim-addp-scalar-trace-a64.h index 1c467247..1e603ebf 100644 --- a/test/a64/traces/sim-addp-scalar-trace-a64.h +++ b/test/a64/traces/sim-addp-scalar-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addv-b-16b-trace-a64.h b/test/a64/traces/sim-addv-b-16b-trace-a64.h index ccba92b9..04a5bd54 100644 --- a/test/a64/traces/sim-addv-b-16b-trace-a64.h +++ b/test/a64/traces/sim-addv-b-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addv-b-8b-trace-a64.h b/test/a64/traces/sim-addv-b-8b-trace-a64.h index 7de4d049..66364006 100644 --- a/test/a64/traces/sim-addv-b-8b-trace-a64.h +++ b/test/a64/traces/sim-addv-b-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addv-h-4h-trace-a64.h b/test/a64/traces/sim-addv-h-4h-trace-a64.h index da917200..a7f3ecba 100644 --- a/test/a64/traces/sim-addv-h-4h-trace-a64.h +++ b/test/a64/traces/sim-addv-h-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addv-h-8h-trace-a64.h b/test/a64/traces/sim-addv-h-8h-trace-a64.h index 212aeb7e..0f197447 100644 --- a/test/a64/traces/sim-addv-h-8h-trace-a64.h +++ b/test/a64/traces/sim-addv-h-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-addv-s-4s-trace-a64.h b/test/a64/traces/sim-addv-s-4s-trace-a64.h index 7ec6d9e5..48821a77 100644 --- a/test/a64/traces/sim-addv-s-4s-trace-a64.h +++ b/test/a64/traces/sim-addv-s-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-and--16b-trace-a64.h b/test/a64/traces/sim-and--16b-trace-a64.h index 7ba8f98b..39fedd29 100644 --- a/test/a64/traces/sim-and--16b-trace-a64.h +++ b/test/a64/traces/sim-and--16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-and--8b-trace-a64.h b/test/a64/traces/sim-and--8b-trace-a64.h index 33a6fd41..4618ea64 100644 --- a/test/a64/traces/sim-and--8b-trace-a64.h +++ b/test/a64/traces/sim-and--8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-bic-16b-trace-a64.h b/test/a64/traces/sim-bic-16b-trace-a64.h index 9812bdce..e0c7707e 100644 --- a/test/a64/traces/sim-bic-16b-trace-a64.h +++ b/test/a64/traces/sim-bic-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-bic-8b-trace-a64.h b/test/a64/traces/sim-bic-8b-trace-a64.h index fbb4532d..47296e17 100644 --- a/test/a64/traces/sim-bic-8b-trace-a64.h +++ b/test/a64/traces/sim-bic-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-bif-16b-trace-a64.h b/test/a64/traces/sim-bif-16b-trace-a64.h index a7f29339..126b0b97 100644 --- a/test/a64/traces/sim-bif-16b-trace-a64.h +++ b/test/a64/traces/sim-bif-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-bif-8b-trace-a64.h b/test/a64/traces/sim-bif-8b-trace-a64.h index fca8039f..6968abbe 100644 --- a/test/a64/traces/sim-bif-8b-trace-a64.h +++ b/test/a64/traces/sim-bif-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-bit-16b-trace-a64.h b/test/a64/traces/sim-bit-16b-trace-a64.h index 866a3033..48ed73f3 100644 --- a/test/a64/traces/sim-bit-16b-trace-a64.h +++ b/test/a64/traces/sim-bit-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-bit-8b-trace-a64.h b/test/a64/traces/sim-bit-8b-trace-a64.h index ed0786f6..613c29e5 100644 --- a/test/a64/traces/sim-bit-8b-trace-a64.h +++ b/test/a64/traces/sim-bit-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-bsl-16b-trace-a64.h b/test/a64/traces/sim-bsl-16b-trace-a64.h index e84b4192..ee3d21c2 100644 --- a/test/a64/traces/sim-bsl-16b-trace-a64.h +++ b/test/a64/traces/sim-bsl-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-bsl-8b-trace-a64.h b/test/a64/traces/sim-bsl-8b-trace-a64.h index 5a480512..dc629553 100644 --- a/test/a64/traces/sim-bsl-8b-trace-a64.h +++ b/test/a64/traces/sim-bsl-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cls-16b-trace-a64.h b/test/a64/traces/sim-cls-16b-trace-a64.h index cab71ef1..3299d574 100644 --- a/test/a64/traces/sim-cls-16b-trace-a64.h +++ b/test/a64/traces/sim-cls-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cls-2s-trace-a64.h b/test/a64/traces/sim-cls-2s-trace-a64.h index f4d211eb..24420147 100644 --- a/test/a64/traces/sim-cls-2s-trace-a64.h +++ b/test/a64/traces/sim-cls-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cls-4h-trace-a64.h b/test/a64/traces/sim-cls-4h-trace-a64.h index f5f24bbf..843c07ad 100644 --- a/test/a64/traces/sim-cls-4h-trace-a64.h +++ b/test/a64/traces/sim-cls-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cls-4s-trace-a64.h b/test/a64/traces/sim-cls-4s-trace-a64.h index 28b9b053..c2a5c2ae 100644 --- a/test/a64/traces/sim-cls-4s-trace-a64.h +++ b/test/a64/traces/sim-cls-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cls-8b-trace-a64.h b/test/a64/traces/sim-cls-8b-trace-a64.h index 0ff967e9..edec1c07 100644 --- a/test/a64/traces/sim-cls-8b-trace-a64.h +++ b/test/a64/traces/sim-cls-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cls-8h-trace-a64.h b/test/a64/traces/sim-cls-8h-trace-a64.h index c7166f76..ee6cb5d6 100644 --- a/test/a64/traces/sim-cls-8h-trace-a64.h +++ b/test/a64/traces/sim-cls-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-clz-16b-trace-a64.h b/test/a64/traces/sim-clz-16b-trace-a64.h index 340a7006..5da1c4ec 100644 --- a/test/a64/traces/sim-clz-16b-trace-a64.h +++ b/test/a64/traces/sim-clz-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-clz-2s-trace-a64.h b/test/a64/traces/sim-clz-2s-trace-a64.h index 0b0e579b..14ac3620 100644 --- a/test/a64/traces/sim-clz-2s-trace-a64.h +++ b/test/a64/traces/sim-clz-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-clz-4h-trace-a64.h b/test/a64/traces/sim-clz-4h-trace-a64.h index 1dcd8241..a822a5cf 100644 --- a/test/a64/traces/sim-clz-4h-trace-a64.h +++ b/test/a64/traces/sim-clz-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-clz-4s-trace-a64.h b/test/a64/traces/sim-clz-4s-trace-a64.h index 657578f6..b093216c 100644 --- a/test/a64/traces/sim-clz-4s-trace-a64.h +++ b/test/a64/traces/sim-clz-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-clz-8b-trace-a64.h b/test/a64/traces/sim-clz-8b-trace-a64.h index 49a588ce..17345343 100644 --- a/test/a64/traces/sim-clz-8b-trace-a64.h +++ b/test/a64/traces/sim-clz-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-clz-8h-trace-a64.h b/test/a64/traces/sim-clz-8h-trace-a64.h index 0e0a3bc5..1c6b0692 100644 --- a/test/a64/traces/sim-clz-8h-trace-a64.h +++ b/test/a64/traces/sim-clz-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-16b-2opimm-trace-a64.h b/test/a64/traces/sim-cmeq-16b-2opimm-trace-a64.h index 2afe556d..ad845e3c 100644 --- a/test/a64/traces/sim-cmeq-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmeq-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-16b-trace-a64.h b/test/a64/traces/sim-cmeq-16b-trace-a64.h index dd467d2c..8d6f248b 100644 --- a/test/a64/traces/sim-cmeq-16b-trace-a64.h +++ b/test/a64/traces/sim-cmeq-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-2d-2opimm-trace-a64.h b/test/a64/traces/sim-cmeq-2d-2opimm-trace-a64.h index 32d1e223..55dd38b5 100644 --- a/test/a64/traces/sim-cmeq-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmeq-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-2d-trace-a64.h b/test/a64/traces/sim-cmeq-2d-trace-a64.h index 55473774..821d7c84 100644 --- a/test/a64/traces/sim-cmeq-2d-trace-a64.h +++ b/test/a64/traces/sim-cmeq-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-2s-2opimm-trace-a64.h b/test/a64/traces/sim-cmeq-2s-2opimm-trace-a64.h index a8028c07..61a9c321 100644 --- a/test/a64/traces/sim-cmeq-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmeq-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-2s-trace-a64.h b/test/a64/traces/sim-cmeq-2s-trace-a64.h index 592da285..b2723aa7 100644 --- a/test/a64/traces/sim-cmeq-2s-trace-a64.h +++ b/test/a64/traces/sim-cmeq-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-4h-2opimm-trace-a64.h b/test/a64/traces/sim-cmeq-4h-2opimm-trace-a64.h index cc7916a3..0f84924e 100644 --- a/test/a64/traces/sim-cmeq-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmeq-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-4h-trace-a64.h b/test/a64/traces/sim-cmeq-4h-trace-a64.h index af6deac7..1f2c4e23 100644 --- a/test/a64/traces/sim-cmeq-4h-trace-a64.h +++ b/test/a64/traces/sim-cmeq-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-4s-2opimm-trace-a64.h b/test/a64/traces/sim-cmeq-4s-2opimm-trace-a64.h index f887459b..153651a9 100644 --- a/test/a64/traces/sim-cmeq-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmeq-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-4s-trace-a64.h b/test/a64/traces/sim-cmeq-4s-trace-a64.h index d51f2246..85b231c4 100644 --- a/test/a64/traces/sim-cmeq-4s-trace-a64.h +++ b/test/a64/traces/sim-cmeq-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-8b-2opimm-trace-a64.h b/test/a64/traces/sim-cmeq-8b-2opimm-trace-a64.h index d5951a6c..44830280 100644 --- a/test/a64/traces/sim-cmeq-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmeq-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-8b-trace-a64.h b/test/a64/traces/sim-cmeq-8b-trace-a64.h index 5538541d..bc45fb72 100644 --- a/test/a64/traces/sim-cmeq-8b-trace-a64.h +++ b/test/a64/traces/sim-cmeq-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-8h-2opimm-trace-a64.h b/test/a64/traces/sim-cmeq-8h-2opimm-trace-a64.h index 19842c7a..cf055740 100644 --- a/test/a64/traces/sim-cmeq-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmeq-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-8h-trace-a64.h b/test/a64/traces/sim-cmeq-8h-trace-a64.h index e4fa36f9..fe623e1b 100644 --- a/test/a64/traces/sim-cmeq-8h-trace-a64.h +++ b/test/a64/traces/sim-cmeq-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-d-2opimm-trace-a64.h b/test/a64/traces/sim-cmeq-d-2opimm-trace-a64.h index 9fafe5ac..e97fab44 100644 --- a/test/a64/traces/sim-cmeq-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmeq-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmeq-d-trace-a64.h b/test/a64/traces/sim-cmeq-d-trace-a64.h index 6eeb629d..f53b4c39 100644 --- a/test/a64/traces/sim-cmeq-d-trace-a64.h +++ b/test/a64/traces/sim-cmeq-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-16b-2opimm-trace-a64.h b/test/a64/traces/sim-cmge-16b-2opimm-trace-a64.h index 9b43f03c..3d216fd0 100644 --- a/test/a64/traces/sim-cmge-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmge-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-16b-trace-a64.h b/test/a64/traces/sim-cmge-16b-trace-a64.h index 6840b01e..63ebb3c9 100644 --- a/test/a64/traces/sim-cmge-16b-trace-a64.h +++ b/test/a64/traces/sim-cmge-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-2d-2opimm-trace-a64.h b/test/a64/traces/sim-cmge-2d-2opimm-trace-a64.h index d6696da4..892fce51 100644 --- a/test/a64/traces/sim-cmge-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmge-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-2d-trace-a64.h b/test/a64/traces/sim-cmge-2d-trace-a64.h index abe8bd59..55f145d4 100644 --- a/test/a64/traces/sim-cmge-2d-trace-a64.h +++ b/test/a64/traces/sim-cmge-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-2s-2opimm-trace-a64.h b/test/a64/traces/sim-cmge-2s-2opimm-trace-a64.h index f83256a5..0371660d 100644 --- a/test/a64/traces/sim-cmge-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmge-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-2s-trace-a64.h b/test/a64/traces/sim-cmge-2s-trace-a64.h index af7a90c4..71f377c9 100644 --- a/test/a64/traces/sim-cmge-2s-trace-a64.h +++ b/test/a64/traces/sim-cmge-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-4h-2opimm-trace-a64.h b/test/a64/traces/sim-cmge-4h-2opimm-trace-a64.h index 00b0d103..7b4c5e37 100644 --- a/test/a64/traces/sim-cmge-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmge-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-4h-trace-a64.h b/test/a64/traces/sim-cmge-4h-trace-a64.h index bc905208..fa1bf52d 100644 --- a/test/a64/traces/sim-cmge-4h-trace-a64.h +++ b/test/a64/traces/sim-cmge-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-4s-2opimm-trace-a64.h b/test/a64/traces/sim-cmge-4s-2opimm-trace-a64.h index 2386f228..0e82125d 100644 --- a/test/a64/traces/sim-cmge-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmge-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-4s-trace-a64.h b/test/a64/traces/sim-cmge-4s-trace-a64.h index 58b99cc2..fe0020ab 100644 --- a/test/a64/traces/sim-cmge-4s-trace-a64.h +++ b/test/a64/traces/sim-cmge-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-8b-2opimm-trace-a64.h b/test/a64/traces/sim-cmge-8b-2opimm-trace-a64.h index a20157ae..881cb6cd 100644 --- a/test/a64/traces/sim-cmge-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmge-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-8b-trace-a64.h b/test/a64/traces/sim-cmge-8b-trace-a64.h index b80c26af..65167f77 100644 --- a/test/a64/traces/sim-cmge-8b-trace-a64.h +++ b/test/a64/traces/sim-cmge-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-8h-2opimm-trace-a64.h b/test/a64/traces/sim-cmge-8h-2opimm-trace-a64.h index 68361b92..8c3b8b24 100644 --- a/test/a64/traces/sim-cmge-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmge-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-8h-trace-a64.h b/test/a64/traces/sim-cmge-8h-trace-a64.h index 05f82a03..1ee4e164 100644 --- a/test/a64/traces/sim-cmge-8h-trace-a64.h +++ b/test/a64/traces/sim-cmge-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-d-2opimm-trace-a64.h b/test/a64/traces/sim-cmge-d-2opimm-trace-a64.h index b6b421df..7f666fe4 100644 --- a/test/a64/traces/sim-cmge-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmge-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmge-d-trace-a64.h b/test/a64/traces/sim-cmge-d-trace-a64.h index 86eb6801..8be6c2f0 100644 --- a/test/a64/traces/sim-cmge-d-trace-a64.h +++ b/test/a64/traces/sim-cmge-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-16b-2opimm-trace-a64.h b/test/a64/traces/sim-cmgt-16b-2opimm-trace-a64.h index 3ab1107f..f51c0561 100644 --- a/test/a64/traces/sim-cmgt-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmgt-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-16b-trace-a64.h b/test/a64/traces/sim-cmgt-16b-trace-a64.h index c9bcf78d..143c3ffb 100644 --- a/test/a64/traces/sim-cmgt-16b-trace-a64.h +++ b/test/a64/traces/sim-cmgt-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-2d-2opimm-trace-a64.h b/test/a64/traces/sim-cmgt-2d-2opimm-trace-a64.h index d4030397..59e035af 100644 --- a/test/a64/traces/sim-cmgt-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmgt-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-2d-trace-a64.h b/test/a64/traces/sim-cmgt-2d-trace-a64.h index a33924b5..babe4a5f 100644 --- a/test/a64/traces/sim-cmgt-2d-trace-a64.h +++ b/test/a64/traces/sim-cmgt-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-2s-2opimm-trace-a64.h b/test/a64/traces/sim-cmgt-2s-2opimm-trace-a64.h index 79219a8a..58d5509a 100644 --- a/test/a64/traces/sim-cmgt-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmgt-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-2s-trace-a64.h b/test/a64/traces/sim-cmgt-2s-trace-a64.h index d6cab32c..3fa27731 100644 --- a/test/a64/traces/sim-cmgt-2s-trace-a64.h +++ b/test/a64/traces/sim-cmgt-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-4h-2opimm-trace-a64.h b/test/a64/traces/sim-cmgt-4h-2opimm-trace-a64.h index 6ca0e1e7..de1df0ff 100644 --- a/test/a64/traces/sim-cmgt-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmgt-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-4h-trace-a64.h b/test/a64/traces/sim-cmgt-4h-trace-a64.h index aaa0c9a3..9e6a858d 100644 --- a/test/a64/traces/sim-cmgt-4h-trace-a64.h +++ b/test/a64/traces/sim-cmgt-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-4s-2opimm-trace-a64.h b/test/a64/traces/sim-cmgt-4s-2opimm-trace-a64.h index e0022a12..a03688bf 100644 --- a/test/a64/traces/sim-cmgt-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmgt-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-4s-trace-a64.h b/test/a64/traces/sim-cmgt-4s-trace-a64.h index 377e66a4..6462671d 100644 --- a/test/a64/traces/sim-cmgt-4s-trace-a64.h +++ b/test/a64/traces/sim-cmgt-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-8b-2opimm-trace-a64.h b/test/a64/traces/sim-cmgt-8b-2opimm-trace-a64.h index ea994d8d..4221114d 100644 --- a/test/a64/traces/sim-cmgt-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmgt-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-8b-trace-a64.h b/test/a64/traces/sim-cmgt-8b-trace-a64.h index 437e4fe3..aef4abcb 100644 --- a/test/a64/traces/sim-cmgt-8b-trace-a64.h +++ b/test/a64/traces/sim-cmgt-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-8h-2opimm-trace-a64.h b/test/a64/traces/sim-cmgt-8h-2opimm-trace-a64.h index d2685f3e..98f886e6 100644 --- a/test/a64/traces/sim-cmgt-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmgt-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-8h-trace-a64.h b/test/a64/traces/sim-cmgt-8h-trace-a64.h index d705b7c1..0e9183e5 100644 --- a/test/a64/traces/sim-cmgt-8h-trace-a64.h +++ b/test/a64/traces/sim-cmgt-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-d-2opimm-trace-a64.h b/test/a64/traces/sim-cmgt-d-2opimm-trace-a64.h index 6e4a23d4..128244c3 100644 --- a/test/a64/traces/sim-cmgt-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmgt-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmgt-d-trace-a64.h b/test/a64/traces/sim-cmgt-d-trace-a64.h index f40b2b35..614d3ae1 100644 --- a/test/a64/traces/sim-cmgt-d-trace-a64.h +++ b/test/a64/traces/sim-cmgt-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhi-16b-trace-a64.h b/test/a64/traces/sim-cmhi-16b-trace-a64.h index 0342f5c9..90806333 100644 --- a/test/a64/traces/sim-cmhi-16b-trace-a64.h +++ b/test/a64/traces/sim-cmhi-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhi-2d-trace-a64.h b/test/a64/traces/sim-cmhi-2d-trace-a64.h index f5aa4d7e..1f1d2dc7 100644 --- a/test/a64/traces/sim-cmhi-2d-trace-a64.h +++ b/test/a64/traces/sim-cmhi-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhi-2s-trace-a64.h b/test/a64/traces/sim-cmhi-2s-trace-a64.h index 3918bef6..802d2803 100644 --- a/test/a64/traces/sim-cmhi-2s-trace-a64.h +++ b/test/a64/traces/sim-cmhi-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhi-4h-trace-a64.h b/test/a64/traces/sim-cmhi-4h-trace-a64.h index 8acbba44..3b5b2b6a 100644 --- a/test/a64/traces/sim-cmhi-4h-trace-a64.h +++ b/test/a64/traces/sim-cmhi-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhi-4s-trace-a64.h b/test/a64/traces/sim-cmhi-4s-trace-a64.h index 2578aa39..b689e076 100644 --- a/test/a64/traces/sim-cmhi-4s-trace-a64.h +++ b/test/a64/traces/sim-cmhi-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhi-8b-trace-a64.h b/test/a64/traces/sim-cmhi-8b-trace-a64.h index 3579653a..31d823cb 100644 --- a/test/a64/traces/sim-cmhi-8b-trace-a64.h +++ b/test/a64/traces/sim-cmhi-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhi-8h-trace-a64.h b/test/a64/traces/sim-cmhi-8h-trace-a64.h index b24144ef..8af9f2b7 100644 --- a/test/a64/traces/sim-cmhi-8h-trace-a64.h +++ b/test/a64/traces/sim-cmhi-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhi-d-trace-a64.h b/test/a64/traces/sim-cmhi-d-trace-a64.h index 5de94266..3827ef20 100644 --- a/test/a64/traces/sim-cmhi-d-trace-a64.h +++ b/test/a64/traces/sim-cmhi-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhs-16b-trace-a64.h b/test/a64/traces/sim-cmhs-16b-trace-a64.h index a12a424f..fe092028 100644 --- a/test/a64/traces/sim-cmhs-16b-trace-a64.h +++ b/test/a64/traces/sim-cmhs-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhs-2d-trace-a64.h b/test/a64/traces/sim-cmhs-2d-trace-a64.h index 34e47007..b76f4641 100644 --- a/test/a64/traces/sim-cmhs-2d-trace-a64.h +++ b/test/a64/traces/sim-cmhs-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhs-2s-trace-a64.h b/test/a64/traces/sim-cmhs-2s-trace-a64.h index 5d4e8c85..0ef0d9a9 100644 --- a/test/a64/traces/sim-cmhs-2s-trace-a64.h +++ b/test/a64/traces/sim-cmhs-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhs-4h-trace-a64.h b/test/a64/traces/sim-cmhs-4h-trace-a64.h index 21f6580d..9008c8ac 100644 --- a/test/a64/traces/sim-cmhs-4h-trace-a64.h +++ b/test/a64/traces/sim-cmhs-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhs-4s-trace-a64.h b/test/a64/traces/sim-cmhs-4s-trace-a64.h index 2ce88cc1..1d67f34c 100644 --- a/test/a64/traces/sim-cmhs-4s-trace-a64.h +++ b/test/a64/traces/sim-cmhs-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhs-8b-trace-a64.h b/test/a64/traces/sim-cmhs-8b-trace-a64.h index da767a30..5bcad52c 100644 --- a/test/a64/traces/sim-cmhs-8b-trace-a64.h +++ b/test/a64/traces/sim-cmhs-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhs-8h-trace-a64.h b/test/a64/traces/sim-cmhs-8h-trace-a64.h index a7e677f2..5fc28cfa 100644 --- a/test/a64/traces/sim-cmhs-8h-trace-a64.h +++ b/test/a64/traces/sim-cmhs-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmhs-d-trace-a64.h b/test/a64/traces/sim-cmhs-d-trace-a64.h index 245ff72a..f6fc7730 100644 --- a/test/a64/traces/sim-cmhs-d-trace-a64.h +++ b/test/a64/traces/sim-cmhs-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmle-16b-2opimm-trace-a64.h b/test/a64/traces/sim-cmle-16b-2opimm-trace-a64.h index 26f15a3a..1b744d11 100644 --- a/test/a64/traces/sim-cmle-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmle-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmle-2d-2opimm-trace-a64.h b/test/a64/traces/sim-cmle-2d-2opimm-trace-a64.h index 5a57c89b..bf4a7909 100644 --- a/test/a64/traces/sim-cmle-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmle-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmle-2s-2opimm-trace-a64.h b/test/a64/traces/sim-cmle-2s-2opimm-trace-a64.h index 095fedca..729c6895 100644 --- a/test/a64/traces/sim-cmle-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmle-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmle-4h-2opimm-trace-a64.h b/test/a64/traces/sim-cmle-4h-2opimm-trace-a64.h index ac8820b9..50dca7a1 100644 --- a/test/a64/traces/sim-cmle-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmle-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmle-4s-2opimm-trace-a64.h b/test/a64/traces/sim-cmle-4s-2opimm-trace-a64.h index db76e753..eb330e80 100644 --- a/test/a64/traces/sim-cmle-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmle-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmle-8b-2opimm-trace-a64.h b/test/a64/traces/sim-cmle-8b-2opimm-trace-a64.h index c0d21ee8..d89cb956 100644 --- a/test/a64/traces/sim-cmle-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmle-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmle-8h-2opimm-trace-a64.h b/test/a64/traces/sim-cmle-8h-2opimm-trace-a64.h index 129b685c..7d97d908 100644 --- a/test/a64/traces/sim-cmle-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmle-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmle-d-2opimm-trace-a64.h b/test/a64/traces/sim-cmle-d-2opimm-trace-a64.h index 63b5a29f..24a51ee6 100644 --- a/test/a64/traces/sim-cmle-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmle-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmlt-16b-2opimm-trace-a64.h b/test/a64/traces/sim-cmlt-16b-2opimm-trace-a64.h index d62e7a7a..558dda61 100644 --- a/test/a64/traces/sim-cmlt-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmlt-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmlt-2d-2opimm-trace-a64.h b/test/a64/traces/sim-cmlt-2d-2opimm-trace-a64.h index c8de2742..1268718d 100644 --- a/test/a64/traces/sim-cmlt-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmlt-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmlt-2s-2opimm-trace-a64.h b/test/a64/traces/sim-cmlt-2s-2opimm-trace-a64.h index 1d414597..7a91b971 100644 --- a/test/a64/traces/sim-cmlt-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmlt-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmlt-4h-2opimm-trace-a64.h b/test/a64/traces/sim-cmlt-4h-2opimm-trace-a64.h index d1081e7c..ff4632c7 100644 --- a/test/a64/traces/sim-cmlt-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmlt-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmlt-4s-2opimm-trace-a64.h b/test/a64/traces/sim-cmlt-4s-2opimm-trace-a64.h index ebac8f2c..24ebcc4a 100644 --- a/test/a64/traces/sim-cmlt-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmlt-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmlt-8b-2opimm-trace-a64.h b/test/a64/traces/sim-cmlt-8b-2opimm-trace-a64.h index e18c4051..f2d240e7 100644 --- a/test/a64/traces/sim-cmlt-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmlt-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmlt-8h-2opimm-trace-a64.h b/test/a64/traces/sim-cmlt-8h-2opimm-trace-a64.h index ff4bde2e..c981e23d 100644 --- a/test/a64/traces/sim-cmlt-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmlt-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmlt-d-2opimm-trace-a64.h b/test/a64/traces/sim-cmlt-d-2opimm-trace-a64.h index ad2f4ebb..7c2e0a5e 100644 --- a/test/a64/traces/sim-cmlt-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-cmlt-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmtst-16b-trace-a64.h b/test/a64/traces/sim-cmtst-16b-trace-a64.h index a13bf9b8..f4837f0d 100644 --- a/test/a64/traces/sim-cmtst-16b-trace-a64.h +++ b/test/a64/traces/sim-cmtst-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmtst-2d-trace-a64.h b/test/a64/traces/sim-cmtst-2d-trace-a64.h index 6b6783cd..6b5721c5 100644 --- a/test/a64/traces/sim-cmtst-2d-trace-a64.h +++ b/test/a64/traces/sim-cmtst-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmtst-2s-trace-a64.h b/test/a64/traces/sim-cmtst-2s-trace-a64.h index 253c4939..df1e827b 100644 --- a/test/a64/traces/sim-cmtst-2s-trace-a64.h +++ b/test/a64/traces/sim-cmtst-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmtst-4h-trace-a64.h b/test/a64/traces/sim-cmtst-4h-trace-a64.h index 8a83c478..3dc8c56c 100644 --- a/test/a64/traces/sim-cmtst-4h-trace-a64.h +++ b/test/a64/traces/sim-cmtst-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmtst-4s-trace-a64.h b/test/a64/traces/sim-cmtst-4s-trace-a64.h index 522a7da6..9dbf872d 100644 --- a/test/a64/traces/sim-cmtst-4s-trace-a64.h +++ b/test/a64/traces/sim-cmtst-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmtst-8b-trace-a64.h b/test/a64/traces/sim-cmtst-8b-trace-a64.h index 8fe2cb2f..3ef46410 100644 --- a/test/a64/traces/sim-cmtst-8b-trace-a64.h +++ b/test/a64/traces/sim-cmtst-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmtst-8h-trace-a64.h b/test/a64/traces/sim-cmtst-8h-trace-a64.h index 4595aee3..255c8494 100644 --- a/test/a64/traces/sim-cmtst-8h-trace-a64.h +++ b/test/a64/traces/sim-cmtst-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cmtst-d-trace-a64.h b/test/a64/traces/sim-cmtst-d-trace-a64.h index 957c0635..0bf83b64 100644 --- a/test/a64/traces/sim-cmtst-d-trace-a64.h +++ b/test/a64/traces/sim-cmtst-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cnt-16b-trace-a64.h b/test/a64/traces/sim-cnt-16b-trace-a64.h index 089fe3fc..ce167c14 100644 --- a/test/a64/traces/sim-cnt-16b-trace-a64.h +++ b/test/a64/traces/sim-cnt-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-cnt-8b-trace-a64.h b/test/a64/traces/sim-cnt-8b-trace-a64.h index b3bc232f..6c4772c7 100644 --- a/test/a64/traces/sim-cnt-8b-trace-a64.h +++ b/test/a64/traces/sim-cnt-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-dup-16b-2opimm-trace-a64.h b/test/a64/traces/sim-dup-16b-2opimm-trace-a64.h index d856778d..dfd54c95 100644 --- a/test/a64/traces/sim-dup-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-dup-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-dup-2d-2opimm-trace-a64.h b/test/a64/traces/sim-dup-2d-2opimm-trace-a64.h index 30dbcb33..442a6d0c 100644 --- a/test/a64/traces/sim-dup-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-dup-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-dup-2s-2opimm-trace-a64.h b/test/a64/traces/sim-dup-2s-2opimm-trace-a64.h index c35d637a..8b42a490 100644 --- a/test/a64/traces/sim-dup-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-dup-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-dup-4h-2opimm-trace-a64.h b/test/a64/traces/sim-dup-4h-2opimm-trace-a64.h index ba46a4d3..87b8668e 100644 --- a/test/a64/traces/sim-dup-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-dup-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-dup-4s-2opimm-trace-a64.h b/test/a64/traces/sim-dup-4s-2opimm-trace-a64.h index 15b92e16..9cbf3a19 100644 --- a/test/a64/traces/sim-dup-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-dup-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-dup-8b-2opimm-trace-a64.h b/test/a64/traces/sim-dup-8b-2opimm-trace-a64.h index 90929281..5cbbbee6 100644 --- a/test/a64/traces/sim-dup-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-dup-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-dup-8h-2opimm-trace-a64.h b/test/a64/traces/sim-dup-8h-2opimm-trace-a64.h index db1c5287..40994b0a 100644 --- a/test/a64/traces/sim-dup-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-dup-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-dup-b-2opimm-trace-a64.h b/test/a64/traces/sim-dup-b-2opimm-trace-a64.h index 1ae57ded..53d9a724 100644 --- a/test/a64/traces/sim-dup-b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-dup-b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-dup-d-2opimm-trace-a64.h b/test/a64/traces/sim-dup-d-2opimm-trace-a64.h index cda60dd5..0fbcff19 100644 --- a/test/a64/traces/sim-dup-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-dup-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-dup-h-2opimm-trace-a64.h b/test/a64/traces/sim-dup-h-2opimm-trace-a64.h index 6ad42bef..74b2c2ad 100644 --- a/test/a64/traces/sim-dup-h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-dup-h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-dup-s-2opimm-trace-a64.h b/test/a64/traces/sim-dup-s-2opimm-trace-a64.h index 6ecd3d67..e4a7ed0d 100644 --- a/test/a64/traces/sim-dup-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-dup-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-eor-16b-trace-a64.h b/test/a64/traces/sim-eor-16b-trace-a64.h index b77b72b3..3860b5d4 100644 --- a/test/a64/traces/sim-eor-16b-trace-a64.h +++ b/test/a64/traces/sim-eor-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-eor-8b-trace-a64.h b/test/a64/traces/sim-eor-8b-trace-a64.h index c642ea06..3a9ab24c 100644 --- a/test/a64/traces/sim-eor-8b-trace-a64.h +++ b/test/a64/traces/sim-eor-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fabd-2d-trace-a64.h b/test/a64/traces/sim-fabd-2d-trace-a64.h index 39d2d1a4..c02115a6 100644 --- a/test/a64/traces/sim-fabd-2d-trace-a64.h +++ b/test/a64/traces/sim-fabd-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fabd-2s-trace-a64.h b/test/a64/traces/sim-fabd-2s-trace-a64.h index 65796575..d719facc 100644 --- a/test/a64/traces/sim-fabd-2s-trace-a64.h +++ b/test/a64/traces/sim-fabd-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fabd-4s-trace-a64.h b/test/a64/traces/sim-fabd-4s-trace-a64.h index ce98ac35..d202a349 100644 --- a/test/a64/traces/sim-fabd-4s-trace-a64.h +++ b/test/a64/traces/sim-fabd-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fabd-d-trace-a64.h b/test/a64/traces/sim-fabd-d-trace-a64.h index 27f89fca..d757a30d 100644 --- a/test/a64/traces/sim-fabd-d-trace-a64.h +++ b/test/a64/traces/sim-fabd-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fabd-s-trace-a64.h b/test/a64/traces/sim-fabd-s-trace-a64.h index a9c41504..624ed4df 100644 --- a/test/a64/traces/sim-fabd-s-trace-a64.h +++ b/test/a64/traces/sim-fabd-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fabs-2d-trace-a64.h b/test/a64/traces/sim-fabs-2d-trace-a64.h index e7aab745..55b96e38 100644 --- a/test/a64/traces/sim-fabs-2d-trace-a64.h +++ b/test/a64/traces/sim-fabs-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fabs-2s-trace-a64.h b/test/a64/traces/sim-fabs-2s-trace-a64.h index d3b4f57e..1f2e2213 100644 --- a/test/a64/traces/sim-fabs-2s-trace-a64.h +++ b/test/a64/traces/sim-fabs-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fabs-4s-trace-a64.h b/test/a64/traces/sim-fabs-4s-trace-a64.h index ae0d7a4b..63497a5c 100644 --- a/test/a64/traces/sim-fabs-4s-trace-a64.h +++ b/test/a64/traces/sim-fabs-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fabs-d-trace-a64.h b/test/a64/traces/sim-fabs-d-trace-a64.h index 016fc553..c1a63078 100644 --- a/test/a64/traces/sim-fabs-d-trace-a64.h +++ b/test/a64/traces/sim-fabs-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fabs-s-trace-a64.h b/test/a64/traces/sim-fabs-s-trace-a64.h index 8f64c01c..443c2718 100644 --- a/test/a64/traces/sim-fabs-s-trace-a64.h +++ b/test/a64/traces/sim-fabs-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-facge-2d-trace-a64.h b/test/a64/traces/sim-facge-2d-trace-a64.h index e1127ea1..095e948a 100644 --- a/test/a64/traces/sim-facge-2d-trace-a64.h +++ b/test/a64/traces/sim-facge-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-facge-2s-trace-a64.h b/test/a64/traces/sim-facge-2s-trace-a64.h index 4b085dff..049bdd72 100644 --- a/test/a64/traces/sim-facge-2s-trace-a64.h +++ b/test/a64/traces/sim-facge-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-facge-4s-trace-a64.h b/test/a64/traces/sim-facge-4s-trace-a64.h index 016657eb..d733ed94 100644 --- a/test/a64/traces/sim-facge-4s-trace-a64.h +++ b/test/a64/traces/sim-facge-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-facge-d-trace-a64.h b/test/a64/traces/sim-facge-d-trace-a64.h index 8e65126d..37804546 100644 --- a/test/a64/traces/sim-facge-d-trace-a64.h +++ b/test/a64/traces/sim-facge-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-facge-s-trace-a64.h b/test/a64/traces/sim-facge-s-trace-a64.h index ba5f7c00..69df68f8 100644 --- a/test/a64/traces/sim-facge-s-trace-a64.h +++ b/test/a64/traces/sim-facge-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-facgt-2d-trace-a64.h b/test/a64/traces/sim-facgt-2d-trace-a64.h index f582533c..3b7f57b7 100644 --- a/test/a64/traces/sim-facgt-2d-trace-a64.h +++ b/test/a64/traces/sim-facgt-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-facgt-2s-trace-a64.h b/test/a64/traces/sim-facgt-2s-trace-a64.h index a64fa9bf..ede45d5b 100644 --- a/test/a64/traces/sim-facgt-2s-trace-a64.h +++ b/test/a64/traces/sim-facgt-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-facgt-4s-trace-a64.h b/test/a64/traces/sim-facgt-4s-trace-a64.h index bad9ca4d..9234a963 100644 --- a/test/a64/traces/sim-facgt-4s-trace-a64.h +++ b/test/a64/traces/sim-facgt-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-facgt-d-trace-a64.h b/test/a64/traces/sim-facgt-d-trace-a64.h index 873fda03..1dbe7a80 100644 --- a/test/a64/traces/sim-facgt-d-trace-a64.h +++ b/test/a64/traces/sim-facgt-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-facgt-s-trace-a64.h b/test/a64/traces/sim-facgt-s-trace-a64.h index 65866e33..98ceb0c2 100644 --- a/test/a64/traces/sim-facgt-s-trace-a64.h +++ b/test/a64/traces/sim-facgt-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fadd-2d-trace-a64.h b/test/a64/traces/sim-fadd-2d-trace-a64.h index a87172bf..ee3ccee4 100644 --- a/test/a64/traces/sim-fadd-2d-trace-a64.h +++ b/test/a64/traces/sim-fadd-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fadd-2s-trace-a64.h b/test/a64/traces/sim-fadd-2s-trace-a64.h index 11d2a878..cfca985b 100644 --- a/test/a64/traces/sim-fadd-2s-trace-a64.h +++ b/test/a64/traces/sim-fadd-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fadd-4s-trace-a64.h b/test/a64/traces/sim-fadd-4s-trace-a64.h index ce6e479b..d9b4f875 100644 --- a/test/a64/traces/sim-fadd-4s-trace-a64.h +++ b/test/a64/traces/sim-fadd-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fadd-d-trace-a64.h b/test/a64/traces/sim-fadd-d-trace-a64.h index 0855c492..1cee6e20 100644 --- a/test/a64/traces/sim-fadd-d-trace-a64.h +++ b/test/a64/traces/sim-fadd-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fadd-s-trace-a64.h b/test/a64/traces/sim-fadd-s-trace-a64.h index 55acac4e..d14b44e2 100644 --- a/test/a64/traces/sim-fadd-s-trace-a64.h +++ b/test/a64/traces/sim-fadd-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-faddp-2d-trace-a64.h b/test/a64/traces/sim-faddp-2d-trace-a64.h index acd6146d..037ec27a 100644 --- a/test/a64/traces/sim-faddp-2d-trace-a64.h +++ b/test/a64/traces/sim-faddp-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-faddp-2s-trace-a64.h b/test/a64/traces/sim-faddp-2s-trace-a64.h index d8a1a6a2..5ffeb0a7 100644 --- a/test/a64/traces/sim-faddp-2s-trace-a64.h +++ b/test/a64/traces/sim-faddp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-faddp-4s-trace-a64.h b/test/a64/traces/sim-faddp-4s-trace-a64.h index 413dabc5..8d6a53e7 100644 --- a/test/a64/traces/sim-faddp-4s-trace-a64.h +++ b/test/a64/traces/sim-faddp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-faddp-d-trace-a64.h b/test/a64/traces/sim-faddp-d-trace-a64.h index 0c25dfcd..b6697c01 100644 --- a/test/a64/traces/sim-faddp-d-trace-a64.h +++ b/test/a64/traces/sim-faddp-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-faddp-s-trace-a64.h b/test/a64/traces/sim-faddp-s-trace-a64.h index b5bf9eb2..4cf857d9 100644 --- a/test/a64/traces/sim-faddp-s-trace-a64.h +++ b/test/a64/traces/sim-faddp-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmeq-2d-2opimm-trace-a64.h b/test/a64/traces/sim-fcmeq-2d-2opimm-trace-a64.h index 4b8fd4d0..43d10903 100644 --- a/test/a64/traces/sim-fcmeq-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmeq-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmeq-2d-trace-a64.h b/test/a64/traces/sim-fcmeq-2d-trace-a64.h index 88bf49a5..a7463c84 100644 --- a/test/a64/traces/sim-fcmeq-2d-trace-a64.h +++ b/test/a64/traces/sim-fcmeq-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmeq-2s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmeq-2s-2opimm-trace-a64.h index 9a420c2e..e77b9b29 100644 --- a/test/a64/traces/sim-fcmeq-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmeq-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmeq-2s-trace-a64.h b/test/a64/traces/sim-fcmeq-2s-trace-a64.h index dce7dc22..58e74a82 100644 --- a/test/a64/traces/sim-fcmeq-2s-trace-a64.h +++ b/test/a64/traces/sim-fcmeq-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmeq-4s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmeq-4s-2opimm-trace-a64.h index b7a4207c..f9b038ef 100644 --- a/test/a64/traces/sim-fcmeq-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmeq-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmeq-4s-trace-a64.h b/test/a64/traces/sim-fcmeq-4s-trace-a64.h index 72a5d69e..a8487c0a 100644 --- a/test/a64/traces/sim-fcmeq-4s-trace-a64.h +++ b/test/a64/traces/sim-fcmeq-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmeq-d-2opimm-trace-a64.h b/test/a64/traces/sim-fcmeq-d-2opimm-trace-a64.h index 242d9a0c..0327fdbd 100644 --- a/test/a64/traces/sim-fcmeq-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmeq-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmeq-d-trace-a64.h b/test/a64/traces/sim-fcmeq-d-trace-a64.h index 8053f9c6..36071924 100644 --- a/test/a64/traces/sim-fcmeq-d-trace-a64.h +++ b/test/a64/traces/sim-fcmeq-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmeq-s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmeq-s-2opimm-trace-a64.h index 86bde33f..6cccf00f 100644 --- a/test/a64/traces/sim-fcmeq-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmeq-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmeq-s-trace-a64.h b/test/a64/traces/sim-fcmeq-s-trace-a64.h index b1a90071..8fbb7be9 100644 --- a/test/a64/traces/sim-fcmeq-s-trace-a64.h +++ b/test/a64/traces/sim-fcmeq-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmge-2d-2opimm-trace-a64.h b/test/a64/traces/sim-fcmge-2d-2opimm-trace-a64.h index 11ef8cdb..624a7287 100644 --- a/test/a64/traces/sim-fcmge-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmge-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmge-2d-trace-a64.h b/test/a64/traces/sim-fcmge-2d-trace-a64.h index cc6ea5a5..ff21c2f7 100644 --- a/test/a64/traces/sim-fcmge-2d-trace-a64.h +++ b/test/a64/traces/sim-fcmge-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmge-2s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmge-2s-2opimm-trace-a64.h index 899e981e..19a568b0 100644 --- a/test/a64/traces/sim-fcmge-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmge-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmge-2s-trace-a64.h b/test/a64/traces/sim-fcmge-2s-trace-a64.h index afd7ebd4..37d0e76d 100644 --- a/test/a64/traces/sim-fcmge-2s-trace-a64.h +++ b/test/a64/traces/sim-fcmge-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmge-4s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmge-4s-2opimm-trace-a64.h index aae0e2a0..633537d6 100644 --- a/test/a64/traces/sim-fcmge-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmge-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmge-4s-trace-a64.h b/test/a64/traces/sim-fcmge-4s-trace-a64.h index bfbf70d8..d42899b5 100644 --- a/test/a64/traces/sim-fcmge-4s-trace-a64.h +++ b/test/a64/traces/sim-fcmge-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmge-d-2opimm-trace-a64.h b/test/a64/traces/sim-fcmge-d-2opimm-trace-a64.h index 4d4b69c1..fd04688a 100644 --- a/test/a64/traces/sim-fcmge-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmge-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmge-d-trace-a64.h b/test/a64/traces/sim-fcmge-d-trace-a64.h index 841f5463..39779cbc 100644 --- a/test/a64/traces/sim-fcmge-d-trace-a64.h +++ b/test/a64/traces/sim-fcmge-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmge-s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmge-s-2opimm-trace-a64.h index 7a0d59a0..5dd34a1d 100644 --- a/test/a64/traces/sim-fcmge-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmge-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmge-s-trace-a64.h b/test/a64/traces/sim-fcmge-s-trace-a64.h index 15601d2b..a2d92aa6 100644 --- a/test/a64/traces/sim-fcmge-s-trace-a64.h +++ b/test/a64/traces/sim-fcmge-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmgt-2d-2opimm-trace-a64.h b/test/a64/traces/sim-fcmgt-2d-2opimm-trace-a64.h index 9514d2d9..f832c976 100644 --- a/test/a64/traces/sim-fcmgt-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmgt-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmgt-2d-trace-a64.h b/test/a64/traces/sim-fcmgt-2d-trace-a64.h index 891f1013..5fd31607 100644 --- a/test/a64/traces/sim-fcmgt-2d-trace-a64.h +++ b/test/a64/traces/sim-fcmgt-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmgt-2s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmgt-2s-2opimm-trace-a64.h index 5109c260..8a823b22 100644 --- a/test/a64/traces/sim-fcmgt-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmgt-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmgt-2s-trace-a64.h b/test/a64/traces/sim-fcmgt-2s-trace-a64.h index 8e2a51ef..a520ca25 100644 --- a/test/a64/traces/sim-fcmgt-2s-trace-a64.h +++ b/test/a64/traces/sim-fcmgt-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmgt-4s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmgt-4s-2opimm-trace-a64.h index 862fc8bb..e8ddfd75 100644 --- a/test/a64/traces/sim-fcmgt-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmgt-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmgt-4s-trace-a64.h b/test/a64/traces/sim-fcmgt-4s-trace-a64.h index 6a4ab1ab..c4ee21fb 100644 --- a/test/a64/traces/sim-fcmgt-4s-trace-a64.h +++ b/test/a64/traces/sim-fcmgt-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmgt-d-2opimm-trace-a64.h b/test/a64/traces/sim-fcmgt-d-2opimm-trace-a64.h index f53d2ee7..5b0f82cf 100644 --- a/test/a64/traces/sim-fcmgt-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmgt-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmgt-d-trace-a64.h b/test/a64/traces/sim-fcmgt-d-trace-a64.h index cb19f801..f8edf1bf 100644 --- a/test/a64/traces/sim-fcmgt-d-trace-a64.h +++ b/test/a64/traces/sim-fcmgt-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmgt-s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmgt-s-2opimm-trace-a64.h index 265bce1a..933d9f45 100644 --- a/test/a64/traces/sim-fcmgt-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmgt-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmgt-s-trace-a64.h b/test/a64/traces/sim-fcmgt-s-trace-a64.h index 6b181cc2..5689325a 100644 --- a/test/a64/traces/sim-fcmgt-s-trace-a64.h +++ b/test/a64/traces/sim-fcmgt-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmle-2d-2opimm-trace-a64.h b/test/a64/traces/sim-fcmle-2d-2opimm-trace-a64.h index 48f881bc..aba854c0 100644 --- a/test/a64/traces/sim-fcmle-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmle-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmle-2s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmle-2s-2opimm-trace-a64.h index 6223d933..56c794b5 100644 --- a/test/a64/traces/sim-fcmle-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmle-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmle-4s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmle-4s-2opimm-trace-a64.h index f4309503..9f86bdf1 100644 --- a/test/a64/traces/sim-fcmle-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmle-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmle-d-2opimm-trace-a64.h b/test/a64/traces/sim-fcmle-d-2opimm-trace-a64.h index 6c329867..072910c5 100644 --- a/test/a64/traces/sim-fcmle-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmle-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmle-s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmle-s-2opimm-trace-a64.h index b6138de7..6bc29bc9 100644 --- a/test/a64/traces/sim-fcmle-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmle-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmlt-2d-2opimm-trace-a64.h b/test/a64/traces/sim-fcmlt-2d-2opimm-trace-a64.h index 08fcf106..fcf8377e 100644 --- a/test/a64/traces/sim-fcmlt-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmlt-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmlt-2s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmlt-2s-2opimm-trace-a64.h index 676d0d54..4ee40e2f 100644 --- a/test/a64/traces/sim-fcmlt-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmlt-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmlt-4s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmlt-4s-2opimm-trace-a64.h index 7f84795e..0e379ea9 100644 --- a/test/a64/traces/sim-fcmlt-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmlt-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmlt-d-2opimm-trace-a64.h b/test/a64/traces/sim-fcmlt-d-2opimm-trace-a64.h index 2aff2c9c..f7ebac8a 100644 --- a/test/a64/traces/sim-fcmlt-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmlt-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmlt-s-2opimm-trace-a64.h b/test/a64/traces/sim-fcmlt-s-2opimm-trace-a64.h index d3efa376..3941dc45 100644 --- a/test/a64/traces/sim-fcmlt-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcmlt-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmp-d-trace-a64.h b/test/a64/traces/sim-fcmp-d-trace-a64.h index 0f3d7793..7bb81194 100644 --- a/test/a64/traces/sim-fcmp-d-trace-a64.h +++ b/test/a64/traces/sim-fcmp-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmp-dz-trace-a64.h b/test/a64/traces/sim-fcmp-dz-trace-a64.h index d8c2bc51..f7863df6 100644 --- a/test/a64/traces/sim-fcmp-dz-trace-a64.h +++ b/test/a64/traces/sim-fcmp-dz-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmp-s-trace-a64.h b/test/a64/traces/sim-fcmp-s-trace-a64.h index 2ea6a265..92ba3a94 100644 --- a/test/a64/traces/sim-fcmp-s-trace-a64.h +++ b/test/a64/traces/sim-fcmp-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcmp-sz-trace-a64.h b/test/a64/traces/sim-fcmp-sz-trace-a64.h index 6604adee..53eca281 100644 --- a/test/a64/traces/sim-fcmp-sz-trace-a64.h +++ b/test/a64/traces/sim-fcmp-sz-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvt-ds-trace-a64.h b/test/a64/traces/sim-fcvt-ds-trace-a64.h index 3fa2e6a4..6faf8a2b 100644 --- a/test/a64/traces/sim-fcvt-ds-trace-a64.h +++ b/test/a64/traces/sim-fcvt-ds-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvt-sd-trace-a64.h b/test/a64/traces/sim-fcvt-sd-trace-a64.h index 49b37d1b..2f93fcac 100644 --- a/test/a64/traces/sim-fcvt-sd-trace-a64.h +++ b/test/a64/traces/sim-fcvt-sd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtas-2d-trace-a64.h b/test/a64/traces/sim-fcvtas-2d-trace-a64.h index cbe9dc0b..1eae034a 100644 --- a/test/a64/traces/sim-fcvtas-2d-trace-a64.h +++ b/test/a64/traces/sim-fcvtas-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtas-2s-trace-a64.h b/test/a64/traces/sim-fcvtas-2s-trace-a64.h index dec068d2..759564f3 100644 --- a/test/a64/traces/sim-fcvtas-2s-trace-a64.h +++ b/test/a64/traces/sim-fcvtas-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtas-4s-trace-a64.h b/test/a64/traces/sim-fcvtas-4s-trace-a64.h index 6b99aab4..0fd75900 100644 --- a/test/a64/traces/sim-fcvtas-4s-trace-a64.h +++ b/test/a64/traces/sim-fcvtas-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtas-d-trace-a64.h b/test/a64/traces/sim-fcvtas-d-trace-a64.h index 1ffe153b..c7a73952 100644 --- a/test/a64/traces/sim-fcvtas-d-trace-a64.h +++ b/test/a64/traces/sim-fcvtas-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtas-s-trace-a64.h b/test/a64/traces/sim-fcvtas-s-trace-a64.h index 7c5dd93c..a3015e16 100644 --- a/test/a64/traces/sim-fcvtas-s-trace-a64.h +++ b/test/a64/traces/sim-fcvtas-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtas-wd-trace-a64.h b/test/a64/traces/sim-fcvtas-wd-trace-a64.h index 9df9e4ee..a57a9883 100644 --- a/test/a64/traces/sim-fcvtas-wd-trace-a64.h +++ b/test/a64/traces/sim-fcvtas-wd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtas-ws-trace-a64.h b/test/a64/traces/sim-fcvtas-ws-trace-a64.h index 9b8c9f92..fa06fc16 100644 --- a/test/a64/traces/sim-fcvtas-ws-trace-a64.h +++ b/test/a64/traces/sim-fcvtas-ws-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtas-xd-trace-a64.h b/test/a64/traces/sim-fcvtas-xd-trace-a64.h index 09b23470..e6c92c26 100644 --- a/test/a64/traces/sim-fcvtas-xd-trace-a64.h +++ b/test/a64/traces/sim-fcvtas-xd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtas-xs-trace-a64.h b/test/a64/traces/sim-fcvtas-xs-trace-a64.h index 9612b481..2a1396e1 100644 --- a/test/a64/traces/sim-fcvtas-xs-trace-a64.h +++ b/test/a64/traces/sim-fcvtas-xs-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtau-2d-trace-a64.h b/test/a64/traces/sim-fcvtau-2d-trace-a64.h index e07bc3d4..8427cf9e 100644 --- a/test/a64/traces/sim-fcvtau-2d-trace-a64.h +++ b/test/a64/traces/sim-fcvtau-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtau-2s-trace-a64.h b/test/a64/traces/sim-fcvtau-2s-trace-a64.h index b02e31bb..5748bc57 100644 --- a/test/a64/traces/sim-fcvtau-2s-trace-a64.h +++ b/test/a64/traces/sim-fcvtau-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtau-4s-trace-a64.h b/test/a64/traces/sim-fcvtau-4s-trace-a64.h index e506203a..4509e14b 100644 --- a/test/a64/traces/sim-fcvtau-4s-trace-a64.h +++ b/test/a64/traces/sim-fcvtau-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtau-d-trace-a64.h b/test/a64/traces/sim-fcvtau-d-trace-a64.h index 6c12a594..53e567cf 100644 --- a/test/a64/traces/sim-fcvtau-d-trace-a64.h +++ b/test/a64/traces/sim-fcvtau-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtau-s-trace-a64.h b/test/a64/traces/sim-fcvtau-s-trace-a64.h index 806b93d5..749314b5 100644 --- a/test/a64/traces/sim-fcvtau-s-trace-a64.h +++ b/test/a64/traces/sim-fcvtau-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtau-wd-trace-a64.h b/test/a64/traces/sim-fcvtau-wd-trace-a64.h index 82d04381..7cec3d01 100644 --- a/test/a64/traces/sim-fcvtau-wd-trace-a64.h +++ b/test/a64/traces/sim-fcvtau-wd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtau-ws-trace-a64.h b/test/a64/traces/sim-fcvtau-ws-trace-a64.h index eabdeea8..36e03a0a 100644 --- a/test/a64/traces/sim-fcvtau-ws-trace-a64.h +++ b/test/a64/traces/sim-fcvtau-ws-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtau-xd-trace-a64.h b/test/a64/traces/sim-fcvtau-xd-trace-a64.h index 9389cbc3..2a8d0d84 100644 --- a/test/a64/traces/sim-fcvtau-xd-trace-a64.h +++ b/test/a64/traces/sim-fcvtau-xd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtau-xs-trace-a64.h b/test/a64/traces/sim-fcvtau-xs-trace-a64.h index 76eba48c..18c9fb51 100644 --- a/test/a64/traces/sim-fcvtau-xs-trace-a64.h +++ b/test/a64/traces/sim-fcvtau-xs-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtl-2d-trace-a64.h b/test/a64/traces/sim-fcvtl-2d-trace-a64.h index 63f031f0..924d2a38 100644 --- a/test/a64/traces/sim-fcvtl-2d-trace-a64.h +++ b/test/a64/traces/sim-fcvtl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtl-4s-trace-a64.h b/test/a64/traces/sim-fcvtl-4s-trace-a64.h index 3c880420..dc564b65 100644 --- a/test/a64/traces/sim-fcvtl-4s-trace-a64.h +++ b/test/a64/traces/sim-fcvtl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtl2-2d-trace-a64.h b/test/a64/traces/sim-fcvtl2-2d-trace-a64.h index a5769e6b..22dfe536 100644 --- a/test/a64/traces/sim-fcvtl2-2d-trace-a64.h +++ b/test/a64/traces/sim-fcvtl2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtl2-4s-trace-a64.h b/test/a64/traces/sim-fcvtl2-4s-trace-a64.h index 1fda45ad..fbc9313d 100644 --- a/test/a64/traces/sim-fcvtl2-4s-trace-a64.h +++ b/test/a64/traces/sim-fcvtl2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtms-2d-trace-a64.h b/test/a64/traces/sim-fcvtms-2d-trace-a64.h index 32981512..69fdb835 100644 --- a/test/a64/traces/sim-fcvtms-2d-trace-a64.h +++ b/test/a64/traces/sim-fcvtms-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtms-2s-trace-a64.h b/test/a64/traces/sim-fcvtms-2s-trace-a64.h index a1c6d13f..3136e3e4 100644 --- a/test/a64/traces/sim-fcvtms-2s-trace-a64.h +++ b/test/a64/traces/sim-fcvtms-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtms-4s-trace-a64.h b/test/a64/traces/sim-fcvtms-4s-trace-a64.h index f9e41ce9..8430d6f2 100644 --- a/test/a64/traces/sim-fcvtms-4s-trace-a64.h +++ b/test/a64/traces/sim-fcvtms-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtms-d-trace-a64.h b/test/a64/traces/sim-fcvtms-d-trace-a64.h index be140126..3d7f11a9 100644 --- a/test/a64/traces/sim-fcvtms-d-trace-a64.h +++ b/test/a64/traces/sim-fcvtms-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtms-s-trace-a64.h b/test/a64/traces/sim-fcvtms-s-trace-a64.h index f14324af..17f56b3d 100644 --- a/test/a64/traces/sim-fcvtms-s-trace-a64.h +++ b/test/a64/traces/sim-fcvtms-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtms-wd-trace-a64.h b/test/a64/traces/sim-fcvtms-wd-trace-a64.h index 5f933713..e0e9ff83 100644 --- a/test/a64/traces/sim-fcvtms-wd-trace-a64.h +++ b/test/a64/traces/sim-fcvtms-wd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtms-ws-trace-a64.h b/test/a64/traces/sim-fcvtms-ws-trace-a64.h index 555fb404..6bda41e2 100644 --- a/test/a64/traces/sim-fcvtms-ws-trace-a64.h +++ b/test/a64/traces/sim-fcvtms-ws-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtms-xd-trace-a64.h b/test/a64/traces/sim-fcvtms-xd-trace-a64.h index 87b67b9c..936888e7 100644 --- a/test/a64/traces/sim-fcvtms-xd-trace-a64.h +++ b/test/a64/traces/sim-fcvtms-xd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtms-xs-trace-a64.h b/test/a64/traces/sim-fcvtms-xs-trace-a64.h index 033ba17e..41c696da 100644 --- a/test/a64/traces/sim-fcvtms-xs-trace-a64.h +++ b/test/a64/traces/sim-fcvtms-xs-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtmu-2d-trace-a64.h b/test/a64/traces/sim-fcvtmu-2d-trace-a64.h index d940ab48..c3f99d0c 100644 --- a/test/a64/traces/sim-fcvtmu-2d-trace-a64.h +++ b/test/a64/traces/sim-fcvtmu-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtmu-2s-trace-a64.h b/test/a64/traces/sim-fcvtmu-2s-trace-a64.h index a02d831b..38a10b85 100644 --- a/test/a64/traces/sim-fcvtmu-2s-trace-a64.h +++ b/test/a64/traces/sim-fcvtmu-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtmu-4s-trace-a64.h b/test/a64/traces/sim-fcvtmu-4s-trace-a64.h index ca2fb816..d4e1d91d 100644 --- a/test/a64/traces/sim-fcvtmu-4s-trace-a64.h +++ b/test/a64/traces/sim-fcvtmu-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtmu-d-trace-a64.h b/test/a64/traces/sim-fcvtmu-d-trace-a64.h index d595801b..916adaa1 100644 --- a/test/a64/traces/sim-fcvtmu-d-trace-a64.h +++ b/test/a64/traces/sim-fcvtmu-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtmu-s-trace-a64.h b/test/a64/traces/sim-fcvtmu-s-trace-a64.h index 8b83baaf..084fcf0f 100644 --- a/test/a64/traces/sim-fcvtmu-s-trace-a64.h +++ b/test/a64/traces/sim-fcvtmu-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtmu-wd-trace-a64.h b/test/a64/traces/sim-fcvtmu-wd-trace-a64.h index 57c55a29..4939feb1 100644 --- a/test/a64/traces/sim-fcvtmu-wd-trace-a64.h +++ b/test/a64/traces/sim-fcvtmu-wd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtmu-ws-trace-a64.h b/test/a64/traces/sim-fcvtmu-ws-trace-a64.h index 8b760ca1..9f3bee2a 100644 --- a/test/a64/traces/sim-fcvtmu-ws-trace-a64.h +++ b/test/a64/traces/sim-fcvtmu-ws-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtmu-xd-trace-a64.h b/test/a64/traces/sim-fcvtmu-xd-trace-a64.h index ee6ccec7..2993d653 100644 --- a/test/a64/traces/sim-fcvtmu-xd-trace-a64.h +++ b/test/a64/traces/sim-fcvtmu-xd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtmu-xs-trace-a64.h b/test/a64/traces/sim-fcvtmu-xs-trace-a64.h index c1a82415..562fa778 100644 --- a/test/a64/traces/sim-fcvtmu-xs-trace-a64.h +++ b/test/a64/traces/sim-fcvtmu-xs-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtn-2s-trace-a64.h b/test/a64/traces/sim-fcvtn-2s-trace-a64.h index b81ab4bb..6dab851d 100644 --- a/test/a64/traces/sim-fcvtn-2s-trace-a64.h +++ b/test/a64/traces/sim-fcvtn-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtn-4h-trace-a64.h b/test/a64/traces/sim-fcvtn-4h-trace-a64.h index 15c42497..81dddc1b 100644 --- a/test/a64/traces/sim-fcvtn-4h-trace-a64.h +++ b/test/a64/traces/sim-fcvtn-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtn2-4s-trace-a64.h b/test/a64/traces/sim-fcvtn2-4s-trace-a64.h index 30d5387f..e1bf259c 100644 --- a/test/a64/traces/sim-fcvtn2-4s-trace-a64.h +++ b/test/a64/traces/sim-fcvtn2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtn2-8h-trace-a64.h b/test/a64/traces/sim-fcvtn2-8h-trace-a64.h index 98a3f8cb..eeb7a9e0 100644 --- a/test/a64/traces/sim-fcvtn2-8h-trace-a64.h +++ b/test/a64/traces/sim-fcvtn2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtns-2d-trace-a64.h b/test/a64/traces/sim-fcvtns-2d-trace-a64.h index 85130452..464e6185 100644 --- a/test/a64/traces/sim-fcvtns-2d-trace-a64.h +++ b/test/a64/traces/sim-fcvtns-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtns-2s-trace-a64.h b/test/a64/traces/sim-fcvtns-2s-trace-a64.h index 86285dcb..474baac0 100644 --- a/test/a64/traces/sim-fcvtns-2s-trace-a64.h +++ b/test/a64/traces/sim-fcvtns-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtns-4s-trace-a64.h b/test/a64/traces/sim-fcvtns-4s-trace-a64.h index c8c022ad..3475c44f 100644 --- a/test/a64/traces/sim-fcvtns-4s-trace-a64.h +++ b/test/a64/traces/sim-fcvtns-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtns-d-trace-a64.h b/test/a64/traces/sim-fcvtns-d-trace-a64.h index 8aa44ee3..bf64ee26 100644 --- a/test/a64/traces/sim-fcvtns-d-trace-a64.h +++ b/test/a64/traces/sim-fcvtns-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtns-s-trace-a64.h b/test/a64/traces/sim-fcvtns-s-trace-a64.h index 7e7dd146..4b631596 100644 --- a/test/a64/traces/sim-fcvtns-s-trace-a64.h +++ b/test/a64/traces/sim-fcvtns-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtns-wd-trace-a64.h b/test/a64/traces/sim-fcvtns-wd-trace-a64.h index 570bb3ee..0b8837ed 100644 --- a/test/a64/traces/sim-fcvtns-wd-trace-a64.h +++ b/test/a64/traces/sim-fcvtns-wd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtns-ws-trace-a64.h b/test/a64/traces/sim-fcvtns-ws-trace-a64.h index 031b0fce..be3266bd 100644 --- a/test/a64/traces/sim-fcvtns-ws-trace-a64.h +++ b/test/a64/traces/sim-fcvtns-ws-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtns-xd-trace-a64.h b/test/a64/traces/sim-fcvtns-xd-trace-a64.h index 43a1cbf1..7fcdecee 100644 --- a/test/a64/traces/sim-fcvtns-xd-trace-a64.h +++ b/test/a64/traces/sim-fcvtns-xd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtns-xs-trace-a64.h b/test/a64/traces/sim-fcvtns-xs-trace-a64.h index 14cbd914..cd67dec9 100644 --- a/test/a64/traces/sim-fcvtns-xs-trace-a64.h +++ b/test/a64/traces/sim-fcvtns-xs-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtnu-2d-trace-a64.h b/test/a64/traces/sim-fcvtnu-2d-trace-a64.h index c5cf7177..c5176c05 100644 --- a/test/a64/traces/sim-fcvtnu-2d-trace-a64.h +++ b/test/a64/traces/sim-fcvtnu-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtnu-2s-trace-a64.h b/test/a64/traces/sim-fcvtnu-2s-trace-a64.h index fe1171cf..8fd18752 100644 --- a/test/a64/traces/sim-fcvtnu-2s-trace-a64.h +++ b/test/a64/traces/sim-fcvtnu-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtnu-4s-trace-a64.h b/test/a64/traces/sim-fcvtnu-4s-trace-a64.h index 0e4add8e..aef9227d 100644 --- a/test/a64/traces/sim-fcvtnu-4s-trace-a64.h +++ b/test/a64/traces/sim-fcvtnu-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtnu-d-trace-a64.h b/test/a64/traces/sim-fcvtnu-d-trace-a64.h index 4bddc99c..03325e24 100644 --- a/test/a64/traces/sim-fcvtnu-d-trace-a64.h +++ b/test/a64/traces/sim-fcvtnu-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtnu-s-trace-a64.h b/test/a64/traces/sim-fcvtnu-s-trace-a64.h index 06ccc94c..9a7956ce 100644 --- a/test/a64/traces/sim-fcvtnu-s-trace-a64.h +++ b/test/a64/traces/sim-fcvtnu-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtnu-wd-trace-a64.h b/test/a64/traces/sim-fcvtnu-wd-trace-a64.h index a798636c..b0bd34cd 100644 --- a/test/a64/traces/sim-fcvtnu-wd-trace-a64.h +++ b/test/a64/traces/sim-fcvtnu-wd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtnu-ws-trace-a64.h b/test/a64/traces/sim-fcvtnu-ws-trace-a64.h index fc1efdac..84e8832f 100644 --- a/test/a64/traces/sim-fcvtnu-ws-trace-a64.h +++ b/test/a64/traces/sim-fcvtnu-ws-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtnu-xd-trace-a64.h b/test/a64/traces/sim-fcvtnu-xd-trace-a64.h index 8d79a32c..3517979e 100644 --- a/test/a64/traces/sim-fcvtnu-xd-trace-a64.h +++ b/test/a64/traces/sim-fcvtnu-xd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtnu-xs-trace-a64.h b/test/a64/traces/sim-fcvtnu-xs-trace-a64.h index 73c133b6..3b106ba3 100644 --- a/test/a64/traces/sim-fcvtnu-xs-trace-a64.h +++ b/test/a64/traces/sim-fcvtnu-xs-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtps-2d-trace-a64.h b/test/a64/traces/sim-fcvtps-2d-trace-a64.h index 9decab10..e13ae760 100644 --- a/test/a64/traces/sim-fcvtps-2d-trace-a64.h +++ b/test/a64/traces/sim-fcvtps-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtps-2s-trace-a64.h b/test/a64/traces/sim-fcvtps-2s-trace-a64.h index f922ec18..eea61c3d 100644 --- a/test/a64/traces/sim-fcvtps-2s-trace-a64.h +++ b/test/a64/traces/sim-fcvtps-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtps-4s-trace-a64.h b/test/a64/traces/sim-fcvtps-4s-trace-a64.h index 3cb221b7..a2caf2ab 100644 --- a/test/a64/traces/sim-fcvtps-4s-trace-a64.h +++ b/test/a64/traces/sim-fcvtps-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtps-d-trace-a64.h b/test/a64/traces/sim-fcvtps-d-trace-a64.h index ae90702a..7ecf88a6 100644 --- a/test/a64/traces/sim-fcvtps-d-trace-a64.h +++ b/test/a64/traces/sim-fcvtps-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtps-s-trace-a64.h b/test/a64/traces/sim-fcvtps-s-trace-a64.h index 8584db81..9efee290 100644 --- a/test/a64/traces/sim-fcvtps-s-trace-a64.h +++ b/test/a64/traces/sim-fcvtps-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtpu-2d-trace-a64.h b/test/a64/traces/sim-fcvtpu-2d-trace-a64.h index 847610b5..402328c1 100644 --- a/test/a64/traces/sim-fcvtpu-2d-trace-a64.h +++ b/test/a64/traces/sim-fcvtpu-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtpu-2s-trace-a64.h b/test/a64/traces/sim-fcvtpu-2s-trace-a64.h index 236ad8be..8dde4962 100644 --- a/test/a64/traces/sim-fcvtpu-2s-trace-a64.h +++ b/test/a64/traces/sim-fcvtpu-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtpu-4s-trace-a64.h b/test/a64/traces/sim-fcvtpu-4s-trace-a64.h index 3b2532f7..0660ca6c 100644 --- a/test/a64/traces/sim-fcvtpu-4s-trace-a64.h +++ b/test/a64/traces/sim-fcvtpu-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtpu-d-trace-a64.h b/test/a64/traces/sim-fcvtpu-d-trace-a64.h index 7d0fba79..c357c7fd 100644 --- a/test/a64/traces/sim-fcvtpu-d-trace-a64.h +++ b/test/a64/traces/sim-fcvtpu-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtpu-s-trace-a64.h b/test/a64/traces/sim-fcvtpu-s-trace-a64.h index e370a94c..7585eed4 100644 --- a/test/a64/traces/sim-fcvtpu-s-trace-a64.h +++ b/test/a64/traces/sim-fcvtpu-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtxn-2s-trace-a64.h b/test/a64/traces/sim-fcvtxn-2s-trace-a64.h index 1e0fb1ea..a60637fb 100644 --- a/test/a64/traces/sim-fcvtxn-2s-trace-a64.h +++ b/test/a64/traces/sim-fcvtxn-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtxn-scalar-trace-a64.h b/test/a64/traces/sim-fcvtxn-scalar-trace-a64.h index 1b2f25da..314c7561 100644 --- a/test/a64/traces/sim-fcvtxn-scalar-trace-a64.h +++ b/test/a64/traces/sim-fcvtxn-scalar-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtxn2-4s-trace-a64.h b/test/a64/traces/sim-fcvtxn2-4s-trace-a64.h index 2dcb89bc..61ec4405 100644 --- a/test/a64/traces/sim-fcvtxn2-4s-trace-a64.h +++ b/test/a64/traces/sim-fcvtxn2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzs-2d-2opimm-trace-a64.h b/test/a64/traces/sim-fcvtzs-2d-2opimm-trace-a64.h index f42d39b2..08443478 100644 --- a/test/a64/traces/sim-fcvtzs-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcvtzs-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzs-2s-2opimm-trace-a64.h b/test/a64/traces/sim-fcvtzs-2s-2opimm-trace-a64.h index 7d1f8f18..4ad8d255 100644 --- a/test/a64/traces/sim-fcvtzs-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcvtzs-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzs-4s-2opimm-trace-a64.h b/test/a64/traces/sim-fcvtzs-4s-2opimm-trace-a64.h index cba5214d..6202a39b 100644 --- a/test/a64/traces/sim-fcvtzs-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcvtzs-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzs-d-2opimm-trace-a64.h b/test/a64/traces/sim-fcvtzs-d-2opimm-trace-a64.h index e0641c94..e97b36ae 100644 --- a/test/a64/traces/sim-fcvtzs-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcvtzs-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzs-s-2opimm-trace-a64.h b/test/a64/traces/sim-fcvtzs-s-2opimm-trace-a64.h index 49720aed..8ffb044b 100644 --- a/test/a64/traces/sim-fcvtzs-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcvtzs-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzs-wd-trace-a64.h b/test/a64/traces/sim-fcvtzs-wd-trace-a64.h index ce0b3395..38f7546e 100644 --- a/test/a64/traces/sim-fcvtzs-wd-trace-a64.h +++ b/test/a64/traces/sim-fcvtzs-wd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzs-ws-trace-a64.h b/test/a64/traces/sim-fcvtzs-ws-trace-a64.h index 3b951fd5..8c856e57 100644 --- a/test/a64/traces/sim-fcvtzs-ws-trace-a64.h +++ b/test/a64/traces/sim-fcvtzs-ws-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzs-xd-trace-a64.h b/test/a64/traces/sim-fcvtzs-xd-trace-a64.h index 5bd00c10..ae40abad 100644 --- a/test/a64/traces/sim-fcvtzs-xd-trace-a64.h +++ b/test/a64/traces/sim-fcvtzs-xd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzs-xs-trace-a64.h b/test/a64/traces/sim-fcvtzs-xs-trace-a64.h index dc2ea437..5a5be076 100644 --- a/test/a64/traces/sim-fcvtzs-xs-trace-a64.h +++ b/test/a64/traces/sim-fcvtzs-xs-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzu-2d-2opimm-trace-a64.h b/test/a64/traces/sim-fcvtzu-2d-2opimm-trace-a64.h index 1ed0e8f9..c0562fff 100644 --- a/test/a64/traces/sim-fcvtzu-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcvtzu-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzu-2s-2opimm-trace-a64.h b/test/a64/traces/sim-fcvtzu-2s-2opimm-trace-a64.h index 02c8cb1e..29aa2565 100644 --- a/test/a64/traces/sim-fcvtzu-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcvtzu-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzu-4s-2opimm-trace-a64.h b/test/a64/traces/sim-fcvtzu-4s-2opimm-trace-a64.h index a7679405..2ebfe618 100644 --- a/test/a64/traces/sim-fcvtzu-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcvtzu-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzu-d-2opimm-trace-a64.h b/test/a64/traces/sim-fcvtzu-d-2opimm-trace-a64.h index 50161ed0..dc64c7fe 100644 --- a/test/a64/traces/sim-fcvtzu-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcvtzu-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzu-s-2opimm-trace-a64.h b/test/a64/traces/sim-fcvtzu-s-2opimm-trace-a64.h index 86421d94..8e7e9076 100644 --- a/test/a64/traces/sim-fcvtzu-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-fcvtzu-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzu-wd-trace-a64.h b/test/a64/traces/sim-fcvtzu-wd-trace-a64.h index 3084fd88..8aa8f0fc 100644 --- a/test/a64/traces/sim-fcvtzu-wd-trace-a64.h +++ b/test/a64/traces/sim-fcvtzu-wd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzu-ws-trace-a64.h b/test/a64/traces/sim-fcvtzu-ws-trace-a64.h index 671deb4c..05229be2 100644 --- a/test/a64/traces/sim-fcvtzu-ws-trace-a64.h +++ b/test/a64/traces/sim-fcvtzu-ws-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzu-xd-trace-a64.h b/test/a64/traces/sim-fcvtzu-xd-trace-a64.h index 87fb3fc4..1a0d7939 100644 --- a/test/a64/traces/sim-fcvtzu-xd-trace-a64.h +++ b/test/a64/traces/sim-fcvtzu-xd-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fcvtzu-xs-trace-a64.h b/test/a64/traces/sim-fcvtzu-xs-trace-a64.h index 55210f97..895301aa 100644 --- a/test/a64/traces/sim-fcvtzu-xs-trace-a64.h +++ b/test/a64/traces/sim-fcvtzu-xs-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fdiv-2d-trace-a64.h b/test/a64/traces/sim-fdiv-2d-trace-a64.h index 1b7a187d..a5c20300 100644 --- a/test/a64/traces/sim-fdiv-2d-trace-a64.h +++ b/test/a64/traces/sim-fdiv-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fdiv-2s-trace-a64.h b/test/a64/traces/sim-fdiv-2s-trace-a64.h index dce2d571..f21c1bab 100644 --- a/test/a64/traces/sim-fdiv-2s-trace-a64.h +++ b/test/a64/traces/sim-fdiv-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fdiv-4s-trace-a64.h b/test/a64/traces/sim-fdiv-4s-trace-a64.h index 99662512..bc7852e6 100644 --- a/test/a64/traces/sim-fdiv-4s-trace-a64.h +++ b/test/a64/traces/sim-fdiv-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fdiv-d-trace-a64.h b/test/a64/traces/sim-fdiv-d-trace-a64.h index 9da3a5eb..f6a89a01 100644 --- a/test/a64/traces/sim-fdiv-d-trace-a64.h +++ b/test/a64/traces/sim-fdiv-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fdiv-s-trace-a64.h b/test/a64/traces/sim-fdiv-s-trace-a64.h index eebb80d6..7144cb4b 100644 --- a/test/a64/traces/sim-fdiv-s-trace-a64.h +++ b/test/a64/traces/sim-fdiv-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmadd-d-trace-a64.h b/test/a64/traces/sim-fmadd-d-trace-a64.h index 650b5076..dde34d94 100644 --- a/test/a64/traces/sim-fmadd-d-trace-a64.h +++ b/test/a64/traces/sim-fmadd-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmadd-s-trace-a64.h b/test/a64/traces/sim-fmadd-s-trace-a64.h index 4e5a39f9..c8483d99 100644 --- a/test/a64/traces/sim-fmadd-s-trace-a64.h +++ b/test/a64/traces/sim-fmadd-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmax-2d-trace-a64.h b/test/a64/traces/sim-fmax-2d-trace-a64.h index d6d5615d..7759192a 100644 --- a/test/a64/traces/sim-fmax-2d-trace-a64.h +++ b/test/a64/traces/sim-fmax-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmax-2s-trace-a64.h b/test/a64/traces/sim-fmax-2s-trace-a64.h index d017fb55..5e2bee90 100644 --- a/test/a64/traces/sim-fmax-2s-trace-a64.h +++ b/test/a64/traces/sim-fmax-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmax-4s-trace-a64.h b/test/a64/traces/sim-fmax-4s-trace-a64.h index e7564125..27e985c2 100644 --- a/test/a64/traces/sim-fmax-4s-trace-a64.h +++ b/test/a64/traces/sim-fmax-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmax-d-trace-a64.h b/test/a64/traces/sim-fmax-d-trace-a64.h index da3adb75..6941cac0 100644 --- a/test/a64/traces/sim-fmax-d-trace-a64.h +++ b/test/a64/traces/sim-fmax-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmax-s-trace-a64.h b/test/a64/traces/sim-fmax-s-trace-a64.h index 8722ca36..b402a4c9 100644 --- a/test/a64/traces/sim-fmax-s-trace-a64.h +++ b/test/a64/traces/sim-fmax-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxnm-2d-trace-a64.h b/test/a64/traces/sim-fmaxnm-2d-trace-a64.h index 71edb6d2..e7458b2c 100644 --- a/test/a64/traces/sim-fmaxnm-2d-trace-a64.h +++ b/test/a64/traces/sim-fmaxnm-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxnm-2s-trace-a64.h b/test/a64/traces/sim-fmaxnm-2s-trace-a64.h index 8a9f1cf3..e7af6d45 100644 --- a/test/a64/traces/sim-fmaxnm-2s-trace-a64.h +++ b/test/a64/traces/sim-fmaxnm-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxnm-4s-trace-a64.h b/test/a64/traces/sim-fmaxnm-4s-trace-a64.h index 093fa5d3..19571ed9 100644 --- a/test/a64/traces/sim-fmaxnm-4s-trace-a64.h +++ b/test/a64/traces/sim-fmaxnm-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxnm-d-trace-a64.h b/test/a64/traces/sim-fmaxnm-d-trace-a64.h index 2b45858c..b36a3d04 100644 --- a/test/a64/traces/sim-fmaxnm-d-trace-a64.h +++ b/test/a64/traces/sim-fmaxnm-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxnm-s-trace-a64.h b/test/a64/traces/sim-fmaxnm-s-trace-a64.h index 09bb86ef..52adc88d 100644 --- a/test/a64/traces/sim-fmaxnm-s-trace-a64.h +++ b/test/a64/traces/sim-fmaxnm-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxnmp-2d-trace-a64.h b/test/a64/traces/sim-fmaxnmp-2d-trace-a64.h index 1738b989..14a9b06c 100644 --- a/test/a64/traces/sim-fmaxnmp-2d-trace-a64.h +++ b/test/a64/traces/sim-fmaxnmp-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxnmp-2s-trace-a64.h b/test/a64/traces/sim-fmaxnmp-2s-trace-a64.h index faacde24..d98215ae 100644 --- a/test/a64/traces/sim-fmaxnmp-2s-trace-a64.h +++ b/test/a64/traces/sim-fmaxnmp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxnmp-4s-trace-a64.h b/test/a64/traces/sim-fmaxnmp-4s-trace-a64.h index 2fae2981..17cebc2c 100644 --- a/test/a64/traces/sim-fmaxnmp-4s-trace-a64.h +++ b/test/a64/traces/sim-fmaxnmp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxnmp-d-trace-a64.h b/test/a64/traces/sim-fmaxnmp-d-trace-a64.h index db22f607..77cee2f0 100644 --- a/test/a64/traces/sim-fmaxnmp-d-trace-a64.h +++ b/test/a64/traces/sim-fmaxnmp-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxnmp-s-trace-a64.h b/test/a64/traces/sim-fmaxnmp-s-trace-a64.h index 2ae78a2f..5a610320 100644 --- a/test/a64/traces/sim-fmaxnmp-s-trace-a64.h +++ b/test/a64/traces/sim-fmaxnmp-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxnmv-s-4s-trace-a64.h b/test/a64/traces/sim-fmaxnmv-s-4s-trace-a64.h index 6075defa..35d433b2 100644 --- a/test/a64/traces/sim-fmaxnmv-s-4s-trace-a64.h +++ b/test/a64/traces/sim-fmaxnmv-s-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxp-2d-trace-a64.h b/test/a64/traces/sim-fmaxp-2d-trace-a64.h index 85112777..75633306 100644 --- a/test/a64/traces/sim-fmaxp-2d-trace-a64.h +++ b/test/a64/traces/sim-fmaxp-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxp-2s-trace-a64.h b/test/a64/traces/sim-fmaxp-2s-trace-a64.h index f1f9a7d7..9794c59c 100644 --- a/test/a64/traces/sim-fmaxp-2s-trace-a64.h +++ b/test/a64/traces/sim-fmaxp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxp-4s-trace-a64.h b/test/a64/traces/sim-fmaxp-4s-trace-a64.h index f0742ce2..e2a07540 100644 --- a/test/a64/traces/sim-fmaxp-4s-trace-a64.h +++ b/test/a64/traces/sim-fmaxp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxp-d-trace-a64.h b/test/a64/traces/sim-fmaxp-d-trace-a64.h index f953c9d1..e07a512f 100644 --- a/test/a64/traces/sim-fmaxp-d-trace-a64.h +++ b/test/a64/traces/sim-fmaxp-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxp-s-trace-a64.h b/test/a64/traces/sim-fmaxp-s-trace-a64.h index 5722ec2e..5a9c89ec 100644 --- a/test/a64/traces/sim-fmaxp-s-trace-a64.h +++ b/test/a64/traces/sim-fmaxp-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmaxv-s-4s-trace-a64.h b/test/a64/traces/sim-fmaxv-s-4s-trace-a64.h index 52177148..6e7d2062 100644 --- a/test/a64/traces/sim-fmaxv-s-4s-trace-a64.h +++ b/test/a64/traces/sim-fmaxv-s-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmin-2d-trace-a64.h b/test/a64/traces/sim-fmin-2d-trace-a64.h index 189bb872..165c91eb 100644 --- a/test/a64/traces/sim-fmin-2d-trace-a64.h +++ b/test/a64/traces/sim-fmin-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmin-2s-trace-a64.h b/test/a64/traces/sim-fmin-2s-trace-a64.h index 739baa21..df1864b4 100644 --- a/test/a64/traces/sim-fmin-2s-trace-a64.h +++ b/test/a64/traces/sim-fmin-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmin-4s-trace-a64.h b/test/a64/traces/sim-fmin-4s-trace-a64.h index 1cac405b..09aec762 100644 --- a/test/a64/traces/sim-fmin-4s-trace-a64.h +++ b/test/a64/traces/sim-fmin-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmin-d-trace-a64.h b/test/a64/traces/sim-fmin-d-trace-a64.h index 2b4541c8..6acfa865 100644 --- a/test/a64/traces/sim-fmin-d-trace-a64.h +++ b/test/a64/traces/sim-fmin-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmin-s-trace-a64.h b/test/a64/traces/sim-fmin-s-trace-a64.h index e9a02094..4fc21f66 100644 --- a/test/a64/traces/sim-fmin-s-trace-a64.h +++ b/test/a64/traces/sim-fmin-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminnm-2d-trace-a64.h b/test/a64/traces/sim-fminnm-2d-trace-a64.h index 975863d0..547a69a1 100644 --- a/test/a64/traces/sim-fminnm-2d-trace-a64.h +++ b/test/a64/traces/sim-fminnm-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminnm-2s-trace-a64.h b/test/a64/traces/sim-fminnm-2s-trace-a64.h index 767d7070..e8ec3cd5 100644 --- a/test/a64/traces/sim-fminnm-2s-trace-a64.h +++ b/test/a64/traces/sim-fminnm-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminnm-4s-trace-a64.h b/test/a64/traces/sim-fminnm-4s-trace-a64.h index c61e0176..15620933 100644 --- a/test/a64/traces/sim-fminnm-4s-trace-a64.h +++ b/test/a64/traces/sim-fminnm-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminnm-d-trace-a64.h b/test/a64/traces/sim-fminnm-d-trace-a64.h index ba9a0bc2..8b06a2da 100644 --- a/test/a64/traces/sim-fminnm-d-trace-a64.h +++ b/test/a64/traces/sim-fminnm-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminnm-s-trace-a64.h b/test/a64/traces/sim-fminnm-s-trace-a64.h index cb673505..77f7b190 100644 --- a/test/a64/traces/sim-fminnm-s-trace-a64.h +++ b/test/a64/traces/sim-fminnm-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminnmp-2d-trace-a64.h b/test/a64/traces/sim-fminnmp-2d-trace-a64.h index 37029e4e..16357ef0 100644 --- a/test/a64/traces/sim-fminnmp-2d-trace-a64.h +++ b/test/a64/traces/sim-fminnmp-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminnmp-2s-trace-a64.h b/test/a64/traces/sim-fminnmp-2s-trace-a64.h index 7a76135a..d34fc6d8 100644 --- a/test/a64/traces/sim-fminnmp-2s-trace-a64.h +++ b/test/a64/traces/sim-fminnmp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminnmp-4s-trace-a64.h b/test/a64/traces/sim-fminnmp-4s-trace-a64.h index 158dc3b3..7649eb3e 100644 --- a/test/a64/traces/sim-fminnmp-4s-trace-a64.h +++ b/test/a64/traces/sim-fminnmp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminnmp-d-trace-a64.h b/test/a64/traces/sim-fminnmp-d-trace-a64.h index 74868a21..268961d5 100644 --- a/test/a64/traces/sim-fminnmp-d-trace-a64.h +++ b/test/a64/traces/sim-fminnmp-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminnmp-s-trace-a64.h b/test/a64/traces/sim-fminnmp-s-trace-a64.h index 99dc2eb1..0ba9f86b 100644 --- a/test/a64/traces/sim-fminnmp-s-trace-a64.h +++ b/test/a64/traces/sim-fminnmp-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminnmv-s-4s-trace-a64.h b/test/a64/traces/sim-fminnmv-s-4s-trace-a64.h index c784f240..4bc0f968 100644 --- a/test/a64/traces/sim-fminnmv-s-4s-trace-a64.h +++ b/test/a64/traces/sim-fminnmv-s-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminp-2d-trace-a64.h b/test/a64/traces/sim-fminp-2d-trace-a64.h index 9ba35da2..0837915a 100644 --- a/test/a64/traces/sim-fminp-2d-trace-a64.h +++ b/test/a64/traces/sim-fminp-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminp-2s-trace-a64.h b/test/a64/traces/sim-fminp-2s-trace-a64.h index 61d2d5b7..a78f4cb5 100644 --- a/test/a64/traces/sim-fminp-2s-trace-a64.h +++ b/test/a64/traces/sim-fminp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminp-4s-trace-a64.h b/test/a64/traces/sim-fminp-4s-trace-a64.h index 045340da..80857080 100644 --- a/test/a64/traces/sim-fminp-4s-trace-a64.h +++ b/test/a64/traces/sim-fminp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminp-d-trace-a64.h b/test/a64/traces/sim-fminp-d-trace-a64.h index 2744ca5e..16e0c8d0 100644 --- a/test/a64/traces/sim-fminp-d-trace-a64.h +++ b/test/a64/traces/sim-fminp-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminp-s-trace-a64.h b/test/a64/traces/sim-fminp-s-trace-a64.h index f76a5fde..2f7e72c6 100644 --- a/test/a64/traces/sim-fminp-s-trace-a64.h +++ b/test/a64/traces/sim-fminp-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fminv-s-4s-trace-a64.h b/test/a64/traces/sim-fminv-s-4s-trace-a64.h index b4d6c15e..ec53fa4c 100644 --- a/test/a64/traces/sim-fminv-s-4s-trace-a64.h +++ b/test/a64/traces/sim-fminv-s-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmla-2d-2d-d-trace-a64.h b/test/a64/traces/sim-fmla-2d-2d-d-trace-a64.h index 8c6ec326..e3b3b7f5 100644 --- a/test/a64/traces/sim-fmla-2d-2d-d-trace-a64.h +++ b/test/a64/traces/sim-fmla-2d-2d-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmla-2d-trace-a64.h b/test/a64/traces/sim-fmla-2d-trace-a64.h index c9b5899c..bc0cc6a8 100644 --- a/test/a64/traces/sim-fmla-2d-trace-a64.h +++ b/test/a64/traces/sim-fmla-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmla-2s-2s-s-trace-a64.h b/test/a64/traces/sim-fmla-2s-2s-s-trace-a64.h index e9b9cbc1..d2a19686 100644 --- a/test/a64/traces/sim-fmla-2s-2s-s-trace-a64.h +++ b/test/a64/traces/sim-fmla-2s-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmla-2s-trace-a64.h b/test/a64/traces/sim-fmla-2s-trace-a64.h index d56969bd..af0d2cd0 100644 --- a/test/a64/traces/sim-fmla-2s-trace-a64.h +++ b/test/a64/traces/sim-fmla-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmla-4s-4s-s-trace-a64.h b/test/a64/traces/sim-fmla-4s-4s-s-trace-a64.h index 70812071..6d032c63 100644 --- a/test/a64/traces/sim-fmla-4s-4s-s-trace-a64.h +++ b/test/a64/traces/sim-fmla-4s-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmla-4s-trace-a64.h b/test/a64/traces/sim-fmla-4s-trace-a64.h index ff04947c..07973caa 100644 --- a/test/a64/traces/sim-fmla-4s-trace-a64.h +++ b/test/a64/traces/sim-fmla-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmla-d-d-d-trace-a64.h b/test/a64/traces/sim-fmla-d-d-d-trace-a64.h index b75be387..d6d7c97e 100644 --- a/test/a64/traces/sim-fmla-d-d-d-trace-a64.h +++ b/test/a64/traces/sim-fmla-d-d-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmla-s-s-s-trace-a64.h b/test/a64/traces/sim-fmla-s-s-s-trace-a64.h index 8986f57b..a681c6a5 100644 --- a/test/a64/traces/sim-fmla-s-s-s-trace-a64.h +++ b/test/a64/traces/sim-fmla-s-s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmls-2d-2d-d-trace-a64.h b/test/a64/traces/sim-fmls-2d-2d-d-trace-a64.h index 0d9eeb3e..7a283035 100644 --- a/test/a64/traces/sim-fmls-2d-2d-d-trace-a64.h +++ b/test/a64/traces/sim-fmls-2d-2d-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmls-2d-trace-a64.h b/test/a64/traces/sim-fmls-2d-trace-a64.h index 3626d0b5..c7259c81 100644 --- a/test/a64/traces/sim-fmls-2d-trace-a64.h +++ b/test/a64/traces/sim-fmls-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmls-2s-2s-s-trace-a64.h b/test/a64/traces/sim-fmls-2s-2s-s-trace-a64.h index cfb1481b..6ce4530c 100644 --- a/test/a64/traces/sim-fmls-2s-2s-s-trace-a64.h +++ b/test/a64/traces/sim-fmls-2s-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmls-2s-trace-a64.h b/test/a64/traces/sim-fmls-2s-trace-a64.h index 4d7a63b2..c5a0c034 100644 --- a/test/a64/traces/sim-fmls-2s-trace-a64.h +++ b/test/a64/traces/sim-fmls-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmls-4s-4s-s-trace-a64.h b/test/a64/traces/sim-fmls-4s-4s-s-trace-a64.h index 9e7b9c74..ecb75d15 100644 --- a/test/a64/traces/sim-fmls-4s-4s-s-trace-a64.h +++ b/test/a64/traces/sim-fmls-4s-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmls-4s-trace-a64.h b/test/a64/traces/sim-fmls-4s-trace-a64.h index 4924b0ed..261dbcc6 100644 --- a/test/a64/traces/sim-fmls-4s-trace-a64.h +++ b/test/a64/traces/sim-fmls-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmls-d-d-d-trace-a64.h b/test/a64/traces/sim-fmls-d-d-d-trace-a64.h index ec188682..6291b492 100644 --- a/test/a64/traces/sim-fmls-d-d-d-trace-a64.h +++ b/test/a64/traces/sim-fmls-d-d-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmls-s-s-s-trace-a64.h b/test/a64/traces/sim-fmls-s-s-s-trace-a64.h index e55e4a66..92bb11a7 100644 --- a/test/a64/traces/sim-fmls-s-s-s-trace-a64.h +++ b/test/a64/traces/sim-fmls-s-s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmov-d-trace-a64.h b/test/a64/traces/sim-fmov-d-trace-a64.h index bd609e0e..4cba47c9 100644 --- a/test/a64/traces/sim-fmov-d-trace-a64.h +++ b/test/a64/traces/sim-fmov-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmov-s-trace-a64.h b/test/a64/traces/sim-fmov-s-trace-a64.h index 42fd8d7f..8c2bab74 100644 --- a/test/a64/traces/sim-fmov-s-trace-a64.h +++ b/test/a64/traces/sim-fmov-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmsub-d-trace-a64.h b/test/a64/traces/sim-fmsub-d-trace-a64.h index e09b947f..f7bb57df 100644 --- a/test/a64/traces/sim-fmsub-d-trace-a64.h +++ b/test/a64/traces/sim-fmsub-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmsub-s-trace-a64.h b/test/a64/traces/sim-fmsub-s-trace-a64.h index 81948a40..53b75e00 100644 --- a/test/a64/traces/sim-fmsub-s-trace-a64.h +++ b/test/a64/traces/sim-fmsub-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmul-2d-2d-d-trace-a64.h b/test/a64/traces/sim-fmul-2d-2d-d-trace-a64.h index 033720de..a2ed1913 100644 --- a/test/a64/traces/sim-fmul-2d-2d-d-trace-a64.h +++ b/test/a64/traces/sim-fmul-2d-2d-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmul-2d-trace-a64.h b/test/a64/traces/sim-fmul-2d-trace-a64.h index 1e161c61..ca3d62a8 100644 --- a/test/a64/traces/sim-fmul-2d-trace-a64.h +++ b/test/a64/traces/sim-fmul-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmul-2s-2s-s-trace-a64.h b/test/a64/traces/sim-fmul-2s-2s-s-trace-a64.h index 038e1f72..05141428 100644 --- a/test/a64/traces/sim-fmul-2s-2s-s-trace-a64.h +++ b/test/a64/traces/sim-fmul-2s-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmul-2s-trace-a64.h b/test/a64/traces/sim-fmul-2s-trace-a64.h index 975702a0..37fb9469 100644 --- a/test/a64/traces/sim-fmul-2s-trace-a64.h +++ b/test/a64/traces/sim-fmul-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmul-4s-4s-s-trace-a64.h b/test/a64/traces/sim-fmul-4s-4s-s-trace-a64.h index d09164b0..19730606 100644 --- a/test/a64/traces/sim-fmul-4s-4s-s-trace-a64.h +++ b/test/a64/traces/sim-fmul-4s-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmul-4s-trace-a64.h b/test/a64/traces/sim-fmul-4s-trace-a64.h index 90dccbc2..6f80e465 100644 --- a/test/a64/traces/sim-fmul-4s-trace-a64.h +++ b/test/a64/traces/sim-fmul-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmul-d-d-d-trace-a64.h b/test/a64/traces/sim-fmul-d-d-d-trace-a64.h index 8de9eb77..0498b118 100644 --- a/test/a64/traces/sim-fmul-d-d-d-trace-a64.h +++ b/test/a64/traces/sim-fmul-d-d-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmul-d-trace-a64.h b/test/a64/traces/sim-fmul-d-trace-a64.h index ac2bed2b..a76e42cc 100644 --- a/test/a64/traces/sim-fmul-d-trace-a64.h +++ b/test/a64/traces/sim-fmul-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmul-s-s-s-trace-a64.h b/test/a64/traces/sim-fmul-s-s-s-trace-a64.h index ac66709e..87f94dec 100644 --- a/test/a64/traces/sim-fmul-s-s-s-trace-a64.h +++ b/test/a64/traces/sim-fmul-s-s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmul-s-trace-a64.h b/test/a64/traces/sim-fmul-s-trace-a64.h index 88c9acb9..670afc97 100644 --- a/test/a64/traces/sim-fmul-s-trace-a64.h +++ b/test/a64/traces/sim-fmul-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmulx-2d-2d-d-trace-a64.h b/test/a64/traces/sim-fmulx-2d-2d-d-trace-a64.h index f4ec615b..548b62fd 100644 --- a/test/a64/traces/sim-fmulx-2d-2d-d-trace-a64.h +++ b/test/a64/traces/sim-fmulx-2d-2d-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmulx-2d-trace-a64.h b/test/a64/traces/sim-fmulx-2d-trace-a64.h index 9ef4f2b7..8b1df1d2 100644 --- a/test/a64/traces/sim-fmulx-2d-trace-a64.h +++ b/test/a64/traces/sim-fmulx-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmulx-2s-2s-s-trace-a64.h b/test/a64/traces/sim-fmulx-2s-2s-s-trace-a64.h index 9be20e6c..51f1c412 100644 --- a/test/a64/traces/sim-fmulx-2s-2s-s-trace-a64.h +++ b/test/a64/traces/sim-fmulx-2s-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmulx-2s-trace-a64.h b/test/a64/traces/sim-fmulx-2s-trace-a64.h index 5d25de60..fa5286fe 100644 --- a/test/a64/traces/sim-fmulx-2s-trace-a64.h +++ b/test/a64/traces/sim-fmulx-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmulx-4s-4s-s-trace-a64.h b/test/a64/traces/sim-fmulx-4s-4s-s-trace-a64.h index 9e168c2a..e213dc10 100644 --- a/test/a64/traces/sim-fmulx-4s-4s-s-trace-a64.h +++ b/test/a64/traces/sim-fmulx-4s-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmulx-4s-trace-a64.h b/test/a64/traces/sim-fmulx-4s-trace-a64.h index 67cef582..57c9f1e8 100644 --- a/test/a64/traces/sim-fmulx-4s-trace-a64.h +++ b/test/a64/traces/sim-fmulx-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmulx-d-d-d-trace-a64.h b/test/a64/traces/sim-fmulx-d-d-d-trace-a64.h index 38e62c79..9290be1b 100644 --- a/test/a64/traces/sim-fmulx-d-d-d-trace-a64.h +++ b/test/a64/traces/sim-fmulx-d-d-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmulx-d-trace-a64.h b/test/a64/traces/sim-fmulx-d-trace-a64.h index 0005cc9a..c7f2e1cc 100644 --- a/test/a64/traces/sim-fmulx-d-trace-a64.h +++ b/test/a64/traces/sim-fmulx-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmulx-s-s-s-trace-a64.h b/test/a64/traces/sim-fmulx-s-s-s-trace-a64.h index a3b42b81..d0f85f16 100644 --- a/test/a64/traces/sim-fmulx-s-s-s-trace-a64.h +++ b/test/a64/traces/sim-fmulx-s-s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fmulx-s-trace-a64.h b/test/a64/traces/sim-fmulx-s-trace-a64.h index 2f8ab7c6..eeb12d03 100644 --- a/test/a64/traces/sim-fmulx-s-trace-a64.h +++ b/test/a64/traces/sim-fmulx-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fneg-2d-trace-a64.h b/test/a64/traces/sim-fneg-2d-trace-a64.h index 37a364df..7d79d910 100644 --- a/test/a64/traces/sim-fneg-2d-trace-a64.h +++ b/test/a64/traces/sim-fneg-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fneg-2s-trace-a64.h b/test/a64/traces/sim-fneg-2s-trace-a64.h index 2c023fca..f344b86d 100644 --- a/test/a64/traces/sim-fneg-2s-trace-a64.h +++ b/test/a64/traces/sim-fneg-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fneg-4s-trace-a64.h b/test/a64/traces/sim-fneg-4s-trace-a64.h index 0b021f34..54e5bb64 100644 --- a/test/a64/traces/sim-fneg-4s-trace-a64.h +++ b/test/a64/traces/sim-fneg-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fneg-d-trace-a64.h b/test/a64/traces/sim-fneg-d-trace-a64.h index 08b34d09..e29df68e 100644 --- a/test/a64/traces/sim-fneg-d-trace-a64.h +++ b/test/a64/traces/sim-fneg-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fneg-s-trace-a64.h b/test/a64/traces/sim-fneg-s-trace-a64.h index 5aebcedf..6ad6176b 100644 --- a/test/a64/traces/sim-fneg-s-trace-a64.h +++ b/test/a64/traces/sim-fneg-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fnmadd-d-trace-a64.h b/test/a64/traces/sim-fnmadd-d-trace-a64.h index d75bed6e..a1fc51ca 100644 --- a/test/a64/traces/sim-fnmadd-d-trace-a64.h +++ b/test/a64/traces/sim-fnmadd-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fnmadd-s-trace-a64.h b/test/a64/traces/sim-fnmadd-s-trace-a64.h index d3cab31b..ef7c76c3 100644 --- a/test/a64/traces/sim-fnmadd-s-trace-a64.h +++ b/test/a64/traces/sim-fnmadd-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fnmsub-d-trace-a64.h b/test/a64/traces/sim-fnmsub-d-trace-a64.h index 9750f3c7..a0feecf1 100644 --- a/test/a64/traces/sim-fnmsub-d-trace-a64.h +++ b/test/a64/traces/sim-fnmsub-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fnmsub-s-trace-a64.h b/test/a64/traces/sim-fnmsub-s-trace-a64.h index de5ef104..ae27c631 100644 --- a/test/a64/traces/sim-fnmsub-s-trace-a64.h +++ b/test/a64/traces/sim-fnmsub-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fnmul-d-trace-a64.h b/test/a64/traces/sim-fnmul-d-trace-a64.h index cf07bb01..78c1d39d 100644 --- a/test/a64/traces/sim-fnmul-d-trace-a64.h +++ b/test/a64/traces/sim-fnmul-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fnmul-s-trace-a64.h b/test/a64/traces/sim-fnmul-s-trace-a64.h index 7652ee10..75c26bc4 100644 --- a/test/a64/traces/sim-fnmul-s-trace-a64.h +++ b/test/a64/traces/sim-fnmul-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frecpe-2d-trace-a64.h b/test/a64/traces/sim-frecpe-2d-trace-a64.h index 6f995826..3dd3b6d6 100644 --- a/test/a64/traces/sim-frecpe-2d-trace-a64.h +++ b/test/a64/traces/sim-frecpe-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frecpe-2s-trace-a64.h b/test/a64/traces/sim-frecpe-2s-trace-a64.h index 16ffde95..7d469ba4 100644 --- a/test/a64/traces/sim-frecpe-2s-trace-a64.h +++ b/test/a64/traces/sim-frecpe-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frecpe-4s-trace-a64.h b/test/a64/traces/sim-frecpe-4s-trace-a64.h index 77593b57..adb4107f 100644 --- a/test/a64/traces/sim-frecpe-4s-trace-a64.h +++ b/test/a64/traces/sim-frecpe-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frecpe-d-trace-a64.h b/test/a64/traces/sim-frecpe-d-trace-a64.h index 7757b036..767af248 100644 --- a/test/a64/traces/sim-frecpe-d-trace-a64.h +++ b/test/a64/traces/sim-frecpe-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frecpe-s-trace-a64.h b/test/a64/traces/sim-frecpe-s-trace-a64.h index 3edbf1b9..c1d5acb6 100644 --- a/test/a64/traces/sim-frecpe-s-trace-a64.h +++ b/test/a64/traces/sim-frecpe-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frecps-2d-trace-a64.h b/test/a64/traces/sim-frecps-2d-trace-a64.h index 45f09b87..0970925c 100644 --- a/test/a64/traces/sim-frecps-2d-trace-a64.h +++ b/test/a64/traces/sim-frecps-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frecps-2s-trace-a64.h b/test/a64/traces/sim-frecps-2s-trace-a64.h index e584e452..4cd44f3b 100644 --- a/test/a64/traces/sim-frecps-2s-trace-a64.h +++ b/test/a64/traces/sim-frecps-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frecps-4s-trace-a64.h b/test/a64/traces/sim-frecps-4s-trace-a64.h index 92a6d370..467516c0 100644 --- a/test/a64/traces/sim-frecps-4s-trace-a64.h +++ b/test/a64/traces/sim-frecps-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frecps-d-trace-a64.h b/test/a64/traces/sim-frecps-d-trace-a64.h index 384caac7..208140df 100644 --- a/test/a64/traces/sim-frecps-d-trace-a64.h +++ b/test/a64/traces/sim-frecps-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frecps-s-trace-a64.h b/test/a64/traces/sim-frecps-s-trace-a64.h index c00ae0c2..5d38654d 100644 --- a/test/a64/traces/sim-frecps-s-trace-a64.h +++ b/test/a64/traces/sim-frecps-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frecpx-d-trace-a64.h b/test/a64/traces/sim-frecpx-d-trace-a64.h index 1991f4c4..6b82dd52 100644 --- a/test/a64/traces/sim-frecpx-d-trace-a64.h +++ b/test/a64/traces/sim-frecpx-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frecpx-s-trace-a64.h b/test/a64/traces/sim-frecpx-s-trace-a64.h index 8194b1bf..d56c8590 100644 --- a/test/a64/traces/sim-frecpx-s-trace-a64.h +++ b/test/a64/traces/sim-frecpx-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frinta-2d-trace-a64.h b/test/a64/traces/sim-frinta-2d-trace-a64.h index 4286d896..0dd591d4 100644 --- a/test/a64/traces/sim-frinta-2d-trace-a64.h +++ b/test/a64/traces/sim-frinta-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frinta-2s-trace-a64.h b/test/a64/traces/sim-frinta-2s-trace-a64.h index 798a1d0b..1658262b 100644 --- a/test/a64/traces/sim-frinta-2s-trace-a64.h +++ b/test/a64/traces/sim-frinta-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frinta-4s-trace-a64.h b/test/a64/traces/sim-frinta-4s-trace-a64.h index 2b609986..27a0bc5d 100644 --- a/test/a64/traces/sim-frinta-4s-trace-a64.h +++ b/test/a64/traces/sim-frinta-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frinta-d-trace-a64.h b/test/a64/traces/sim-frinta-d-trace-a64.h index 53e8d29a..e4395da0 100644 --- a/test/a64/traces/sim-frinta-d-trace-a64.h +++ b/test/a64/traces/sim-frinta-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frinta-s-trace-a64.h b/test/a64/traces/sim-frinta-s-trace-a64.h index cd65c4ae..3c7e203a 100644 --- a/test/a64/traces/sim-frinta-s-trace-a64.h +++ b/test/a64/traces/sim-frinta-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frinti-2d-trace-a64.h b/test/a64/traces/sim-frinti-2d-trace-a64.h index 29bdec01..c3fcfa8d 100644 --- a/test/a64/traces/sim-frinti-2d-trace-a64.h +++ b/test/a64/traces/sim-frinti-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frinti-2s-trace-a64.h b/test/a64/traces/sim-frinti-2s-trace-a64.h index b3d79201..e411676c 100644 --- a/test/a64/traces/sim-frinti-2s-trace-a64.h +++ b/test/a64/traces/sim-frinti-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frinti-4s-trace-a64.h b/test/a64/traces/sim-frinti-4s-trace-a64.h index bfbedbf5..29e94afa 100644 --- a/test/a64/traces/sim-frinti-4s-trace-a64.h +++ b/test/a64/traces/sim-frinti-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frinti-d-trace-a64.h b/test/a64/traces/sim-frinti-d-trace-a64.h index 5f21304f..3fa4ad3f 100644 --- a/test/a64/traces/sim-frinti-d-trace-a64.h +++ b/test/a64/traces/sim-frinti-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frinti-s-trace-a64.h b/test/a64/traces/sim-frinti-s-trace-a64.h index 31894b30..cf4a109f 100644 --- a/test/a64/traces/sim-frinti-s-trace-a64.h +++ b/test/a64/traces/sim-frinti-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintm-2d-trace-a64.h b/test/a64/traces/sim-frintm-2d-trace-a64.h index 686813b7..663e60be 100644 --- a/test/a64/traces/sim-frintm-2d-trace-a64.h +++ b/test/a64/traces/sim-frintm-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintm-2s-trace-a64.h b/test/a64/traces/sim-frintm-2s-trace-a64.h index dd9e5128..3f4940fd 100644 --- a/test/a64/traces/sim-frintm-2s-trace-a64.h +++ b/test/a64/traces/sim-frintm-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintm-4s-trace-a64.h b/test/a64/traces/sim-frintm-4s-trace-a64.h index 707283ce..8905e8d4 100644 --- a/test/a64/traces/sim-frintm-4s-trace-a64.h +++ b/test/a64/traces/sim-frintm-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintm-d-trace-a64.h b/test/a64/traces/sim-frintm-d-trace-a64.h index 23d1d1e4..0a32c7c1 100644 --- a/test/a64/traces/sim-frintm-d-trace-a64.h +++ b/test/a64/traces/sim-frintm-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintm-s-trace-a64.h b/test/a64/traces/sim-frintm-s-trace-a64.h index bc2c8103..53ea4dd5 100644 --- a/test/a64/traces/sim-frintm-s-trace-a64.h +++ b/test/a64/traces/sim-frintm-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintn-2d-trace-a64.h b/test/a64/traces/sim-frintn-2d-trace-a64.h index 4f147362..c4a1e404 100644 --- a/test/a64/traces/sim-frintn-2d-trace-a64.h +++ b/test/a64/traces/sim-frintn-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintn-2s-trace-a64.h b/test/a64/traces/sim-frintn-2s-trace-a64.h index 5224365d..09c8b286 100644 --- a/test/a64/traces/sim-frintn-2s-trace-a64.h +++ b/test/a64/traces/sim-frintn-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintn-4s-trace-a64.h b/test/a64/traces/sim-frintn-4s-trace-a64.h index e14b1164..3e6a5766 100644 --- a/test/a64/traces/sim-frintn-4s-trace-a64.h +++ b/test/a64/traces/sim-frintn-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintn-d-trace-a64.h b/test/a64/traces/sim-frintn-d-trace-a64.h index 597fb3c5..5d7d532f 100644 --- a/test/a64/traces/sim-frintn-d-trace-a64.h +++ b/test/a64/traces/sim-frintn-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintn-s-trace-a64.h b/test/a64/traces/sim-frintn-s-trace-a64.h index 7ec7cf82..0a3f41f2 100644 --- a/test/a64/traces/sim-frintn-s-trace-a64.h +++ b/test/a64/traces/sim-frintn-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintp-2d-trace-a64.h b/test/a64/traces/sim-frintp-2d-trace-a64.h index 51e00f78..d669ebd3 100644 --- a/test/a64/traces/sim-frintp-2d-trace-a64.h +++ b/test/a64/traces/sim-frintp-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintp-2s-trace-a64.h b/test/a64/traces/sim-frintp-2s-trace-a64.h index a2140b5d..693a8554 100644 --- a/test/a64/traces/sim-frintp-2s-trace-a64.h +++ b/test/a64/traces/sim-frintp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintp-4s-trace-a64.h b/test/a64/traces/sim-frintp-4s-trace-a64.h index 2d5376fb..28ad4b98 100644 --- a/test/a64/traces/sim-frintp-4s-trace-a64.h +++ b/test/a64/traces/sim-frintp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintp-d-trace-a64.h b/test/a64/traces/sim-frintp-d-trace-a64.h index 98f05676..6dde8836 100644 --- a/test/a64/traces/sim-frintp-d-trace-a64.h +++ b/test/a64/traces/sim-frintp-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintp-s-trace-a64.h b/test/a64/traces/sim-frintp-s-trace-a64.h index 35bfe6fc..393080ba 100644 --- a/test/a64/traces/sim-frintp-s-trace-a64.h +++ b/test/a64/traces/sim-frintp-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintx-2d-trace-a64.h b/test/a64/traces/sim-frintx-2d-trace-a64.h index 8e2e3138..813a002e 100644 --- a/test/a64/traces/sim-frintx-2d-trace-a64.h +++ b/test/a64/traces/sim-frintx-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintx-2s-trace-a64.h b/test/a64/traces/sim-frintx-2s-trace-a64.h index 1d0b6863..3c5190ec 100644 --- a/test/a64/traces/sim-frintx-2s-trace-a64.h +++ b/test/a64/traces/sim-frintx-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintx-4s-trace-a64.h b/test/a64/traces/sim-frintx-4s-trace-a64.h index 49a5c518..c26fb61b 100644 --- a/test/a64/traces/sim-frintx-4s-trace-a64.h +++ b/test/a64/traces/sim-frintx-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintx-d-trace-a64.h b/test/a64/traces/sim-frintx-d-trace-a64.h index b07b2643..b8aef2c9 100644 --- a/test/a64/traces/sim-frintx-d-trace-a64.h +++ b/test/a64/traces/sim-frintx-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintx-s-trace-a64.h b/test/a64/traces/sim-frintx-s-trace-a64.h index 1c8f4f3e..8c2f976d 100644 --- a/test/a64/traces/sim-frintx-s-trace-a64.h +++ b/test/a64/traces/sim-frintx-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintz-2d-trace-a64.h b/test/a64/traces/sim-frintz-2d-trace-a64.h index f84a844f..f1d9df6c 100644 --- a/test/a64/traces/sim-frintz-2d-trace-a64.h +++ b/test/a64/traces/sim-frintz-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintz-2s-trace-a64.h b/test/a64/traces/sim-frintz-2s-trace-a64.h index e49651ad..9dd1709a 100644 --- a/test/a64/traces/sim-frintz-2s-trace-a64.h +++ b/test/a64/traces/sim-frintz-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintz-4s-trace-a64.h b/test/a64/traces/sim-frintz-4s-trace-a64.h index 16896315..17178320 100644 --- a/test/a64/traces/sim-frintz-4s-trace-a64.h +++ b/test/a64/traces/sim-frintz-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintz-d-trace-a64.h b/test/a64/traces/sim-frintz-d-trace-a64.h index e3d939a1..d35fc440 100644 --- a/test/a64/traces/sim-frintz-d-trace-a64.h +++ b/test/a64/traces/sim-frintz-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frintz-s-trace-a64.h b/test/a64/traces/sim-frintz-s-trace-a64.h index d00b77d3..b8c049b5 100644 --- a/test/a64/traces/sim-frintz-s-trace-a64.h +++ b/test/a64/traces/sim-frintz-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frsqrte-2d-trace-a64.h b/test/a64/traces/sim-frsqrte-2d-trace-a64.h index 2f7a55ff..2007cfb3 100644 --- a/test/a64/traces/sim-frsqrte-2d-trace-a64.h +++ b/test/a64/traces/sim-frsqrte-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frsqrte-2s-trace-a64.h b/test/a64/traces/sim-frsqrte-2s-trace-a64.h index 8b764f55..da40a84c 100644 --- a/test/a64/traces/sim-frsqrte-2s-trace-a64.h +++ b/test/a64/traces/sim-frsqrte-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frsqrte-4s-trace-a64.h b/test/a64/traces/sim-frsqrte-4s-trace-a64.h index 97d345db..9d95d101 100644 --- a/test/a64/traces/sim-frsqrte-4s-trace-a64.h +++ b/test/a64/traces/sim-frsqrte-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frsqrte-d-trace-a64.h b/test/a64/traces/sim-frsqrte-d-trace-a64.h index 85e83627..afdbb303 100644 --- a/test/a64/traces/sim-frsqrte-d-trace-a64.h +++ b/test/a64/traces/sim-frsqrte-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frsqrte-s-trace-a64.h b/test/a64/traces/sim-frsqrte-s-trace-a64.h index 067bac0c..22e46099 100644 --- a/test/a64/traces/sim-frsqrte-s-trace-a64.h +++ b/test/a64/traces/sim-frsqrte-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frsqrts-2d-trace-a64.h b/test/a64/traces/sim-frsqrts-2d-trace-a64.h index d90f1d35..fd97991a 100644 --- a/test/a64/traces/sim-frsqrts-2d-trace-a64.h +++ b/test/a64/traces/sim-frsqrts-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frsqrts-2s-trace-a64.h b/test/a64/traces/sim-frsqrts-2s-trace-a64.h index 5f703c4f..aae3987d 100644 --- a/test/a64/traces/sim-frsqrts-2s-trace-a64.h +++ b/test/a64/traces/sim-frsqrts-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frsqrts-4s-trace-a64.h b/test/a64/traces/sim-frsqrts-4s-trace-a64.h index 04814073..cc2a5a35 100644 --- a/test/a64/traces/sim-frsqrts-4s-trace-a64.h +++ b/test/a64/traces/sim-frsqrts-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frsqrts-d-trace-a64.h b/test/a64/traces/sim-frsqrts-d-trace-a64.h index 9fa4a747..bddbd3f7 100644 --- a/test/a64/traces/sim-frsqrts-d-trace-a64.h +++ b/test/a64/traces/sim-frsqrts-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-frsqrts-s-trace-a64.h b/test/a64/traces/sim-frsqrts-s-trace-a64.h index 64bf1918..55c420c7 100644 --- a/test/a64/traces/sim-frsqrts-s-trace-a64.h +++ b/test/a64/traces/sim-frsqrts-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fsqrt-2d-trace-a64.h b/test/a64/traces/sim-fsqrt-2d-trace-a64.h index f442ca9a..47812309 100644 --- a/test/a64/traces/sim-fsqrt-2d-trace-a64.h +++ b/test/a64/traces/sim-fsqrt-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fsqrt-2s-trace-a64.h b/test/a64/traces/sim-fsqrt-2s-trace-a64.h index 2c3f278b..aaee8eaf 100644 --- a/test/a64/traces/sim-fsqrt-2s-trace-a64.h +++ b/test/a64/traces/sim-fsqrt-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fsqrt-4s-trace-a64.h b/test/a64/traces/sim-fsqrt-4s-trace-a64.h index 9d4486c0..3515c8a8 100644 --- a/test/a64/traces/sim-fsqrt-4s-trace-a64.h +++ b/test/a64/traces/sim-fsqrt-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fsqrt-d-trace-a64.h b/test/a64/traces/sim-fsqrt-d-trace-a64.h index 4eb9af44..df43b00e 100644 --- a/test/a64/traces/sim-fsqrt-d-trace-a64.h +++ b/test/a64/traces/sim-fsqrt-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fsqrt-s-trace-a64.h b/test/a64/traces/sim-fsqrt-s-trace-a64.h index 561ca770..16195df2 100644 --- a/test/a64/traces/sim-fsqrt-s-trace-a64.h +++ b/test/a64/traces/sim-fsqrt-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fsub-2d-trace-a64.h b/test/a64/traces/sim-fsub-2d-trace-a64.h index 5982c5a6..8dbdf34e 100644 --- a/test/a64/traces/sim-fsub-2d-trace-a64.h +++ b/test/a64/traces/sim-fsub-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fsub-2s-trace-a64.h b/test/a64/traces/sim-fsub-2s-trace-a64.h index d1ae7b09..e8e9d2d7 100644 --- a/test/a64/traces/sim-fsub-2s-trace-a64.h +++ b/test/a64/traces/sim-fsub-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fsub-4s-trace-a64.h b/test/a64/traces/sim-fsub-4s-trace-a64.h index ab7a53a2..dde39428 100644 --- a/test/a64/traces/sim-fsub-4s-trace-a64.h +++ b/test/a64/traces/sim-fsub-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fsub-d-trace-a64.h b/test/a64/traces/sim-fsub-d-trace-a64.h index 6c84a3f9..f1ae7699 100644 --- a/test/a64/traces/sim-fsub-d-trace-a64.h +++ b/test/a64/traces/sim-fsub-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-fsub-s-trace-a64.h b/test/a64/traces/sim-fsub-s-trace-a64.h index 1029a0ca..d6c98f5e 100644 --- a/test/a64/traces/sim-fsub-s-trace-a64.h +++ b/test/a64/traces/sim-fsub-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ins-b-trace-a64.h b/test/a64/traces/sim-ins-b-trace-a64.h index 6232d6a6..8cb66b45 100644 --- a/test/a64/traces/sim-ins-b-trace-a64.h +++ b/test/a64/traces/sim-ins-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ins-d-trace-a64.h b/test/a64/traces/sim-ins-d-trace-a64.h index 91c54f02..78f4dfc2 100644 --- a/test/a64/traces/sim-ins-d-trace-a64.h +++ b/test/a64/traces/sim-ins-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ins-h-trace-a64.h b/test/a64/traces/sim-ins-h-trace-a64.h index 0ec1dd59..84c8a5d5 100644 --- a/test/a64/traces/sim-ins-h-trace-a64.h +++ b/test/a64/traces/sim-ins-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ins-s-trace-a64.h b/test/a64/traces/sim-ins-s-trace-a64.h index 7057eaa5..5fc3db74 100644 --- a/test/a64/traces/sim-ins-s-trace-a64.h +++ b/test/a64/traces/sim-ins-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mla-16b-trace-a64.h b/test/a64/traces/sim-mla-16b-trace-a64.h index 739fa8a9..13edeec3 100644 --- a/test/a64/traces/sim-mla-16b-trace-a64.h +++ b/test/a64/traces/sim-mla-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mla-2s-2s-s-trace-a64.h b/test/a64/traces/sim-mla-2s-2s-s-trace-a64.h index 6088487f..ccc72503 100644 --- a/test/a64/traces/sim-mla-2s-2s-s-trace-a64.h +++ b/test/a64/traces/sim-mla-2s-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mla-2s-trace-a64.h b/test/a64/traces/sim-mla-2s-trace-a64.h index 83d786c3..39b1ff65 100644 --- a/test/a64/traces/sim-mla-2s-trace-a64.h +++ b/test/a64/traces/sim-mla-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mla-4h-4h-h-trace-a64.h b/test/a64/traces/sim-mla-4h-4h-h-trace-a64.h index fcfe5025..0fc31bca 100644 --- a/test/a64/traces/sim-mla-4h-4h-h-trace-a64.h +++ b/test/a64/traces/sim-mla-4h-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mla-4h-trace-a64.h b/test/a64/traces/sim-mla-4h-trace-a64.h index 0f32e20b..cc9b984c 100644 --- a/test/a64/traces/sim-mla-4h-trace-a64.h +++ b/test/a64/traces/sim-mla-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mla-4s-4s-s-trace-a64.h b/test/a64/traces/sim-mla-4s-4s-s-trace-a64.h index 1b67c363..cee1f7d2 100644 --- a/test/a64/traces/sim-mla-4s-4s-s-trace-a64.h +++ b/test/a64/traces/sim-mla-4s-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mla-4s-trace-a64.h b/test/a64/traces/sim-mla-4s-trace-a64.h index 85d24e95..6cd44a45 100644 --- a/test/a64/traces/sim-mla-4s-trace-a64.h +++ b/test/a64/traces/sim-mla-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mla-8b-trace-a64.h b/test/a64/traces/sim-mla-8b-trace-a64.h index c67cfa76..28e34eda 100644 --- a/test/a64/traces/sim-mla-8b-trace-a64.h +++ b/test/a64/traces/sim-mla-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mla-8h-8h-h-trace-a64.h b/test/a64/traces/sim-mla-8h-8h-h-trace-a64.h index 9cf9af5a..8a627411 100644 --- a/test/a64/traces/sim-mla-8h-8h-h-trace-a64.h +++ b/test/a64/traces/sim-mla-8h-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mla-8h-trace-a64.h b/test/a64/traces/sim-mla-8h-trace-a64.h index fe480919..25ef0542 100644 --- a/test/a64/traces/sim-mla-8h-trace-a64.h +++ b/test/a64/traces/sim-mla-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mls-16b-trace-a64.h b/test/a64/traces/sim-mls-16b-trace-a64.h index ca5ba782..a82c82ca 100644 --- a/test/a64/traces/sim-mls-16b-trace-a64.h +++ b/test/a64/traces/sim-mls-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mls-2s-2s-s-trace-a64.h b/test/a64/traces/sim-mls-2s-2s-s-trace-a64.h index 18e2bc7c..e1489243 100644 --- a/test/a64/traces/sim-mls-2s-2s-s-trace-a64.h +++ b/test/a64/traces/sim-mls-2s-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mls-2s-trace-a64.h b/test/a64/traces/sim-mls-2s-trace-a64.h index 9400b037..59d7bae2 100644 --- a/test/a64/traces/sim-mls-2s-trace-a64.h +++ b/test/a64/traces/sim-mls-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mls-4h-4h-h-trace-a64.h b/test/a64/traces/sim-mls-4h-4h-h-trace-a64.h index 0707a090..15c707e1 100644 --- a/test/a64/traces/sim-mls-4h-4h-h-trace-a64.h +++ b/test/a64/traces/sim-mls-4h-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mls-4h-trace-a64.h b/test/a64/traces/sim-mls-4h-trace-a64.h index db4d0b1a..16cc6098 100644 --- a/test/a64/traces/sim-mls-4h-trace-a64.h +++ b/test/a64/traces/sim-mls-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mls-4s-4s-s-trace-a64.h b/test/a64/traces/sim-mls-4s-4s-s-trace-a64.h index 71099185..9e4f104b 100644 --- a/test/a64/traces/sim-mls-4s-4s-s-trace-a64.h +++ b/test/a64/traces/sim-mls-4s-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mls-4s-trace-a64.h b/test/a64/traces/sim-mls-4s-trace-a64.h index 97cc5705..dc9cb451 100644 --- a/test/a64/traces/sim-mls-4s-trace-a64.h +++ b/test/a64/traces/sim-mls-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mls-8b-trace-a64.h b/test/a64/traces/sim-mls-8b-trace-a64.h index 6f6a2e02..96662abb 100644 --- a/test/a64/traces/sim-mls-8b-trace-a64.h +++ b/test/a64/traces/sim-mls-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mls-8h-8h-h-trace-a64.h b/test/a64/traces/sim-mls-8h-8h-h-trace-a64.h index 8e3175d0..2b8b7ab8 100644 --- a/test/a64/traces/sim-mls-8h-8h-h-trace-a64.h +++ b/test/a64/traces/sim-mls-8h-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mls-8h-trace-a64.h b/test/a64/traces/sim-mls-8h-trace-a64.h index ca4d32f5..3fbc7a06 100644 --- a/test/a64/traces/sim-mls-8h-trace-a64.h +++ b/test/a64/traces/sim-mls-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mul-16b-trace-a64.h b/test/a64/traces/sim-mul-16b-trace-a64.h index 3f32e22f..cf1fdd12 100644 --- a/test/a64/traces/sim-mul-16b-trace-a64.h +++ b/test/a64/traces/sim-mul-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mul-2s-2s-s-trace-a64.h b/test/a64/traces/sim-mul-2s-2s-s-trace-a64.h index 6dd81ef4..cd463d13 100644 --- a/test/a64/traces/sim-mul-2s-2s-s-trace-a64.h +++ b/test/a64/traces/sim-mul-2s-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mul-2s-trace-a64.h b/test/a64/traces/sim-mul-2s-trace-a64.h index 35e051c4..60cd330a 100644 --- a/test/a64/traces/sim-mul-2s-trace-a64.h +++ b/test/a64/traces/sim-mul-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mul-4h-4h-h-trace-a64.h b/test/a64/traces/sim-mul-4h-4h-h-trace-a64.h index bb381271..be00e969 100644 --- a/test/a64/traces/sim-mul-4h-4h-h-trace-a64.h +++ b/test/a64/traces/sim-mul-4h-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mul-4h-trace-a64.h b/test/a64/traces/sim-mul-4h-trace-a64.h index e041eddb..ef917e4d 100644 --- a/test/a64/traces/sim-mul-4h-trace-a64.h +++ b/test/a64/traces/sim-mul-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mul-4s-4s-s-trace-a64.h b/test/a64/traces/sim-mul-4s-4s-s-trace-a64.h index e772eef5..8159edd1 100644 --- a/test/a64/traces/sim-mul-4s-4s-s-trace-a64.h +++ b/test/a64/traces/sim-mul-4s-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mul-4s-trace-a64.h b/test/a64/traces/sim-mul-4s-trace-a64.h index 97fd28eb..60a04b02 100644 --- a/test/a64/traces/sim-mul-4s-trace-a64.h +++ b/test/a64/traces/sim-mul-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mul-8b-trace-a64.h b/test/a64/traces/sim-mul-8b-trace-a64.h index b9aa2b11..6ac05521 100644 --- a/test/a64/traces/sim-mul-8b-trace-a64.h +++ b/test/a64/traces/sim-mul-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mul-8h-8h-h-trace-a64.h b/test/a64/traces/sim-mul-8h-8h-h-trace-a64.h index 04aa4b58..d7d8a8b7 100644 --- a/test/a64/traces/sim-mul-8h-8h-h-trace-a64.h +++ b/test/a64/traces/sim-mul-8h-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-mul-8h-trace-a64.h b/test/a64/traces/sim-mul-8h-trace-a64.h index cbb0f56d..481b683e 100644 --- a/test/a64/traces/sim-mul-8h-trace-a64.h +++ b/test/a64/traces/sim-mul-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-neg-16b-trace-a64.h b/test/a64/traces/sim-neg-16b-trace-a64.h index eabf8466..2e62f45c 100644 --- a/test/a64/traces/sim-neg-16b-trace-a64.h +++ b/test/a64/traces/sim-neg-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-neg-2d-trace-a64.h b/test/a64/traces/sim-neg-2d-trace-a64.h index 201899d3..1da60430 100644 --- a/test/a64/traces/sim-neg-2d-trace-a64.h +++ b/test/a64/traces/sim-neg-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-neg-2s-trace-a64.h b/test/a64/traces/sim-neg-2s-trace-a64.h index f90a8e9a..9168acc9 100644 --- a/test/a64/traces/sim-neg-2s-trace-a64.h +++ b/test/a64/traces/sim-neg-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-neg-4h-trace-a64.h b/test/a64/traces/sim-neg-4h-trace-a64.h index 1b4ffb13..222f7de1 100644 --- a/test/a64/traces/sim-neg-4h-trace-a64.h +++ b/test/a64/traces/sim-neg-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-neg-4s-trace-a64.h b/test/a64/traces/sim-neg-4s-trace-a64.h index b7384c22..e6c04135 100644 --- a/test/a64/traces/sim-neg-4s-trace-a64.h +++ b/test/a64/traces/sim-neg-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-neg-8b-trace-a64.h b/test/a64/traces/sim-neg-8b-trace-a64.h index 54683c4f..e77c30c0 100644 --- a/test/a64/traces/sim-neg-8b-trace-a64.h +++ b/test/a64/traces/sim-neg-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-neg-8h-trace-a64.h b/test/a64/traces/sim-neg-8h-trace-a64.h index 67e93a39..1ed65683 100644 --- a/test/a64/traces/sim-neg-8h-trace-a64.h +++ b/test/a64/traces/sim-neg-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-neg-d-trace-a64.h b/test/a64/traces/sim-neg-d-trace-a64.h index a7b2c7d7..6b72d490 100644 --- a/test/a64/traces/sim-neg-d-trace-a64.h +++ b/test/a64/traces/sim-neg-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-not--16b-trace-a64.h b/test/a64/traces/sim-not--16b-trace-a64.h index b85ab90a..e1c3965b 100644 --- a/test/a64/traces/sim-not--16b-trace-a64.h +++ b/test/a64/traces/sim-not--16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-not--8b-trace-a64.h b/test/a64/traces/sim-not--8b-trace-a64.h index 2aa69777..5b49a009 100644 --- a/test/a64/traces/sim-not--8b-trace-a64.h +++ b/test/a64/traces/sim-not--8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-orn-16b-trace-a64.h b/test/a64/traces/sim-orn-16b-trace-a64.h index 4ba6425b..8b4b8052 100644 --- a/test/a64/traces/sim-orn-16b-trace-a64.h +++ b/test/a64/traces/sim-orn-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-orn-8b-trace-a64.h b/test/a64/traces/sim-orn-8b-trace-a64.h index c4e9d416..c5d79210 100644 --- a/test/a64/traces/sim-orn-8b-trace-a64.h +++ b/test/a64/traces/sim-orn-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-orr-16b-trace-a64.h b/test/a64/traces/sim-orr-16b-trace-a64.h index 8771145d..0a2ae627 100644 --- a/test/a64/traces/sim-orr-16b-trace-a64.h +++ b/test/a64/traces/sim-orr-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-orr-8b-trace-a64.h b/test/a64/traces/sim-orr-8b-trace-a64.h index 7f6d349f..22b5386f 100644 --- a/test/a64/traces/sim-orr-8b-trace-a64.h +++ b/test/a64/traces/sim-orr-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-pmul-16b-trace-a64.h b/test/a64/traces/sim-pmul-16b-trace-a64.h index 1092c5c2..5c535348 100644 --- a/test/a64/traces/sim-pmul-16b-trace-a64.h +++ b/test/a64/traces/sim-pmul-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-pmul-8b-trace-a64.h b/test/a64/traces/sim-pmul-8b-trace-a64.h index 7fa9a19f..b96c3d19 100644 --- a/test/a64/traces/sim-pmul-8b-trace-a64.h +++ b/test/a64/traces/sim-pmul-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-pmull-8h-trace-a64.h b/test/a64/traces/sim-pmull-8h-trace-a64.h index 243cf861..c45e7205 100644 --- a/test/a64/traces/sim-pmull-8h-trace-a64.h +++ b/test/a64/traces/sim-pmull-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-pmull2-8h-trace-a64.h b/test/a64/traces/sim-pmull2-8h-trace-a64.h index 57a2d62e..b022ca3e 100644 --- a/test/a64/traces/sim-pmull2-8h-trace-a64.h +++ b/test/a64/traces/sim-pmull2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-raddhn-2s-trace-a64.h b/test/a64/traces/sim-raddhn-2s-trace-a64.h index fc75c34c..8c4e3e68 100644 --- a/test/a64/traces/sim-raddhn-2s-trace-a64.h +++ b/test/a64/traces/sim-raddhn-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-raddhn-4h-trace-a64.h b/test/a64/traces/sim-raddhn-4h-trace-a64.h index d5dde137..9554ca4e 100644 --- a/test/a64/traces/sim-raddhn-4h-trace-a64.h +++ b/test/a64/traces/sim-raddhn-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-raddhn-8b-trace-a64.h b/test/a64/traces/sim-raddhn-8b-trace-a64.h index 283fc296..5d383e7f 100644 --- a/test/a64/traces/sim-raddhn-8b-trace-a64.h +++ b/test/a64/traces/sim-raddhn-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-raddhn2-16b-trace-a64.h b/test/a64/traces/sim-raddhn2-16b-trace-a64.h index 7f209d11..6e6d005d 100644 --- a/test/a64/traces/sim-raddhn2-16b-trace-a64.h +++ b/test/a64/traces/sim-raddhn2-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-raddhn2-4s-trace-a64.h b/test/a64/traces/sim-raddhn2-4s-trace-a64.h index d33d9d72..0675231b 100644 --- a/test/a64/traces/sim-raddhn2-4s-trace-a64.h +++ b/test/a64/traces/sim-raddhn2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-raddhn2-8h-trace-a64.h b/test/a64/traces/sim-raddhn2-8h-trace-a64.h index bb2114c1..1068411c 100644 --- a/test/a64/traces/sim-raddhn2-8h-trace-a64.h +++ b/test/a64/traces/sim-raddhn2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rbit-16b-trace-a64.h b/test/a64/traces/sim-rbit-16b-trace-a64.h index 88a3601d..ddc40d89 100644 --- a/test/a64/traces/sim-rbit-16b-trace-a64.h +++ b/test/a64/traces/sim-rbit-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rbit-8b-trace-a64.h b/test/a64/traces/sim-rbit-8b-trace-a64.h index f757c994..3570dddb 100644 --- a/test/a64/traces/sim-rbit-8b-trace-a64.h +++ b/test/a64/traces/sim-rbit-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rev16-16b-trace-a64.h b/test/a64/traces/sim-rev16-16b-trace-a64.h index 2cbc4645..788251c9 100644 --- a/test/a64/traces/sim-rev16-16b-trace-a64.h +++ b/test/a64/traces/sim-rev16-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rev16-8b-trace-a64.h b/test/a64/traces/sim-rev16-8b-trace-a64.h index d915d54e..8d2f6af4 100644 --- a/test/a64/traces/sim-rev16-8b-trace-a64.h +++ b/test/a64/traces/sim-rev16-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rev32-16b-trace-a64.h b/test/a64/traces/sim-rev32-16b-trace-a64.h index 913f38f0..dc35d774 100644 --- a/test/a64/traces/sim-rev32-16b-trace-a64.h +++ b/test/a64/traces/sim-rev32-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rev32-4h-trace-a64.h b/test/a64/traces/sim-rev32-4h-trace-a64.h index 43e283b6..59a1bcda 100644 --- a/test/a64/traces/sim-rev32-4h-trace-a64.h +++ b/test/a64/traces/sim-rev32-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rev32-8b-trace-a64.h b/test/a64/traces/sim-rev32-8b-trace-a64.h index 3b0affca..5f0cd06f 100644 --- a/test/a64/traces/sim-rev32-8b-trace-a64.h +++ b/test/a64/traces/sim-rev32-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rev32-8h-trace-a64.h b/test/a64/traces/sim-rev32-8h-trace-a64.h index 53d8929f..df7cea93 100644 --- a/test/a64/traces/sim-rev32-8h-trace-a64.h +++ b/test/a64/traces/sim-rev32-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rev64-16b-trace-a64.h b/test/a64/traces/sim-rev64-16b-trace-a64.h index 6a29b4cc..4fa8ca51 100644 --- a/test/a64/traces/sim-rev64-16b-trace-a64.h +++ b/test/a64/traces/sim-rev64-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rev64-2s-trace-a64.h b/test/a64/traces/sim-rev64-2s-trace-a64.h index a1ab4962..0f2e6c36 100644 --- a/test/a64/traces/sim-rev64-2s-trace-a64.h +++ b/test/a64/traces/sim-rev64-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rev64-4h-trace-a64.h b/test/a64/traces/sim-rev64-4h-trace-a64.h index 44831946..54f6cced 100644 --- a/test/a64/traces/sim-rev64-4h-trace-a64.h +++ b/test/a64/traces/sim-rev64-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rev64-4s-trace-a64.h b/test/a64/traces/sim-rev64-4s-trace-a64.h index 67163723..6d859f0a 100644 --- a/test/a64/traces/sim-rev64-4s-trace-a64.h +++ b/test/a64/traces/sim-rev64-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rev64-8b-trace-a64.h b/test/a64/traces/sim-rev64-8b-trace-a64.h index cdc1b626..5ca8aeae 100644 --- a/test/a64/traces/sim-rev64-8b-trace-a64.h +++ b/test/a64/traces/sim-rev64-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rev64-8h-trace-a64.h b/test/a64/traces/sim-rev64-8h-trace-a64.h index a079523d..aa8a0237 100644 --- a/test/a64/traces/sim-rev64-8h-trace-a64.h +++ b/test/a64/traces/sim-rev64-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rshrn-2s-2opimm-trace-a64.h b/test/a64/traces/sim-rshrn-2s-2opimm-trace-a64.h index 786a30b1..0183a1d2 100644 --- a/test/a64/traces/sim-rshrn-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-rshrn-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rshrn-4h-2opimm-trace-a64.h b/test/a64/traces/sim-rshrn-4h-2opimm-trace-a64.h index 9dbbacac..a753e966 100644 --- a/test/a64/traces/sim-rshrn-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-rshrn-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rshrn-8b-2opimm-trace-a64.h b/test/a64/traces/sim-rshrn-8b-2opimm-trace-a64.h index 7d0de817..db3b101c 100644 --- a/test/a64/traces/sim-rshrn-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-rshrn-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rshrn2-16b-2opimm-trace-a64.h b/test/a64/traces/sim-rshrn2-16b-2opimm-trace-a64.h index b8370723..b0784e22 100644 --- a/test/a64/traces/sim-rshrn2-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-rshrn2-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rshrn2-4s-2opimm-trace-a64.h b/test/a64/traces/sim-rshrn2-4s-2opimm-trace-a64.h index a1dc00dc..c5da5148 100644 --- a/test/a64/traces/sim-rshrn2-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-rshrn2-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rshrn2-8h-2opimm-trace-a64.h b/test/a64/traces/sim-rshrn2-8h-2opimm-trace-a64.h index d398c516..783c7724 100644 --- a/test/a64/traces/sim-rshrn2-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-rshrn2-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rsubhn-2s-trace-a64.h b/test/a64/traces/sim-rsubhn-2s-trace-a64.h index 59bea78f..7307f2dd 100644 --- a/test/a64/traces/sim-rsubhn-2s-trace-a64.h +++ b/test/a64/traces/sim-rsubhn-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rsubhn-4h-trace-a64.h b/test/a64/traces/sim-rsubhn-4h-trace-a64.h index cf4f1997..24b2ca35 100644 --- a/test/a64/traces/sim-rsubhn-4h-trace-a64.h +++ b/test/a64/traces/sim-rsubhn-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rsubhn-8b-trace-a64.h b/test/a64/traces/sim-rsubhn-8b-trace-a64.h index 2d17e9cc..08f3ce31 100644 --- a/test/a64/traces/sim-rsubhn-8b-trace-a64.h +++ b/test/a64/traces/sim-rsubhn-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rsubhn2-16b-trace-a64.h b/test/a64/traces/sim-rsubhn2-16b-trace-a64.h index 98360f33..9d5b76ed 100644 --- a/test/a64/traces/sim-rsubhn2-16b-trace-a64.h +++ b/test/a64/traces/sim-rsubhn2-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rsubhn2-4s-trace-a64.h b/test/a64/traces/sim-rsubhn2-4s-trace-a64.h index f7b83e75..e86bf240 100644 --- a/test/a64/traces/sim-rsubhn2-4s-trace-a64.h +++ b/test/a64/traces/sim-rsubhn2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-rsubhn2-8h-trace-a64.h b/test/a64/traces/sim-rsubhn2-8h-trace-a64.h index 490c3131..b7f07fda 100644 --- a/test/a64/traces/sim-rsubhn2-8h-trace-a64.h +++ b/test/a64/traces/sim-rsubhn2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saba-16b-trace-a64.h b/test/a64/traces/sim-saba-16b-trace-a64.h index 61b230c0..a95dea83 100644 --- a/test/a64/traces/sim-saba-16b-trace-a64.h +++ b/test/a64/traces/sim-saba-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saba-2s-trace-a64.h b/test/a64/traces/sim-saba-2s-trace-a64.h index 5d456556..e899163c 100644 --- a/test/a64/traces/sim-saba-2s-trace-a64.h +++ b/test/a64/traces/sim-saba-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saba-4h-trace-a64.h b/test/a64/traces/sim-saba-4h-trace-a64.h index bfea4266..851b8bac 100644 --- a/test/a64/traces/sim-saba-4h-trace-a64.h +++ b/test/a64/traces/sim-saba-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saba-4s-trace-a64.h b/test/a64/traces/sim-saba-4s-trace-a64.h index 7490dd5a..8937d686 100644 --- a/test/a64/traces/sim-saba-4s-trace-a64.h +++ b/test/a64/traces/sim-saba-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saba-8b-trace-a64.h b/test/a64/traces/sim-saba-8b-trace-a64.h index e2848ddf..b4d2af18 100644 --- a/test/a64/traces/sim-saba-8b-trace-a64.h +++ b/test/a64/traces/sim-saba-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saba-8h-trace-a64.h b/test/a64/traces/sim-saba-8h-trace-a64.h index a5843df6..0f9080b4 100644 --- a/test/a64/traces/sim-saba-8h-trace-a64.h +++ b/test/a64/traces/sim-saba-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabal-2d-trace-a64.h b/test/a64/traces/sim-sabal-2d-trace-a64.h index c3a18a99..1fca3dba 100644 --- a/test/a64/traces/sim-sabal-2d-trace-a64.h +++ b/test/a64/traces/sim-sabal-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabal-4s-trace-a64.h b/test/a64/traces/sim-sabal-4s-trace-a64.h index 456f5736..c66b1c59 100644 --- a/test/a64/traces/sim-sabal-4s-trace-a64.h +++ b/test/a64/traces/sim-sabal-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabal-8h-trace-a64.h b/test/a64/traces/sim-sabal-8h-trace-a64.h index 307bb0cf..37861377 100644 --- a/test/a64/traces/sim-sabal-8h-trace-a64.h +++ b/test/a64/traces/sim-sabal-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabal2-2d-trace-a64.h b/test/a64/traces/sim-sabal2-2d-trace-a64.h index ce69974f..256cf33f 100644 --- a/test/a64/traces/sim-sabal2-2d-trace-a64.h +++ b/test/a64/traces/sim-sabal2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabal2-4s-trace-a64.h b/test/a64/traces/sim-sabal2-4s-trace-a64.h index 9336414c..8d7c03b4 100644 --- a/test/a64/traces/sim-sabal2-4s-trace-a64.h +++ b/test/a64/traces/sim-sabal2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabal2-8h-trace-a64.h b/test/a64/traces/sim-sabal2-8h-trace-a64.h index b9c3b467..c220f62e 100644 --- a/test/a64/traces/sim-sabal2-8h-trace-a64.h +++ b/test/a64/traces/sim-sabal2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabd-16b-trace-a64.h b/test/a64/traces/sim-sabd-16b-trace-a64.h index 58cb43e2..27b3c353 100644 --- a/test/a64/traces/sim-sabd-16b-trace-a64.h +++ b/test/a64/traces/sim-sabd-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabd-2s-trace-a64.h b/test/a64/traces/sim-sabd-2s-trace-a64.h index f4a6aa78..29d6aec3 100644 --- a/test/a64/traces/sim-sabd-2s-trace-a64.h +++ b/test/a64/traces/sim-sabd-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabd-4h-trace-a64.h b/test/a64/traces/sim-sabd-4h-trace-a64.h index 621f4b64..ec29a7d8 100644 --- a/test/a64/traces/sim-sabd-4h-trace-a64.h +++ b/test/a64/traces/sim-sabd-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabd-4s-trace-a64.h b/test/a64/traces/sim-sabd-4s-trace-a64.h index 565587a3..3b1407fb 100644 --- a/test/a64/traces/sim-sabd-4s-trace-a64.h +++ b/test/a64/traces/sim-sabd-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabd-8b-trace-a64.h b/test/a64/traces/sim-sabd-8b-trace-a64.h index 19dc4a22..122afd1c 100644 --- a/test/a64/traces/sim-sabd-8b-trace-a64.h +++ b/test/a64/traces/sim-sabd-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabd-8h-trace-a64.h b/test/a64/traces/sim-sabd-8h-trace-a64.h index a42445ac..6612f1ed 100644 --- a/test/a64/traces/sim-sabd-8h-trace-a64.h +++ b/test/a64/traces/sim-sabd-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabdl-2d-trace-a64.h b/test/a64/traces/sim-sabdl-2d-trace-a64.h index 3597ab3b..7703a402 100644 --- a/test/a64/traces/sim-sabdl-2d-trace-a64.h +++ b/test/a64/traces/sim-sabdl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabdl-4s-trace-a64.h b/test/a64/traces/sim-sabdl-4s-trace-a64.h index 6cea86b9..2be19dee 100644 --- a/test/a64/traces/sim-sabdl-4s-trace-a64.h +++ b/test/a64/traces/sim-sabdl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabdl-8h-trace-a64.h b/test/a64/traces/sim-sabdl-8h-trace-a64.h index 324dc57f..6ed521e0 100644 --- a/test/a64/traces/sim-sabdl-8h-trace-a64.h +++ b/test/a64/traces/sim-sabdl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabdl2-2d-trace-a64.h b/test/a64/traces/sim-sabdl2-2d-trace-a64.h index 0094ea30..e7f25be5 100644 --- a/test/a64/traces/sim-sabdl2-2d-trace-a64.h +++ b/test/a64/traces/sim-sabdl2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabdl2-4s-trace-a64.h b/test/a64/traces/sim-sabdl2-4s-trace-a64.h index 029f73f0..ce98c9be 100644 --- a/test/a64/traces/sim-sabdl2-4s-trace-a64.h +++ b/test/a64/traces/sim-sabdl2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sabdl2-8h-trace-a64.h b/test/a64/traces/sim-sabdl2-8h-trace-a64.h index e5e9b89c..8698a4a8 100644 --- a/test/a64/traces/sim-sabdl2-8h-trace-a64.h +++ b/test/a64/traces/sim-sabdl2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sadalp-1d-trace-a64.h b/test/a64/traces/sim-sadalp-1d-trace-a64.h index 47445a9c..50411b29 100644 --- a/test/a64/traces/sim-sadalp-1d-trace-a64.h +++ b/test/a64/traces/sim-sadalp-1d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sadalp-2d-trace-a64.h b/test/a64/traces/sim-sadalp-2d-trace-a64.h index 434038c9..a6f7abab 100644 --- a/test/a64/traces/sim-sadalp-2d-trace-a64.h +++ b/test/a64/traces/sim-sadalp-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sadalp-2s-trace-a64.h b/test/a64/traces/sim-sadalp-2s-trace-a64.h index 3c2f7589..7d5f6f65 100644 --- a/test/a64/traces/sim-sadalp-2s-trace-a64.h +++ b/test/a64/traces/sim-sadalp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sadalp-4h-trace-a64.h b/test/a64/traces/sim-sadalp-4h-trace-a64.h index cc6ae82c..1e73a5c0 100644 --- a/test/a64/traces/sim-sadalp-4h-trace-a64.h +++ b/test/a64/traces/sim-sadalp-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sadalp-4s-trace-a64.h b/test/a64/traces/sim-sadalp-4s-trace-a64.h index 548c4ad8..33281c4f 100644 --- a/test/a64/traces/sim-sadalp-4s-trace-a64.h +++ b/test/a64/traces/sim-sadalp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sadalp-8h-trace-a64.h b/test/a64/traces/sim-sadalp-8h-trace-a64.h index 69233627..791b2e7f 100644 --- a/test/a64/traces/sim-sadalp-8h-trace-a64.h +++ b/test/a64/traces/sim-sadalp-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddl-2d-trace-a64.h b/test/a64/traces/sim-saddl-2d-trace-a64.h index ef9d7ee9..012507d2 100644 --- a/test/a64/traces/sim-saddl-2d-trace-a64.h +++ b/test/a64/traces/sim-saddl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddl-4s-trace-a64.h b/test/a64/traces/sim-saddl-4s-trace-a64.h index 07fa6e9b..0b06f425 100644 --- a/test/a64/traces/sim-saddl-4s-trace-a64.h +++ b/test/a64/traces/sim-saddl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddl-8h-trace-a64.h b/test/a64/traces/sim-saddl-8h-trace-a64.h index b8166937..53d31131 100644 --- a/test/a64/traces/sim-saddl-8h-trace-a64.h +++ b/test/a64/traces/sim-saddl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddl2-2d-trace-a64.h b/test/a64/traces/sim-saddl2-2d-trace-a64.h index 8fd7f6f8..a19cf06a 100644 --- a/test/a64/traces/sim-saddl2-2d-trace-a64.h +++ b/test/a64/traces/sim-saddl2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddl2-4s-trace-a64.h b/test/a64/traces/sim-saddl2-4s-trace-a64.h index 9fb4bf4f..f5a25bc9 100644 --- a/test/a64/traces/sim-saddl2-4s-trace-a64.h +++ b/test/a64/traces/sim-saddl2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddl2-8h-trace-a64.h b/test/a64/traces/sim-saddl2-8h-trace-a64.h index e8be84a4..b79e9878 100644 --- a/test/a64/traces/sim-saddl2-8h-trace-a64.h +++ b/test/a64/traces/sim-saddl2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddlp-1d-trace-a64.h b/test/a64/traces/sim-saddlp-1d-trace-a64.h index f57030ae..adafcab4 100644 --- a/test/a64/traces/sim-saddlp-1d-trace-a64.h +++ b/test/a64/traces/sim-saddlp-1d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddlp-2d-trace-a64.h b/test/a64/traces/sim-saddlp-2d-trace-a64.h index 02575551..0a788b59 100644 --- a/test/a64/traces/sim-saddlp-2d-trace-a64.h +++ b/test/a64/traces/sim-saddlp-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddlp-2s-trace-a64.h b/test/a64/traces/sim-saddlp-2s-trace-a64.h index 8b864a38..9f1d8128 100644 --- a/test/a64/traces/sim-saddlp-2s-trace-a64.h +++ b/test/a64/traces/sim-saddlp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddlp-4h-trace-a64.h b/test/a64/traces/sim-saddlp-4h-trace-a64.h index e56ce81f..cc4936b3 100644 --- a/test/a64/traces/sim-saddlp-4h-trace-a64.h +++ b/test/a64/traces/sim-saddlp-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddlp-4s-trace-a64.h b/test/a64/traces/sim-saddlp-4s-trace-a64.h index ab7820b1..92ff3fab 100644 --- a/test/a64/traces/sim-saddlp-4s-trace-a64.h +++ b/test/a64/traces/sim-saddlp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddlp-8h-trace-a64.h b/test/a64/traces/sim-saddlp-8h-trace-a64.h index 57e44bcd..ed7423fd 100644 --- a/test/a64/traces/sim-saddlp-8h-trace-a64.h +++ b/test/a64/traces/sim-saddlp-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddlv-d-4s-trace-a64.h b/test/a64/traces/sim-saddlv-d-4s-trace-a64.h index 0aa8c06e..e5a73cf8 100644 --- a/test/a64/traces/sim-saddlv-d-4s-trace-a64.h +++ b/test/a64/traces/sim-saddlv-d-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddlv-h-16b-trace-a64.h b/test/a64/traces/sim-saddlv-h-16b-trace-a64.h index 86158892..138efaa1 100644 --- a/test/a64/traces/sim-saddlv-h-16b-trace-a64.h +++ b/test/a64/traces/sim-saddlv-h-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddlv-h-8b-trace-a64.h b/test/a64/traces/sim-saddlv-h-8b-trace-a64.h index ad590ece..72ae7124 100644 --- a/test/a64/traces/sim-saddlv-h-8b-trace-a64.h +++ b/test/a64/traces/sim-saddlv-h-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddlv-s-4h-trace-a64.h b/test/a64/traces/sim-saddlv-s-4h-trace-a64.h index 89449922..d74d6d13 100644 --- a/test/a64/traces/sim-saddlv-s-4h-trace-a64.h +++ b/test/a64/traces/sim-saddlv-s-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddlv-s-8h-trace-a64.h b/test/a64/traces/sim-saddlv-s-8h-trace-a64.h index a34e7ee3..37334f39 100644 --- a/test/a64/traces/sim-saddlv-s-8h-trace-a64.h +++ b/test/a64/traces/sim-saddlv-s-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddw-2d-trace-a64.h b/test/a64/traces/sim-saddw-2d-trace-a64.h index 0bbef07e..1725c5f5 100644 --- a/test/a64/traces/sim-saddw-2d-trace-a64.h +++ b/test/a64/traces/sim-saddw-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddw-4s-trace-a64.h b/test/a64/traces/sim-saddw-4s-trace-a64.h index e4c0abde..884ee924 100644 --- a/test/a64/traces/sim-saddw-4s-trace-a64.h +++ b/test/a64/traces/sim-saddw-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddw-8h-trace-a64.h b/test/a64/traces/sim-saddw-8h-trace-a64.h index c4e352d8..c211bfd3 100644 --- a/test/a64/traces/sim-saddw-8h-trace-a64.h +++ b/test/a64/traces/sim-saddw-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddw2-2d-trace-a64.h b/test/a64/traces/sim-saddw2-2d-trace-a64.h index 998f5d8c..ec3bcf2e 100644 --- a/test/a64/traces/sim-saddw2-2d-trace-a64.h +++ b/test/a64/traces/sim-saddw2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddw2-4s-trace-a64.h b/test/a64/traces/sim-saddw2-4s-trace-a64.h index 553c2cb9..98c73cbb 100644 --- a/test/a64/traces/sim-saddw2-4s-trace-a64.h +++ b/test/a64/traces/sim-saddw2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-saddw2-8h-trace-a64.h b/test/a64/traces/sim-saddw2-8h-trace-a64.h index 38339213..0992046c 100644 --- a/test/a64/traces/sim-saddw2-8h-trace-a64.h +++ b/test/a64/traces/sim-saddw2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-scvtf-2d-2opimm-trace-a64.h b/test/a64/traces/sim-scvtf-2d-2opimm-trace-a64.h index 11c8c581..111230d5 100644 --- a/test/a64/traces/sim-scvtf-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-scvtf-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-scvtf-2s-2opimm-trace-a64.h b/test/a64/traces/sim-scvtf-2s-2opimm-trace-a64.h index 46b29421..0ee80334 100644 --- a/test/a64/traces/sim-scvtf-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-scvtf-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-scvtf-4s-2opimm-trace-a64.h b/test/a64/traces/sim-scvtf-4s-2opimm-trace-a64.h index 16ef9fad..3e109486 100644 --- a/test/a64/traces/sim-scvtf-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-scvtf-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-scvtf-d-2opimm-trace-a64.h b/test/a64/traces/sim-scvtf-d-2opimm-trace-a64.h index 04b6f74e..73ff655d 100644 --- a/test/a64/traces/sim-scvtf-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-scvtf-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-scvtf-s-2opimm-trace-a64.h b/test/a64/traces/sim-scvtf-s-2opimm-trace-a64.h index 5d405f1b..f6a2cf8f 100644 --- a/test/a64/traces/sim-scvtf-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-scvtf-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shadd-16b-trace-a64.h b/test/a64/traces/sim-shadd-16b-trace-a64.h index 7d6b3a22..0cbf5bea 100644 --- a/test/a64/traces/sim-shadd-16b-trace-a64.h +++ b/test/a64/traces/sim-shadd-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shadd-2s-trace-a64.h b/test/a64/traces/sim-shadd-2s-trace-a64.h index 6a2f199e..0bb1b046 100644 --- a/test/a64/traces/sim-shadd-2s-trace-a64.h +++ b/test/a64/traces/sim-shadd-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shadd-4h-trace-a64.h b/test/a64/traces/sim-shadd-4h-trace-a64.h index 26c5c2e2..b72c5b77 100644 --- a/test/a64/traces/sim-shadd-4h-trace-a64.h +++ b/test/a64/traces/sim-shadd-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shadd-4s-trace-a64.h b/test/a64/traces/sim-shadd-4s-trace-a64.h index c53364f2..0871738d 100644 --- a/test/a64/traces/sim-shadd-4s-trace-a64.h +++ b/test/a64/traces/sim-shadd-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shadd-8b-trace-a64.h b/test/a64/traces/sim-shadd-8b-trace-a64.h index cd748d63..dffa2275 100644 --- a/test/a64/traces/sim-shadd-8b-trace-a64.h +++ b/test/a64/traces/sim-shadd-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shadd-8h-trace-a64.h b/test/a64/traces/sim-shadd-8h-trace-a64.h index bf9bedbc..5400a4c7 100644 --- a/test/a64/traces/sim-shadd-8h-trace-a64.h +++ b/test/a64/traces/sim-shadd-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shl-16b-2opimm-trace-a64.h b/test/a64/traces/sim-shl-16b-2opimm-trace-a64.h index b9f33975..d2c484f1 100644 --- a/test/a64/traces/sim-shl-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shl-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shl-2d-2opimm-trace-a64.h b/test/a64/traces/sim-shl-2d-2opimm-trace-a64.h index 2a38cd36..7dfa34e6 100644 --- a/test/a64/traces/sim-shl-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shl-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shl-2s-2opimm-trace-a64.h b/test/a64/traces/sim-shl-2s-2opimm-trace-a64.h index 8eb27313..f9c5577b 100644 --- a/test/a64/traces/sim-shl-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shl-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shl-4h-2opimm-trace-a64.h b/test/a64/traces/sim-shl-4h-2opimm-trace-a64.h index d5e038e2..e691f585 100644 --- a/test/a64/traces/sim-shl-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shl-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shl-4s-2opimm-trace-a64.h b/test/a64/traces/sim-shl-4s-2opimm-trace-a64.h index 8f48f401..eb4448ad 100644 --- a/test/a64/traces/sim-shl-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shl-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shl-8b-2opimm-trace-a64.h b/test/a64/traces/sim-shl-8b-2opimm-trace-a64.h index c5d1e9a7..60eb1122 100644 --- a/test/a64/traces/sim-shl-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shl-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shl-8h-2opimm-trace-a64.h b/test/a64/traces/sim-shl-8h-2opimm-trace-a64.h index c82bd02c..e0dc91d9 100644 --- a/test/a64/traces/sim-shl-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shl-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shl-d-2opimm-trace-a64.h b/test/a64/traces/sim-shl-d-2opimm-trace-a64.h index 326f24de..543d5551 100644 --- a/test/a64/traces/sim-shl-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shl-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shll-2d-2opimm-trace-a64.h b/test/a64/traces/sim-shll-2d-2opimm-trace-a64.h index 4b7d36cb..eff9a160 100644 --- a/test/a64/traces/sim-shll-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shll-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shll-4s-2opimm-trace-a64.h b/test/a64/traces/sim-shll-4s-2opimm-trace-a64.h index e00786cd..6a9dd14e 100644 --- a/test/a64/traces/sim-shll-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shll-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shll-8h-2opimm-trace-a64.h b/test/a64/traces/sim-shll-8h-2opimm-trace-a64.h index 9c8d8a80..8b78bdeb 100644 --- a/test/a64/traces/sim-shll-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shll-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shll2-2d-2opimm-trace-a64.h b/test/a64/traces/sim-shll2-2d-2opimm-trace-a64.h index 0b204a58..79510e84 100644 --- a/test/a64/traces/sim-shll2-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shll2-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shll2-4s-2opimm-trace-a64.h b/test/a64/traces/sim-shll2-4s-2opimm-trace-a64.h index 32401cfe..04880898 100644 --- a/test/a64/traces/sim-shll2-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shll2-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shll2-8h-2opimm-trace-a64.h b/test/a64/traces/sim-shll2-8h-2opimm-trace-a64.h index 06d66c4e..5bb6a789 100644 --- a/test/a64/traces/sim-shll2-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shll2-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shrn-2s-2opimm-trace-a64.h b/test/a64/traces/sim-shrn-2s-2opimm-trace-a64.h index a343f1cc..ecf58eab 100644 --- a/test/a64/traces/sim-shrn-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shrn-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shrn-4h-2opimm-trace-a64.h b/test/a64/traces/sim-shrn-4h-2opimm-trace-a64.h index 64f886a1..c46a8f63 100644 --- a/test/a64/traces/sim-shrn-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shrn-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shrn-8b-2opimm-trace-a64.h b/test/a64/traces/sim-shrn-8b-2opimm-trace-a64.h index 2261852a..5ee61dd0 100644 --- a/test/a64/traces/sim-shrn-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shrn-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shrn2-16b-2opimm-trace-a64.h b/test/a64/traces/sim-shrn2-16b-2opimm-trace-a64.h index 63ad0988..0c829e1b 100644 --- a/test/a64/traces/sim-shrn2-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shrn2-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shrn2-4s-2opimm-trace-a64.h b/test/a64/traces/sim-shrn2-4s-2opimm-trace-a64.h index ea42c85c..73fd53c6 100644 --- a/test/a64/traces/sim-shrn2-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shrn2-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shrn2-8h-2opimm-trace-a64.h b/test/a64/traces/sim-shrn2-8h-2opimm-trace-a64.h index a058bef2..4e761313 100644 --- a/test/a64/traces/sim-shrn2-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-shrn2-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shsub-16b-trace-a64.h b/test/a64/traces/sim-shsub-16b-trace-a64.h index c4fb646b..fe31d0d7 100644 --- a/test/a64/traces/sim-shsub-16b-trace-a64.h +++ b/test/a64/traces/sim-shsub-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shsub-2s-trace-a64.h b/test/a64/traces/sim-shsub-2s-trace-a64.h index d0a1eef7..48da3329 100644 --- a/test/a64/traces/sim-shsub-2s-trace-a64.h +++ b/test/a64/traces/sim-shsub-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shsub-4h-trace-a64.h b/test/a64/traces/sim-shsub-4h-trace-a64.h index d0fc0d83..5bdfc887 100644 --- a/test/a64/traces/sim-shsub-4h-trace-a64.h +++ b/test/a64/traces/sim-shsub-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shsub-4s-trace-a64.h b/test/a64/traces/sim-shsub-4s-trace-a64.h index 2d36c341..ee193451 100644 --- a/test/a64/traces/sim-shsub-4s-trace-a64.h +++ b/test/a64/traces/sim-shsub-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shsub-8b-trace-a64.h b/test/a64/traces/sim-shsub-8b-trace-a64.h index 89c5f9e2..a462280e 100644 --- a/test/a64/traces/sim-shsub-8b-trace-a64.h +++ b/test/a64/traces/sim-shsub-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-shsub-8h-trace-a64.h b/test/a64/traces/sim-shsub-8h-trace-a64.h index f10ae780..00c4051d 100644 --- a/test/a64/traces/sim-shsub-8h-trace-a64.h +++ b/test/a64/traces/sim-shsub-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sli-16b-2opimm-trace-a64.h b/test/a64/traces/sim-sli-16b-2opimm-trace-a64.h index 2e41d49a..ff5650cc 100644 --- a/test/a64/traces/sim-sli-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sli-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sli-2d-2opimm-trace-a64.h b/test/a64/traces/sim-sli-2d-2opimm-trace-a64.h index c391e42e..9fe0fbe4 100644 --- a/test/a64/traces/sim-sli-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sli-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sli-2s-2opimm-trace-a64.h b/test/a64/traces/sim-sli-2s-2opimm-trace-a64.h index 3cadd54d..56359393 100644 --- a/test/a64/traces/sim-sli-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sli-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sli-4h-2opimm-trace-a64.h b/test/a64/traces/sim-sli-4h-2opimm-trace-a64.h index 79e0140f..7b9686b2 100644 --- a/test/a64/traces/sim-sli-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sli-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sli-4s-2opimm-trace-a64.h b/test/a64/traces/sim-sli-4s-2opimm-trace-a64.h index 0381fac9..b86e8d05 100644 --- a/test/a64/traces/sim-sli-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sli-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sli-8b-2opimm-trace-a64.h b/test/a64/traces/sim-sli-8b-2opimm-trace-a64.h index 1c411556..f06c9a5d 100644 --- a/test/a64/traces/sim-sli-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sli-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sli-8h-2opimm-trace-a64.h b/test/a64/traces/sim-sli-8h-2opimm-trace-a64.h index dc446fd5..63c11e3d 100644 --- a/test/a64/traces/sim-sli-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sli-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sli-d-2opimm-trace-a64.h b/test/a64/traces/sim-sli-d-2opimm-trace-a64.h index 7746a018..043642e3 100644 --- a/test/a64/traces/sim-sli-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sli-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smax-16b-trace-a64.h b/test/a64/traces/sim-smax-16b-trace-a64.h index 12f5d180..1a7cb011 100644 --- a/test/a64/traces/sim-smax-16b-trace-a64.h +++ b/test/a64/traces/sim-smax-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smax-2s-trace-a64.h b/test/a64/traces/sim-smax-2s-trace-a64.h index 54a13697..95c62ae4 100644 --- a/test/a64/traces/sim-smax-2s-trace-a64.h +++ b/test/a64/traces/sim-smax-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smax-4h-trace-a64.h b/test/a64/traces/sim-smax-4h-trace-a64.h index bffe3e12..c7f2178a 100644 --- a/test/a64/traces/sim-smax-4h-trace-a64.h +++ b/test/a64/traces/sim-smax-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smax-4s-trace-a64.h b/test/a64/traces/sim-smax-4s-trace-a64.h index 03c22ccd..a9356ef9 100644 --- a/test/a64/traces/sim-smax-4s-trace-a64.h +++ b/test/a64/traces/sim-smax-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smax-8b-trace-a64.h b/test/a64/traces/sim-smax-8b-trace-a64.h index 7c470608..2df8ed78 100644 --- a/test/a64/traces/sim-smax-8b-trace-a64.h +++ b/test/a64/traces/sim-smax-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smax-8h-trace-a64.h b/test/a64/traces/sim-smax-8h-trace-a64.h index 099ebfb9..42714e30 100644 --- a/test/a64/traces/sim-smax-8h-trace-a64.h +++ b/test/a64/traces/sim-smax-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smaxp-16b-trace-a64.h b/test/a64/traces/sim-smaxp-16b-trace-a64.h index 55d06d62..8c3c2cc9 100644 --- a/test/a64/traces/sim-smaxp-16b-trace-a64.h +++ b/test/a64/traces/sim-smaxp-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smaxp-2s-trace-a64.h b/test/a64/traces/sim-smaxp-2s-trace-a64.h index d3212603..a335132c 100644 --- a/test/a64/traces/sim-smaxp-2s-trace-a64.h +++ b/test/a64/traces/sim-smaxp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smaxp-4h-trace-a64.h b/test/a64/traces/sim-smaxp-4h-trace-a64.h index 6913f66a..3c3f68bd 100644 --- a/test/a64/traces/sim-smaxp-4h-trace-a64.h +++ b/test/a64/traces/sim-smaxp-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smaxp-4s-trace-a64.h b/test/a64/traces/sim-smaxp-4s-trace-a64.h index f2460476..86e2b953 100644 --- a/test/a64/traces/sim-smaxp-4s-trace-a64.h +++ b/test/a64/traces/sim-smaxp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smaxp-8b-trace-a64.h b/test/a64/traces/sim-smaxp-8b-trace-a64.h index a62a9eec..d46af76c 100644 --- a/test/a64/traces/sim-smaxp-8b-trace-a64.h +++ b/test/a64/traces/sim-smaxp-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smaxp-8h-trace-a64.h b/test/a64/traces/sim-smaxp-8h-trace-a64.h index 060488a9..360c6d8c 100644 --- a/test/a64/traces/sim-smaxp-8h-trace-a64.h +++ b/test/a64/traces/sim-smaxp-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smaxv-b-16b-trace-a64.h b/test/a64/traces/sim-smaxv-b-16b-trace-a64.h index eb58d66a..44afea79 100644 --- a/test/a64/traces/sim-smaxv-b-16b-trace-a64.h +++ b/test/a64/traces/sim-smaxv-b-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smaxv-b-8b-trace-a64.h b/test/a64/traces/sim-smaxv-b-8b-trace-a64.h index fcb166c9..7fcac489 100644 --- a/test/a64/traces/sim-smaxv-b-8b-trace-a64.h +++ b/test/a64/traces/sim-smaxv-b-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smaxv-h-4h-trace-a64.h b/test/a64/traces/sim-smaxv-h-4h-trace-a64.h index 25d08bdb..8ecb2769 100644 --- a/test/a64/traces/sim-smaxv-h-4h-trace-a64.h +++ b/test/a64/traces/sim-smaxv-h-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smaxv-h-8h-trace-a64.h b/test/a64/traces/sim-smaxv-h-8h-trace-a64.h index 2833e9cc..23b11375 100644 --- a/test/a64/traces/sim-smaxv-h-8h-trace-a64.h +++ b/test/a64/traces/sim-smaxv-h-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smaxv-s-4s-trace-a64.h b/test/a64/traces/sim-smaxv-s-4s-trace-a64.h index 650d7f51..b9cb8dcc 100644 --- a/test/a64/traces/sim-smaxv-s-4s-trace-a64.h +++ b/test/a64/traces/sim-smaxv-s-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smin-16b-trace-a64.h b/test/a64/traces/sim-smin-16b-trace-a64.h index 7475c339..3ea00f15 100644 --- a/test/a64/traces/sim-smin-16b-trace-a64.h +++ b/test/a64/traces/sim-smin-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smin-2s-trace-a64.h b/test/a64/traces/sim-smin-2s-trace-a64.h index 2decbacf..f32a6fff 100644 --- a/test/a64/traces/sim-smin-2s-trace-a64.h +++ b/test/a64/traces/sim-smin-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smin-4h-trace-a64.h b/test/a64/traces/sim-smin-4h-trace-a64.h index 6fd4e2a8..586551ff 100644 --- a/test/a64/traces/sim-smin-4h-trace-a64.h +++ b/test/a64/traces/sim-smin-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smin-4s-trace-a64.h b/test/a64/traces/sim-smin-4s-trace-a64.h index 23761748..574fe4e5 100644 --- a/test/a64/traces/sim-smin-4s-trace-a64.h +++ b/test/a64/traces/sim-smin-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smin-8b-trace-a64.h b/test/a64/traces/sim-smin-8b-trace-a64.h index f0bfcd5f..903613a3 100644 --- a/test/a64/traces/sim-smin-8b-trace-a64.h +++ b/test/a64/traces/sim-smin-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smin-8h-trace-a64.h b/test/a64/traces/sim-smin-8h-trace-a64.h index c111c6a8..1d650847 100644 --- a/test/a64/traces/sim-smin-8h-trace-a64.h +++ b/test/a64/traces/sim-smin-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sminp-16b-trace-a64.h b/test/a64/traces/sim-sminp-16b-trace-a64.h index 9742afe8..9a1b7816 100644 --- a/test/a64/traces/sim-sminp-16b-trace-a64.h +++ b/test/a64/traces/sim-sminp-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sminp-2s-trace-a64.h b/test/a64/traces/sim-sminp-2s-trace-a64.h index 82726276..645966e7 100644 --- a/test/a64/traces/sim-sminp-2s-trace-a64.h +++ b/test/a64/traces/sim-sminp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sminp-4h-trace-a64.h b/test/a64/traces/sim-sminp-4h-trace-a64.h index 32fed096..922f6608 100644 --- a/test/a64/traces/sim-sminp-4h-trace-a64.h +++ b/test/a64/traces/sim-sminp-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sminp-4s-trace-a64.h b/test/a64/traces/sim-sminp-4s-trace-a64.h index 0d42ef08..48b42a92 100644 --- a/test/a64/traces/sim-sminp-4s-trace-a64.h +++ b/test/a64/traces/sim-sminp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sminp-8b-trace-a64.h b/test/a64/traces/sim-sminp-8b-trace-a64.h index 4afd8812..64566018 100644 --- a/test/a64/traces/sim-sminp-8b-trace-a64.h +++ b/test/a64/traces/sim-sminp-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sminp-8h-trace-a64.h b/test/a64/traces/sim-sminp-8h-trace-a64.h index 471d6b01..aee4d693 100644 --- a/test/a64/traces/sim-sminp-8h-trace-a64.h +++ b/test/a64/traces/sim-sminp-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sminv-b-16b-trace-a64.h b/test/a64/traces/sim-sminv-b-16b-trace-a64.h index 0df4fb40..c13a258d 100644 --- a/test/a64/traces/sim-sminv-b-16b-trace-a64.h +++ b/test/a64/traces/sim-sminv-b-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sminv-b-8b-trace-a64.h b/test/a64/traces/sim-sminv-b-8b-trace-a64.h index 948a38ea..6c3f9749 100644 --- a/test/a64/traces/sim-sminv-b-8b-trace-a64.h +++ b/test/a64/traces/sim-sminv-b-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sminv-h-4h-trace-a64.h b/test/a64/traces/sim-sminv-h-4h-trace-a64.h index fb26bf15..06f35c62 100644 --- a/test/a64/traces/sim-sminv-h-4h-trace-a64.h +++ b/test/a64/traces/sim-sminv-h-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sminv-h-8h-trace-a64.h b/test/a64/traces/sim-sminv-h-8h-trace-a64.h index 6afb0093..14ba3c96 100644 --- a/test/a64/traces/sim-sminv-h-8h-trace-a64.h +++ b/test/a64/traces/sim-sminv-h-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sminv-s-4s-trace-a64.h b/test/a64/traces/sim-sminv-s-4s-trace-a64.h index fc64c04a..422f5611 100644 --- a/test/a64/traces/sim-sminv-s-4s-trace-a64.h +++ b/test/a64/traces/sim-sminv-s-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlal-2d-2s-s-trace-a64.h b/test/a64/traces/sim-smlal-2d-2s-s-trace-a64.h index abf65807..447601f9 100644 --- a/test/a64/traces/sim-smlal-2d-2s-s-trace-a64.h +++ b/test/a64/traces/sim-smlal-2d-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlal-2d-trace-a64.h b/test/a64/traces/sim-smlal-2d-trace-a64.h index 2ea965d1..702c8adb 100644 --- a/test/a64/traces/sim-smlal-2d-trace-a64.h +++ b/test/a64/traces/sim-smlal-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlal-4s-4h-h-trace-a64.h b/test/a64/traces/sim-smlal-4s-4h-h-trace-a64.h index 592230ae..828ae51d 100644 --- a/test/a64/traces/sim-smlal-4s-4h-h-trace-a64.h +++ b/test/a64/traces/sim-smlal-4s-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlal-4s-trace-a64.h b/test/a64/traces/sim-smlal-4s-trace-a64.h index 563143f4..d6b9d867 100644 --- a/test/a64/traces/sim-smlal-4s-trace-a64.h +++ b/test/a64/traces/sim-smlal-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlal-8h-trace-a64.h b/test/a64/traces/sim-smlal-8h-trace-a64.h index 249de616..617cc45c 100644 --- a/test/a64/traces/sim-smlal-8h-trace-a64.h +++ b/test/a64/traces/sim-smlal-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlal2-2d-4s-s-trace-a64.h b/test/a64/traces/sim-smlal2-2d-4s-s-trace-a64.h index 4702ec27..fc79afb4 100644 --- a/test/a64/traces/sim-smlal2-2d-4s-s-trace-a64.h +++ b/test/a64/traces/sim-smlal2-2d-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlal2-2d-trace-a64.h b/test/a64/traces/sim-smlal2-2d-trace-a64.h index 5dce51d9..0a8cc515 100644 --- a/test/a64/traces/sim-smlal2-2d-trace-a64.h +++ b/test/a64/traces/sim-smlal2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlal2-4s-8h-h-trace-a64.h b/test/a64/traces/sim-smlal2-4s-8h-h-trace-a64.h index a5d2f934..263f0c4d 100644 --- a/test/a64/traces/sim-smlal2-4s-8h-h-trace-a64.h +++ b/test/a64/traces/sim-smlal2-4s-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlal2-4s-trace-a64.h b/test/a64/traces/sim-smlal2-4s-trace-a64.h index 7e23218d..d87171df 100644 --- a/test/a64/traces/sim-smlal2-4s-trace-a64.h +++ b/test/a64/traces/sim-smlal2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlal2-8h-trace-a64.h b/test/a64/traces/sim-smlal2-8h-trace-a64.h index bc08d1dc..19787fe4 100644 --- a/test/a64/traces/sim-smlal2-8h-trace-a64.h +++ b/test/a64/traces/sim-smlal2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlsl-2d-2s-s-trace-a64.h b/test/a64/traces/sim-smlsl-2d-2s-s-trace-a64.h index eb7f5b0d..a1ee17d2 100644 --- a/test/a64/traces/sim-smlsl-2d-2s-s-trace-a64.h +++ b/test/a64/traces/sim-smlsl-2d-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlsl-2d-trace-a64.h b/test/a64/traces/sim-smlsl-2d-trace-a64.h index 9a1c6172..adba287e 100644 --- a/test/a64/traces/sim-smlsl-2d-trace-a64.h +++ b/test/a64/traces/sim-smlsl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlsl-4s-4h-h-trace-a64.h b/test/a64/traces/sim-smlsl-4s-4h-h-trace-a64.h index ac8535b6..070d1ec3 100644 --- a/test/a64/traces/sim-smlsl-4s-4h-h-trace-a64.h +++ b/test/a64/traces/sim-smlsl-4s-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlsl-4s-trace-a64.h b/test/a64/traces/sim-smlsl-4s-trace-a64.h index a70ae7b2..700732d6 100644 --- a/test/a64/traces/sim-smlsl-4s-trace-a64.h +++ b/test/a64/traces/sim-smlsl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlsl-8h-trace-a64.h b/test/a64/traces/sim-smlsl-8h-trace-a64.h index 1f8d57bd..aed346c8 100644 --- a/test/a64/traces/sim-smlsl-8h-trace-a64.h +++ b/test/a64/traces/sim-smlsl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlsl2-2d-4s-s-trace-a64.h b/test/a64/traces/sim-smlsl2-2d-4s-s-trace-a64.h index 5fd95a47..412ea2e9 100644 --- a/test/a64/traces/sim-smlsl2-2d-4s-s-trace-a64.h +++ b/test/a64/traces/sim-smlsl2-2d-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlsl2-2d-trace-a64.h b/test/a64/traces/sim-smlsl2-2d-trace-a64.h index bb959a8d..9a58f11c 100644 --- a/test/a64/traces/sim-smlsl2-2d-trace-a64.h +++ b/test/a64/traces/sim-smlsl2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlsl2-4s-8h-h-trace-a64.h b/test/a64/traces/sim-smlsl2-4s-8h-h-trace-a64.h index e9c2423b..9d36d4d1 100644 --- a/test/a64/traces/sim-smlsl2-4s-8h-h-trace-a64.h +++ b/test/a64/traces/sim-smlsl2-4s-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlsl2-4s-trace-a64.h b/test/a64/traces/sim-smlsl2-4s-trace-a64.h index 3216f61e..017376d3 100644 --- a/test/a64/traces/sim-smlsl2-4s-trace-a64.h +++ b/test/a64/traces/sim-smlsl2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smlsl2-8h-trace-a64.h b/test/a64/traces/sim-smlsl2-8h-trace-a64.h index 2677d753..d8f4213e 100644 --- a/test/a64/traces/sim-smlsl2-8h-trace-a64.h +++ b/test/a64/traces/sim-smlsl2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smull-2d-2s-s-trace-a64.h b/test/a64/traces/sim-smull-2d-2s-s-trace-a64.h index 80d544d3..fee76b73 100644 --- a/test/a64/traces/sim-smull-2d-2s-s-trace-a64.h +++ b/test/a64/traces/sim-smull-2d-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smull-2d-trace-a64.h b/test/a64/traces/sim-smull-2d-trace-a64.h index 80d90f45..462fed7e 100644 --- a/test/a64/traces/sim-smull-2d-trace-a64.h +++ b/test/a64/traces/sim-smull-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smull-4s-4h-h-trace-a64.h b/test/a64/traces/sim-smull-4s-4h-h-trace-a64.h index cdbbb043..c14707e0 100644 --- a/test/a64/traces/sim-smull-4s-4h-h-trace-a64.h +++ b/test/a64/traces/sim-smull-4s-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smull-4s-trace-a64.h b/test/a64/traces/sim-smull-4s-trace-a64.h index 20001e57..32df1e2c 100644 --- a/test/a64/traces/sim-smull-4s-trace-a64.h +++ b/test/a64/traces/sim-smull-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smull-8h-trace-a64.h b/test/a64/traces/sim-smull-8h-trace-a64.h index ef25a60c..ef8a3164 100644 --- a/test/a64/traces/sim-smull-8h-trace-a64.h +++ b/test/a64/traces/sim-smull-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smull2-2d-4s-s-trace-a64.h b/test/a64/traces/sim-smull2-2d-4s-s-trace-a64.h index e09ea529..8b58b73c 100644 --- a/test/a64/traces/sim-smull2-2d-4s-s-trace-a64.h +++ b/test/a64/traces/sim-smull2-2d-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smull2-2d-trace-a64.h b/test/a64/traces/sim-smull2-2d-trace-a64.h index 33ebaefa..b5388fbf 100644 --- a/test/a64/traces/sim-smull2-2d-trace-a64.h +++ b/test/a64/traces/sim-smull2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smull2-4s-8h-h-trace-a64.h b/test/a64/traces/sim-smull2-4s-8h-h-trace-a64.h index f3a5c29b..2c92e28c 100644 --- a/test/a64/traces/sim-smull2-4s-8h-h-trace-a64.h +++ b/test/a64/traces/sim-smull2-4s-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smull2-4s-trace-a64.h b/test/a64/traces/sim-smull2-4s-trace-a64.h index a28e86f6..f32ed21d 100644 --- a/test/a64/traces/sim-smull2-4s-trace-a64.h +++ b/test/a64/traces/sim-smull2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-smull2-8h-trace-a64.h b/test/a64/traces/sim-smull2-8h-trace-a64.h index 1db54dbe..70c11944 100644 --- a/test/a64/traces/sim-smull2-8h-trace-a64.h +++ b/test/a64/traces/sim-smull2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqabs-16b-trace-a64.h b/test/a64/traces/sim-sqabs-16b-trace-a64.h index 74a185a5..1c5e4ebb 100644 --- a/test/a64/traces/sim-sqabs-16b-trace-a64.h +++ b/test/a64/traces/sim-sqabs-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqabs-2d-trace-a64.h b/test/a64/traces/sim-sqabs-2d-trace-a64.h index 6e881619..09f010b5 100644 --- a/test/a64/traces/sim-sqabs-2d-trace-a64.h +++ b/test/a64/traces/sim-sqabs-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqabs-2s-trace-a64.h b/test/a64/traces/sim-sqabs-2s-trace-a64.h index 5ac09b38..68d6e7c2 100644 --- a/test/a64/traces/sim-sqabs-2s-trace-a64.h +++ b/test/a64/traces/sim-sqabs-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqabs-4h-trace-a64.h b/test/a64/traces/sim-sqabs-4h-trace-a64.h index dcf0fc69..01283549 100644 --- a/test/a64/traces/sim-sqabs-4h-trace-a64.h +++ b/test/a64/traces/sim-sqabs-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqabs-4s-trace-a64.h b/test/a64/traces/sim-sqabs-4s-trace-a64.h index 881a976c..f209ba5a 100644 --- a/test/a64/traces/sim-sqabs-4s-trace-a64.h +++ b/test/a64/traces/sim-sqabs-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqabs-8b-trace-a64.h b/test/a64/traces/sim-sqabs-8b-trace-a64.h index ab61e760..f0e99b00 100644 --- a/test/a64/traces/sim-sqabs-8b-trace-a64.h +++ b/test/a64/traces/sim-sqabs-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqabs-8h-trace-a64.h b/test/a64/traces/sim-sqabs-8h-trace-a64.h index d0cb0cce..24145060 100644 --- a/test/a64/traces/sim-sqabs-8h-trace-a64.h +++ b/test/a64/traces/sim-sqabs-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqabs-b-trace-a64.h b/test/a64/traces/sim-sqabs-b-trace-a64.h index a8d67eee..7d659fa8 100644 --- a/test/a64/traces/sim-sqabs-b-trace-a64.h +++ b/test/a64/traces/sim-sqabs-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqabs-d-trace-a64.h b/test/a64/traces/sim-sqabs-d-trace-a64.h index 6a31a60c..c7edf923 100644 --- a/test/a64/traces/sim-sqabs-d-trace-a64.h +++ b/test/a64/traces/sim-sqabs-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqabs-h-trace-a64.h b/test/a64/traces/sim-sqabs-h-trace-a64.h index a7fec424..b31ace3d 100644 --- a/test/a64/traces/sim-sqabs-h-trace-a64.h +++ b/test/a64/traces/sim-sqabs-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqabs-s-trace-a64.h b/test/a64/traces/sim-sqabs-s-trace-a64.h index a459ed0d..8de38aee 100644 --- a/test/a64/traces/sim-sqabs-s-trace-a64.h +++ b/test/a64/traces/sim-sqabs-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqadd-16b-trace-a64.h b/test/a64/traces/sim-sqadd-16b-trace-a64.h index 64c35043..66f73efc 100644 --- a/test/a64/traces/sim-sqadd-16b-trace-a64.h +++ b/test/a64/traces/sim-sqadd-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqadd-2d-trace-a64.h b/test/a64/traces/sim-sqadd-2d-trace-a64.h index 3e8f9e58..4c6b4d5b 100644 --- a/test/a64/traces/sim-sqadd-2d-trace-a64.h +++ b/test/a64/traces/sim-sqadd-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqadd-2s-trace-a64.h b/test/a64/traces/sim-sqadd-2s-trace-a64.h index 44b28cd7..fb3af75d 100644 --- a/test/a64/traces/sim-sqadd-2s-trace-a64.h +++ b/test/a64/traces/sim-sqadd-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqadd-4h-trace-a64.h b/test/a64/traces/sim-sqadd-4h-trace-a64.h index 46d80b53..562f5585 100644 --- a/test/a64/traces/sim-sqadd-4h-trace-a64.h +++ b/test/a64/traces/sim-sqadd-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqadd-4s-trace-a64.h b/test/a64/traces/sim-sqadd-4s-trace-a64.h index f13d94bf..916beb35 100644 --- a/test/a64/traces/sim-sqadd-4s-trace-a64.h +++ b/test/a64/traces/sim-sqadd-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqadd-8b-trace-a64.h b/test/a64/traces/sim-sqadd-8b-trace-a64.h index d32354bc..d17df960 100644 --- a/test/a64/traces/sim-sqadd-8b-trace-a64.h +++ b/test/a64/traces/sim-sqadd-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqadd-8h-trace-a64.h b/test/a64/traces/sim-sqadd-8h-trace-a64.h index aa0a9f65..4f9b14ca 100644 --- a/test/a64/traces/sim-sqadd-8h-trace-a64.h +++ b/test/a64/traces/sim-sqadd-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqadd-b-trace-a64.h b/test/a64/traces/sim-sqadd-b-trace-a64.h index 10b76c1a..775e569f 100644 --- a/test/a64/traces/sim-sqadd-b-trace-a64.h +++ b/test/a64/traces/sim-sqadd-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqadd-d-trace-a64.h b/test/a64/traces/sim-sqadd-d-trace-a64.h index 1aba133e..5161957a 100644 --- a/test/a64/traces/sim-sqadd-d-trace-a64.h +++ b/test/a64/traces/sim-sqadd-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqadd-h-trace-a64.h b/test/a64/traces/sim-sqadd-h-trace-a64.h index 80a5013b..d56f555a 100644 --- a/test/a64/traces/sim-sqadd-h-trace-a64.h +++ b/test/a64/traces/sim-sqadd-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqadd-s-trace-a64.h b/test/a64/traces/sim-sqadd-s-trace-a64.h index 02b6c464..98064dd9 100644 --- a/test/a64/traces/sim-sqadd-s-trace-a64.h +++ b/test/a64/traces/sim-sqadd-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlal-2d-2s-s-trace-a64.h b/test/a64/traces/sim-sqdmlal-2d-2s-s-trace-a64.h index 275a6dfe..fc1787fb 100644 --- a/test/a64/traces/sim-sqdmlal-2d-2s-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmlal-2d-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlal-2d-trace-a64.h b/test/a64/traces/sim-sqdmlal-2d-trace-a64.h index 8e6ab2c7..9666867f 100644 --- a/test/a64/traces/sim-sqdmlal-2d-trace-a64.h +++ b/test/a64/traces/sim-sqdmlal-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlal-4s-4h-h-trace-a64.h b/test/a64/traces/sim-sqdmlal-4s-4h-h-trace-a64.h index 207576f2..c3567b8f 100644 --- a/test/a64/traces/sim-sqdmlal-4s-4h-h-trace-a64.h +++ b/test/a64/traces/sim-sqdmlal-4s-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlal-4s-trace-a64.h b/test/a64/traces/sim-sqdmlal-4s-trace-a64.h index 3efc72fc..fbce4444 100644 --- a/test/a64/traces/sim-sqdmlal-4s-trace-a64.h +++ b/test/a64/traces/sim-sqdmlal-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlal-d-s-s-trace-a64.h b/test/a64/traces/sim-sqdmlal-d-s-s-trace-a64.h index 53820287..f5fe3fcf 100644 --- a/test/a64/traces/sim-sqdmlal-d-s-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmlal-d-s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlal-d-trace-a64.h b/test/a64/traces/sim-sqdmlal-d-trace-a64.h index cca0dea2..4ccfe4c2 100644 --- a/test/a64/traces/sim-sqdmlal-d-trace-a64.h +++ b/test/a64/traces/sim-sqdmlal-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlal-s-h-h-trace-a64.h b/test/a64/traces/sim-sqdmlal-s-h-h-trace-a64.h index c3cdfae5..bb1c9974 100644 --- a/test/a64/traces/sim-sqdmlal-s-h-h-trace-a64.h +++ b/test/a64/traces/sim-sqdmlal-s-h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlal-s-trace-a64.h b/test/a64/traces/sim-sqdmlal-s-trace-a64.h index 64d6f3e3..834b5c85 100644 --- a/test/a64/traces/sim-sqdmlal-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmlal-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlal2-2d-4s-s-trace-a64.h b/test/a64/traces/sim-sqdmlal2-2d-4s-s-trace-a64.h index 1b7ccd2f..6e2566d5 100644 --- a/test/a64/traces/sim-sqdmlal2-2d-4s-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmlal2-2d-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlal2-2d-trace-a64.h b/test/a64/traces/sim-sqdmlal2-2d-trace-a64.h index 8df519f7..c022a1bb 100644 --- a/test/a64/traces/sim-sqdmlal2-2d-trace-a64.h +++ b/test/a64/traces/sim-sqdmlal2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlal2-4s-8h-h-trace-a64.h b/test/a64/traces/sim-sqdmlal2-4s-8h-h-trace-a64.h index 1beb0b99..3bbfa507 100644 --- a/test/a64/traces/sim-sqdmlal2-4s-8h-h-trace-a64.h +++ b/test/a64/traces/sim-sqdmlal2-4s-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlal2-4s-trace-a64.h b/test/a64/traces/sim-sqdmlal2-4s-trace-a64.h index 89f2420c..44a75108 100644 --- a/test/a64/traces/sim-sqdmlal2-4s-trace-a64.h +++ b/test/a64/traces/sim-sqdmlal2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlsl-2d-2s-s-trace-a64.h b/test/a64/traces/sim-sqdmlsl-2d-2s-s-trace-a64.h index ea73824d..a46a5434 100644 --- a/test/a64/traces/sim-sqdmlsl-2d-2s-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmlsl-2d-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlsl-2d-trace-a64.h b/test/a64/traces/sim-sqdmlsl-2d-trace-a64.h index 4764ce65..f1fe47a9 100644 --- a/test/a64/traces/sim-sqdmlsl-2d-trace-a64.h +++ b/test/a64/traces/sim-sqdmlsl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlsl-4s-4h-h-trace-a64.h b/test/a64/traces/sim-sqdmlsl-4s-4h-h-trace-a64.h index 27b00dc5..5062ef49 100644 --- a/test/a64/traces/sim-sqdmlsl-4s-4h-h-trace-a64.h +++ b/test/a64/traces/sim-sqdmlsl-4s-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlsl-4s-trace-a64.h b/test/a64/traces/sim-sqdmlsl-4s-trace-a64.h index d1acb151..7e0d6c4d 100644 --- a/test/a64/traces/sim-sqdmlsl-4s-trace-a64.h +++ b/test/a64/traces/sim-sqdmlsl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlsl-d-s-s-trace-a64.h b/test/a64/traces/sim-sqdmlsl-d-s-s-trace-a64.h index 69072690..1f005cc1 100644 --- a/test/a64/traces/sim-sqdmlsl-d-s-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmlsl-d-s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlsl-d-trace-a64.h b/test/a64/traces/sim-sqdmlsl-d-trace-a64.h index 471e0751..bddc78cb 100644 --- a/test/a64/traces/sim-sqdmlsl-d-trace-a64.h +++ b/test/a64/traces/sim-sqdmlsl-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlsl-s-h-h-trace-a64.h b/test/a64/traces/sim-sqdmlsl-s-h-h-trace-a64.h index 9c8c1271..75bd7d23 100644 --- a/test/a64/traces/sim-sqdmlsl-s-h-h-trace-a64.h +++ b/test/a64/traces/sim-sqdmlsl-s-h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlsl-s-trace-a64.h b/test/a64/traces/sim-sqdmlsl-s-trace-a64.h index 7031b724..27250416 100644 --- a/test/a64/traces/sim-sqdmlsl-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmlsl-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlsl2-2d-4s-s-trace-a64.h b/test/a64/traces/sim-sqdmlsl2-2d-4s-s-trace-a64.h index ecd50a14..c3f0fc8d 100644 --- a/test/a64/traces/sim-sqdmlsl2-2d-4s-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmlsl2-2d-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlsl2-2d-trace-a64.h b/test/a64/traces/sim-sqdmlsl2-2d-trace-a64.h index c15c12a7..10ecea59 100644 --- a/test/a64/traces/sim-sqdmlsl2-2d-trace-a64.h +++ b/test/a64/traces/sim-sqdmlsl2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlsl2-4s-8h-h-trace-a64.h b/test/a64/traces/sim-sqdmlsl2-4s-8h-h-trace-a64.h index 29d94daf..0172344e 100644 --- a/test/a64/traces/sim-sqdmlsl2-4s-8h-h-trace-a64.h +++ b/test/a64/traces/sim-sqdmlsl2-4s-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmlsl2-4s-trace-a64.h b/test/a64/traces/sim-sqdmlsl2-4s-trace-a64.h index 01b1d75a..d552cc9e 100644 --- a/test/a64/traces/sim-sqdmlsl2-4s-trace-a64.h +++ b/test/a64/traces/sim-sqdmlsl2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmulh-2s-2s-s-trace-a64.h b/test/a64/traces/sim-sqdmulh-2s-2s-s-trace-a64.h index 302f59c3..caa7a4ae 100644 --- a/test/a64/traces/sim-sqdmulh-2s-2s-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmulh-2s-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmulh-2s-trace-a64.h b/test/a64/traces/sim-sqdmulh-2s-trace-a64.h index 79897d6d..0999d62b 100644 --- a/test/a64/traces/sim-sqdmulh-2s-trace-a64.h +++ b/test/a64/traces/sim-sqdmulh-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmulh-4h-4h-h-trace-a64.h b/test/a64/traces/sim-sqdmulh-4h-4h-h-trace-a64.h index 69be6752..c3879ef1 100644 --- a/test/a64/traces/sim-sqdmulh-4h-4h-h-trace-a64.h +++ b/test/a64/traces/sim-sqdmulh-4h-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmulh-4h-trace-a64.h b/test/a64/traces/sim-sqdmulh-4h-trace-a64.h index ef93016d..86a07a50 100644 --- a/test/a64/traces/sim-sqdmulh-4h-trace-a64.h +++ b/test/a64/traces/sim-sqdmulh-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmulh-4s-4s-s-trace-a64.h b/test/a64/traces/sim-sqdmulh-4s-4s-s-trace-a64.h index 6fea21c7..91df5665 100644 --- a/test/a64/traces/sim-sqdmulh-4s-4s-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmulh-4s-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmulh-4s-trace-a64.h b/test/a64/traces/sim-sqdmulh-4s-trace-a64.h index 40ceeab8..8b2a6919 100644 --- a/test/a64/traces/sim-sqdmulh-4s-trace-a64.h +++ b/test/a64/traces/sim-sqdmulh-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmulh-8h-8h-h-trace-a64.h b/test/a64/traces/sim-sqdmulh-8h-8h-h-trace-a64.h index b7322e31..042cd4af 100644 --- a/test/a64/traces/sim-sqdmulh-8h-8h-h-trace-a64.h +++ b/test/a64/traces/sim-sqdmulh-8h-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmulh-8h-trace-a64.h b/test/a64/traces/sim-sqdmulh-8h-trace-a64.h index af98cd56..d8e15fb8 100644 --- a/test/a64/traces/sim-sqdmulh-8h-trace-a64.h +++ b/test/a64/traces/sim-sqdmulh-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmulh-h-h-h-trace-a64.h b/test/a64/traces/sim-sqdmulh-h-h-h-trace-a64.h index a5cb5cb7..0790b1a6 100644 --- a/test/a64/traces/sim-sqdmulh-h-h-h-trace-a64.h +++ b/test/a64/traces/sim-sqdmulh-h-h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmulh-h-trace-a64.h b/test/a64/traces/sim-sqdmulh-h-trace-a64.h index 7924e567..95ad42e6 100644 --- a/test/a64/traces/sim-sqdmulh-h-trace-a64.h +++ b/test/a64/traces/sim-sqdmulh-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmulh-s-s-s-trace-a64.h b/test/a64/traces/sim-sqdmulh-s-s-s-trace-a64.h index c257e68b..d561b913 100644 --- a/test/a64/traces/sim-sqdmulh-s-s-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmulh-s-s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmulh-s-trace-a64.h b/test/a64/traces/sim-sqdmulh-s-trace-a64.h index 114c2828..5b345018 100644 --- a/test/a64/traces/sim-sqdmulh-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmulh-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmull-2d-2s-s-trace-a64.h b/test/a64/traces/sim-sqdmull-2d-2s-s-trace-a64.h index 27a647ce..a119d55a 100644 --- a/test/a64/traces/sim-sqdmull-2d-2s-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmull-2d-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmull-2d-trace-a64.h b/test/a64/traces/sim-sqdmull-2d-trace-a64.h index 94130a16..aa06fa2f 100644 --- a/test/a64/traces/sim-sqdmull-2d-trace-a64.h +++ b/test/a64/traces/sim-sqdmull-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmull-4s-4h-h-trace-a64.h b/test/a64/traces/sim-sqdmull-4s-4h-h-trace-a64.h index 31f8ccfd..ad6edf6f 100644 --- a/test/a64/traces/sim-sqdmull-4s-4h-h-trace-a64.h +++ b/test/a64/traces/sim-sqdmull-4s-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmull-4s-trace-a64.h b/test/a64/traces/sim-sqdmull-4s-trace-a64.h index 32b2f647..9f7567ce 100644 --- a/test/a64/traces/sim-sqdmull-4s-trace-a64.h +++ b/test/a64/traces/sim-sqdmull-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmull-d-s-s-trace-a64.h b/test/a64/traces/sim-sqdmull-d-s-s-trace-a64.h index 7bcb1147..9a9dba93 100644 --- a/test/a64/traces/sim-sqdmull-d-s-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmull-d-s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmull-d-trace-a64.h b/test/a64/traces/sim-sqdmull-d-trace-a64.h index a067746b..05bc7b68 100644 --- a/test/a64/traces/sim-sqdmull-d-trace-a64.h +++ b/test/a64/traces/sim-sqdmull-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmull-s-h-h-trace-a64.h b/test/a64/traces/sim-sqdmull-s-h-h-trace-a64.h index b086ee03..ce50ec3e 100644 --- a/test/a64/traces/sim-sqdmull-s-h-h-trace-a64.h +++ b/test/a64/traces/sim-sqdmull-s-h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmull-s-trace-a64.h b/test/a64/traces/sim-sqdmull-s-trace-a64.h index 3336b1e8..8a68f72a 100644 --- a/test/a64/traces/sim-sqdmull-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmull-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmull2-2d-4s-s-trace-a64.h b/test/a64/traces/sim-sqdmull2-2d-4s-s-trace-a64.h index 80cfa9a2..a7b04bf8 100644 --- a/test/a64/traces/sim-sqdmull2-2d-4s-s-trace-a64.h +++ b/test/a64/traces/sim-sqdmull2-2d-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmull2-2d-trace-a64.h b/test/a64/traces/sim-sqdmull2-2d-trace-a64.h index e955be6e..b236c6d8 100644 --- a/test/a64/traces/sim-sqdmull2-2d-trace-a64.h +++ b/test/a64/traces/sim-sqdmull2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmull2-4s-8h-h-trace-a64.h b/test/a64/traces/sim-sqdmull2-4s-8h-h-trace-a64.h index 4086f9f0..33591fd8 100644 --- a/test/a64/traces/sim-sqdmull2-4s-8h-h-trace-a64.h +++ b/test/a64/traces/sim-sqdmull2-4s-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqdmull2-4s-trace-a64.h b/test/a64/traces/sim-sqdmull2-4s-trace-a64.h index 13ccf7d0..791f827f 100644 --- a/test/a64/traces/sim-sqdmull2-4s-trace-a64.h +++ b/test/a64/traces/sim-sqdmull2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqneg-16b-trace-a64.h b/test/a64/traces/sim-sqneg-16b-trace-a64.h index 17c0b370..77df50c5 100644 --- a/test/a64/traces/sim-sqneg-16b-trace-a64.h +++ b/test/a64/traces/sim-sqneg-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqneg-2d-trace-a64.h b/test/a64/traces/sim-sqneg-2d-trace-a64.h index 4d45bbc0..bba95ba8 100644 --- a/test/a64/traces/sim-sqneg-2d-trace-a64.h +++ b/test/a64/traces/sim-sqneg-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqneg-2s-trace-a64.h b/test/a64/traces/sim-sqneg-2s-trace-a64.h index 27d4b9b7..02bb4b19 100644 --- a/test/a64/traces/sim-sqneg-2s-trace-a64.h +++ b/test/a64/traces/sim-sqneg-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqneg-4h-trace-a64.h b/test/a64/traces/sim-sqneg-4h-trace-a64.h index f10c0924..f4c88b35 100644 --- a/test/a64/traces/sim-sqneg-4h-trace-a64.h +++ b/test/a64/traces/sim-sqneg-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqneg-4s-trace-a64.h b/test/a64/traces/sim-sqneg-4s-trace-a64.h index 5ecbe560..53e1b436 100644 --- a/test/a64/traces/sim-sqneg-4s-trace-a64.h +++ b/test/a64/traces/sim-sqneg-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqneg-8b-trace-a64.h b/test/a64/traces/sim-sqneg-8b-trace-a64.h index 8bf9d6ff..f987ba7b 100644 --- a/test/a64/traces/sim-sqneg-8b-trace-a64.h +++ b/test/a64/traces/sim-sqneg-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqneg-8h-trace-a64.h b/test/a64/traces/sim-sqneg-8h-trace-a64.h index 2adcf245..decdec89 100644 --- a/test/a64/traces/sim-sqneg-8h-trace-a64.h +++ b/test/a64/traces/sim-sqneg-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqneg-b-trace-a64.h b/test/a64/traces/sim-sqneg-b-trace-a64.h index a7646a43..469ec4d8 100644 --- a/test/a64/traces/sim-sqneg-b-trace-a64.h +++ b/test/a64/traces/sim-sqneg-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqneg-d-trace-a64.h b/test/a64/traces/sim-sqneg-d-trace-a64.h index af1ad338..72457911 100644 --- a/test/a64/traces/sim-sqneg-d-trace-a64.h +++ b/test/a64/traces/sim-sqneg-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqneg-h-trace-a64.h b/test/a64/traces/sim-sqneg-h-trace-a64.h index 2663beb6..78be96cc 100644 --- a/test/a64/traces/sim-sqneg-h-trace-a64.h +++ b/test/a64/traces/sim-sqneg-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqneg-s-trace-a64.h b/test/a64/traces/sim-sqneg-s-trace-a64.h index a41fd3a5..b3f89b97 100644 --- a/test/a64/traces/sim-sqneg-s-trace-a64.h +++ b/test/a64/traces/sim-sqneg-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrdmulh-2s-2s-s-trace-a64.h b/test/a64/traces/sim-sqrdmulh-2s-2s-s-trace-a64.h index 99618a7d..5991dbef 100644 --- a/test/a64/traces/sim-sqrdmulh-2s-2s-s-trace-a64.h +++ b/test/a64/traces/sim-sqrdmulh-2s-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrdmulh-2s-trace-a64.h b/test/a64/traces/sim-sqrdmulh-2s-trace-a64.h index 9089eb3a..05011d4f 100644 --- a/test/a64/traces/sim-sqrdmulh-2s-trace-a64.h +++ b/test/a64/traces/sim-sqrdmulh-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrdmulh-4h-4h-h-trace-a64.h b/test/a64/traces/sim-sqrdmulh-4h-4h-h-trace-a64.h index db7c7eeb..8f78bcf1 100644 --- a/test/a64/traces/sim-sqrdmulh-4h-4h-h-trace-a64.h +++ b/test/a64/traces/sim-sqrdmulh-4h-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrdmulh-4h-trace-a64.h b/test/a64/traces/sim-sqrdmulh-4h-trace-a64.h index 31ce5162..1ce6f3fb 100644 --- a/test/a64/traces/sim-sqrdmulh-4h-trace-a64.h +++ b/test/a64/traces/sim-sqrdmulh-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrdmulh-4s-4s-s-trace-a64.h b/test/a64/traces/sim-sqrdmulh-4s-4s-s-trace-a64.h index d7d48bc1..7ed9f3a2 100644 --- a/test/a64/traces/sim-sqrdmulh-4s-4s-s-trace-a64.h +++ b/test/a64/traces/sim-sqrdmulh-4s-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrdmulh-4s-trace-a64.h b/test/a64/traces/sim-sqrdmulh-4s-trace-a64.h index 13402e2f..e466dbec 100644 --- a/test/a64/traces/sim-sqrdmulh-4s-trace-a64.h +++ b/test/a64/traces/sim-sqrdmulh-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrdmulh-8h-8h-h-trace-a64.h b/test/a64/traces/sim-sqrdmulh-8h-8h-h-trace-a64.h index c1756f65..d94d9ac4 100644 --- a/test/a64/traces/sim-sqrdmulh-8h-8h-h-trace-a64.h +++ b/test/a64/traces/sim-sqrdmulh-8h-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrdmulh-8h-trace-a64.h b/test/a64/traces/sim-sqrdmulh-8h-trace-a64.h index db51061e..6a303ee1 100644 --- a/test/a64/traces/sim-sqrdmulh-8h-trace-a64.h +++ b/test/a64/traces/sim-sqrdmulh-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrdmulh-h-h-h-trace-a64.h b/test/a64/traces/sim-sqrdmulh-h-h-h-trace-a64.h index 510c60ee..a36ef284 100644 --- a/test/a64/traces/sim-sqrdmulh-h-h-h-trace-a64.h +++ b/test/a64/traces/sim-sqrdmulh-h-h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrdmulh-h-trace-a64.h b/test/a64/traces/sim-sqrdmulh-h-trace-a64.h index 320cf64f..d3d95599 100644 --- a/test/a64/traces/sim-sqrdmulh-h-trace-a64.h +++ b/test/a64/traces/sim-sqrdmulh-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrdmulh-s-s-s-trace-a64.h b/test/a64/traces/sim-sqrdmulh-s-s-s-trace-a64.h index 44a4aa28..a3bba9c5 100644 --- a/test/a64/traces/sim-sqrdmulh-s-s-s-trace-a64.h +++ b/test/a64/traces/sim-sqrdmulh-s-s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrdmulh-s-trace-a64.h b/test/a64/traces/sim-sqrdmulh-s-trace-a64.h index 82ae091c..c5d1a975 100644 --- a/test/a64/traces/sim-sqrdmulh-s-trace-a64.h +++ b/test/a64/traces/sim-sqrdmulh-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshl-16b-trace-a64.h b/test/a64/traces/sim-sqrshl-16b-trace-a64.h index aaa88a69..9873f852 100644 --- a/test/a64/traces/sim-sqrshl-16b-trace-a64.h +++ b/test/a64/traces/sim-sqrshl-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshl-2d-trace-a64.h b/test/a64/traces/sim-sqrshl-2d-trace-a64.h index bdda8015..83d346f6 100644 --- a/test/a64/traces/sim-sqrshl-2d-trace-a64.h +++ b/test/a64/traces/sim-sqrshl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshl-2s-trace-a64.h b/test/a64/traces/sim-sqrshl-2s-trace-a64.h index bba1f435..7e3953e9 100644 --- a/test/a64/traces/sim-sqrshl-2s-trace-a64.h +++ b/test/a64/traces/sim-sqrshl-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshl-4h-trace-a64.h b/test/a64/traces/sim-sqrshl-4h-trace-a64.h index 34720d61..e93179d8 100644 --- a/test/a64/traces/sim-sqrshl-4h-trace-a64.h +++ b/test/a64/traces/sim-sqrshl-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshl-4s-trace-a64.h b/test/a64/traces/sim-sqrshl-4s-trace-a64.h index 20071025..a9904545 100644 --- a/test/a64/traces/sim-sqrshl-4s-trace-a64.h +++ b/test/a64/traces/sim-sqrshl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshl-8b-trace-a64.h b/test/a64/traces/sim-sqrshl-8b-trace-a64.h index 5e10ea97..78468cd9 100644 --- a/test/a64/traces/sim-sqrshl-8b-trace-a64.h +++ b/test/a64/traces/sim-sqrshl-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshl-8h-trace-a64.h b/test/a64/traces/sim-sqrshl-8h-trace-a64.h index 270950d6..2dbe4fb2 100644 --- a/test/a64/traces/sim-sqrshl-8h-trace-a64.h +++ b/test/a64/traces/sim-sqrshl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshl-b-trace-a64.h b/test/a64/traces/sim-sqrshl-b-trace-a64.h index efb86721..c9b123c5 100644 --- a/test/a64/traces/sim-sqrshl-b-trace-a64.h +++ b/test/a64/traces/sim-sqrshl-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshl-d-trace-a64.h b/test/a64/traces/sim-sqrshl-d-trace-a64.h index 4edafe68..b3fe9790 100644 --- a/test/a64/traces/sim-sqrshl-d-trace-a64.h +++ b/test/a64/traces/sim-sqrshl-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshl-h-trace-a64.h b/test/a64/traces/sim-sqrshl-h-trace-a64.h index 46f2e85d..94dbe5b9 100644 --- a/test/a64/traces/sim-sqrshl-h-trace-a64.h +++ b/test/a64/traces/sim-sqrshl-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshl-s-trace-a64.h b/test/a64/traces/sim-sqrshl-s-trace-a64.h index 3d049480..f51e0ad8 100644 --- a/test/a64/traces/sim-sqrshl-s-trace-a64.h +++ b/test/a64/traces/sim-sqrshl-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrn-2s-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrn-2s-2opimm-trace-a64.h index e78c176f..6a8f0e9e 100644 --- a/test/a64/traces/sim-sqrshrn-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrn-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrn-4h-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrn-4h-2opimm-trace-a64.h index 5b1101f9..904fa1ff 100644 --- a/test/a64/traces/sim-sqrshrn-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrn-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrn-8b-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrn-8b-2opimm-trace-a64.h index 15d942de..0362bdea 100644 --- a/test/a64/traces/sim-sqrshrn-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrn-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrn-b-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrn-b-2opimm-trace-a64.h index fcb807d8..d26c9bc4 100644 --- a/test/a64/traces/sim-sqrshrn-b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrn-b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrn-h-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrn-h-2opimm-trace-a64.h index 12464ebf..b033e17e 100644 --- a/test/a64/traces/sim-sqrshrn-h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrn-h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrn-s-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrn-s-2opimm-trace-a64.h index 355c9a77..1a076848 100644 --- a/test/a64/traces/sim-sqrshrn-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrn-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrn2-16b-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrn2-16b-2opimm-trace-a64.h index a7bf243f..95905e4b 100644 --- a/test/a64/traces/sim-sqrshrn2-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrn2-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrn2-4s-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrn2-4s-2opimm-trace-a64.h index 68fd20eb..8dd1076c 100644 --- a/test/a64/traces/sim-sqrshrn2-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrn2-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrn2-8h-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrn2-8h-2opimm-trace-a64.h index f476c527..dbad8ef5 100644 --- a/test/a64/traces/sim-sqrshrn2-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrn2-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrun-2s-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrun-2s-2opimm-trace-a64.h index 321c75e7..debe901b 100644 --- a/test/a64/traces/sim-sqrshrun-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrun-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrun-4h-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrun-4h-2opimm-trace-a64.h index 2f573175..3539f79b 100644 --- a/test/a64/traces/sim-sqrshrun-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrun-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrun-8b-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrun-8b-2opimm-trace-a64.h index 4d690ead..3bc936d9 100644 --- a/test/a64/traces/sim-sqrshrun-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrun-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrun-b-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrun-b-2opimm-trace-a64.h index 73e9ba42..288a26bd 100644 --- a/test/a64/traces/sim-sqrshrun-b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrun-b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrun-h-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrun-h-2opimm-trace-a64.h index 6d93ff59..7723e0fc 100644 --- a/test/a64/traces/sim-sqrshrun-h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrun-h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrun-s-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrun-s-2opimm-trace-a64.h index 5a6e863f..e7c0238f 100644 --- a/test/a64/traces/sim-sqrshrun-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrun-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrun2-16b-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrun2-16b-2opimm-trace-a64.h index 9718dc12..c647c5b6 100644 --- a/test/a64/traces/sim-sqrshrun2-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrun2-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrun2-4s-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrun2-4s-2opimm-trace-a64.h index cd56e8c9..5038b413 100644 --- a/test/a64/traces/sim-sqrshrun2-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrun2-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqrshrun2-8h-2opimm-trace-a64.h b/test/a64/traces/sim-sqrshrun2-8h-2opimm-trace-a64.h index e4f81d05..0ac441b9 100644 --- a/test/a64/traces/sim-sqrshrun2-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqrshrun2-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-16b-2opimm-trace-a64.h b/test/a64/traces/sim-sqshl-16b-2opimm-trace-a64.h index eaf120ac..ff1adbf2 100644 --- a/test/a64/traces/sim-sqshl-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshl-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-16b-trace-a64.h b/test/a64/traces/sim-sqshl-16b-trace-a64.h index 90b1f705..778bef67 100644 --- a/test/a64/traces/sim-sqshl-16b-trace-a64.h +++ b/test/a64/traces/sim-sqshl-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-2d-2opimm-trace-a64.h b/test/a64/traces/sim-sqshl-2d-2opimm-trace-a64.h index ca812f7f..f00c3787 100644 --- a/test/a64/traces/sim-sqshl-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshl-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-2d-trace-a64.h b/test/a64/traces/sim-sqshl-2d-trace-a64.h index f0e06392..9df0b9dd 100644 --- a/test/a64/traces/sim-sqshl-2d-trace-a64.h +++ b/test/a64/traces/sim-sqshl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-2s-2opimm-trace-a64.h b/test/a64/traces/sim-sqshl-2s-2opimm-trace-a64.h index 79699038..88bf9c62 100644 --- a/test/a64/traces/sim-sqshl-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshl-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-2s-trace-a64.h b/test/a64/traces/sim-sqshl-2s-trace-a64.h index ce633edd..d89d9086 100644 --- a/test/a64/traces/sim-sqshl-2s-trace-a64.h +++ b/test/a64/traces/sim-sqshl-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-4h-2opimm-trace-a64.h b/test/a64/traces/sim-sqshl-4h-2opimm-trace-a64.h index bdf24a7d..664293a6 100644 --- a/test/a64/traces/sim-sqshl-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshl-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-4h-trace-a64.h b/test/a64/traces/sim-sqshl-4h-trace-a64.h index 078f8ec1..35866af5 100644 --- a/test/a64/traces/sim-sqshl-4h-trace-a64.h +++ b/test/a64/traces/sim-sqshl-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-4s-2opimm-trace-a64.h b/test/a64/traces/sim-sqshl-4s-2opimm-trace-a64.h index 40c3e3cb..8035632e 100644 --- a/test/a64/traces/sim-sqshl-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshl-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-4s-trace-a64.h b/test/a64/traces/sim-sqshl-4s-trace-a64.h index c4c4fa86..d037d229 100644 --- a/test/a64/traces/sim-sqshl-4s-trace-a64.h +++ b/test/a64/traces/sim-sqshl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-8b-2opimm-trace-a64.h b/test/a64/traces/sim-sqshl-8b-2opimm-trace-a64.h index 5410eab2..2f5c4486 100644 --- a/test/a64/traces/sim-sqshl-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshl-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-8b-trace-a64.h b/test/a64/traces/sim-sqshl-8b-trace-a64.h index 8639ec9d..f0402d79 100644 --- a/test/a64/traces/sim-sqshl-8b-trace-a64.h +++ b/test/a64/traces/sim-sqshl-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-8h-2opimm-trace-a64.h b/test/a64/traces/sim-sqshl-8h-2opimm-trace-a64.h index 4e4a7fe2..90eefd26 100644 --- a/test/a64/traces/sim-sqshl-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshl-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-8h-trace-a64.h b/test/a64/traces/sim-sqshl-8h-trace-a64.h index 98407f2b..17b0d3a2 100644 --- a/test/a64/traces/sim-sqshl-8h-trace-a64.h +++ b/test/a64/traces/sim-sqshl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-b-2opimm-trace-a64.h b/test/a64/traces/sim-sqshl-b-2opimm-trace-a64.h index 9edbc915..8106176b 100644 --- a/test/a64/traces/sim-sqshl-b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshl-b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-b-trace-a64.h b/test/a64/traces/sim-sqshl-b-trace-a64.h index ceabf62e..41c6097a 100644 --- a/test/a64/traces/sim-sqshl-b-trace-a64.h +++ b/test/a64/traces/sim-sqshl-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-d-2opimm-trace-a64.h b/test/a64/traces/sim-sqshl-d-2opimm-trace-a64.h index 58f82239..7a73959a 100644 --- a/test/a64/traces/sim-sqshl-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshl-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-d-trace-a64.h b/test/a64/traces/sim-sqshl-d-trace-a64.h index 2a920062..9f63ef7f 100644 --- a/test/a64/traces/sim-sqshl-d-trace-a64.h +++ b/test/a64/traces/sim-sqshl-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-h-2opimm-trace-a64.h b/test/a64/traces/sim-sqshl-h-2opimm-trace-a64.h index 5d284f71..adb02c4f 100644 --- a/test/a64/traces/sim-sqshl-h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshl-h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-h-trace-a64.h b/test/a64/traces/sim-sqshl-h-trace-a64.h index 31400921..c5526219 100644 --- a/test/a64/traces/sim-sqshl-h-trace-a64.h +++ b/test/a64/traces/sim-sqshl-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-s-2opimm-trace-a64.h b/test/a64/traces/sim-sqshl-s-2opimm-trace-a64.h index a9563d6c..b9c83912 100644 --- a/test/a64/traces/sim-sqshl-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshl-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshl-s-trace-a64.h b/test/a64/traces/sim-sqshl-s-trace-a64.h index 6137c33e..2fdfa5b5 100644 --- a/test/a64/traces/sim-sqshl-s-trace-a64.h +++ b/test/a64/traces/sim-sqshl-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshlu-16b-2opimm-trace-a64.h b/test/a64/traces/sim-sqshlu-16b-2opimm-trace-a64.h index 4a4c669e..a68b1896 100644 --- a/test/a64/traces/sim-sqshlu-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshlu-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshlu-2d-2opimm-trace-a64.h b/test/a64/traces/sim-sqshlu-2d-2opimm-trace-a64.h index 5304240d..b07ff651 100644 --- a/test/a64/traces/sim-sqshlu-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshlu-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshlu-2s-2opimm-trace-a64.h b/test/a64/traces/sim-sqshlu-2s-2opimm-trace-a64.h index ccc30472..a01fd38a 100644 --- a/test/a64/traces/sim-sqshlu-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshlu-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshlu-4h-2opimm-trace-a64.h b/test/a64/traces/sim-sqshlu-4h-2opimm-trace-a64.h index efdd93cc..cebc2342 100644 --- a/test/a64/traces/sim-sqshlu-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshlu-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshlu-4s-2opimm-trace-a64.h b/test/a64/traces/sim-sqshlu-4s-2opimm-trace-a64.h index b4210052..af96e2cb 100644 --- a/test/a64/traces/sim-sqshlu-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshlu-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshlu-8b-2opimm-trace-a64.h b/test/a64/traces/sim-sqshlu-8b-2opimm-trace-a64.h index b208fe2c..1dee4cd6 100644 --- a/test/a64/traces/sim-sqshlu-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshlu-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshlu-8h-2opimm-trace-a64.h b/test/a64/traces/sim-sqshlu-8h-2opimm-trace-a64.h index 58e14b68..3f6f5efc 100644 --- a/test/a64/traces/sim-sqshlu-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshlu-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshlu-b-2opimm-trace-a64.h b/test/a64/traces/sim-sqshlu-b-2opimm-trace-a64.h index dd62cd87..3cdab4af 100644 --- a/test/a64/traces/sim-sqshlu-b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshlu-b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshlu-d-2opimm-trace-a64.h b/test/a64/traces/sim-sqshlu-d-2opimm-trace-a64.h index 9b3e472a..58941be7 100644 --- a/test/a64/traces/sim-sqshlu-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshlu-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshlu-h-2opimm-trace-a64.h b/test/a64/traces/sim-sqshlu-h-2opimm-trace-a64.h index 0f92352d..85128fcd 100644 --- a/test/a64/traces/sim-sqshlu-h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshlu-h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshlu-s-2opimm-trace-a64.h b/test/a64/traces/sim-sqshlu-s-2opimm-trace-a64.h index 7ce436b7..bcd4546a 100644 --- a/test/a64/traces/sim-sqshlu-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshlu-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrn-2s-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrn-2s-2opimm-trace-a64.h index 27480949..51c9d27b 100644 --- a/test/a64/traces/sim-sqshrn-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrn-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrn-4h-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrn-4h-2opimm-trace-a64.h index 5f5577eb..3a173958 100644 --- a/test/a64/traces/sim-sqshrn-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrn-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrn-8b-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrn-8b-2opimm-trace-a64.h index 78933720..cba9f8ca 100644 --- a/test/a64/traces/sim-sqshrn-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrn-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrn-b-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrn-b-2opimm-trace-a64.h index 8c1a0d61..d5609c9d 100644 --- a/test/a64/traces/sim-sqshrn-b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrn-b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrn-h-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrn-h-2opimm-trace-a64.h index 874a6f1a..a1ff41c6 100644 --- a/test/a64/traces/sim-sqshrn-h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrn-h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrn-s-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrn-s-2opimm-trace-a64.h index 9d1471a0..a4fd9833 100644 --- a/test/a64/traces/sim-sqshrn-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrn-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrn2-16b-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrn2-16b-2opimm-trace-a64.h index b98d0ee2..bff5cd6e 100644 --- a/test/a64/traces/sim-sqshrn2-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrn2-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrn2-4s-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrn2-4s-2opimm-trace-a64.h index 47a0d502..23863a11 100644 --- a/test/a64/traces/sim-sqshrn2-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrn2-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrn2-8h-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrn2-8h-2opimm-trace-a64.h index 4491a26c..fef87a8d 100644 --- a/test/a64/traces/sim-sqshrn2-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrn2-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrun-2s-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrun-2s-2opimm-trace-a64.h index 03c00fa2..36f376cb 100644 --- a/test/a64/traces/sim-sqshrun-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrun-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrun-4h-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrun-4h-2opimm-trace-a64.h index 2d4971eb..d44a69a9 100644 --- a/test/a64/traces/sim-sqshrun-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrun-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrun-8b-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrun-8b-2opimm-trace-a64.h index 691a9181..7d03eb1c 100644 --- a/test/a64/traces/sim-sqshrun-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrun-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrun-b-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrun-b-2opimm-trace-a64.h index 4ad7add8..80dee542 100644 --- a/test/a64/traces/sim-sqshrun-b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrun-b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrun-h-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrun-h-2opimm-trace-a64.h index 6f5718e6..bf6cc694 100644 --- a/test/a64/traces/sim-sqshrun-h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrun-h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrun-s-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrun-s-2opimm-trace-a64.h index 84a3ead4..cb8a5027 100644 --- a/test/a64/traces/sim-sqshrun-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrun-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrun2-16b-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrun2-16b-2opimm-trace-a64.h index e7cc89a1..2c7f9455 100644 --- a/test/a64/traces/sim-sqshrun2-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrun2-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrun2-4s-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrun2-4s-2opimm-trace-a64.h index b264f9f9..51751468 100644 --- a/test/a64/traces/sim-sqshrun2-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrun2-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqshrun2-8h-2opimm-trace-a64.h b/test/a64/traces/sim-sqshrun2-8h-2opimm-trace-a64.h index f68fe9fa..b8af360e 100644 --- a/test/a64/traces/sim-sqshrun2-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sqshrun2-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqsub-16b-trace-a64.h b/test/a64/traces/sim-sqsub-16b-trace-a64.h index 506c0a31..acf0a49f 100644 --- a/test/a64/traces/sim-sqsub-16b-trace-a64.h +++ b/test/a64/traces/sim-sqsub-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqsub-2d-trace-a64.h b/test/a64/traces/sim-sqsub-2d-trace-a64.h index 01f95770..e58dced3 100644 --- a/test/a64/traces/sim-sqsub-2d-trace-a64.h +++ b/test/a64/traces/sim-sqsub-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqsub-2s-trace-a64.h b/test/a64/traces/sim-sqsub-2s-trace-a64.h index aa64d1ad..57e6c61f 100644 --- a/test/a64/traces/sim-sqsub-2s-trace-a64.h +++ b/test/a64/traces/sim-sqsub-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqsub-4h-trace-a64.h b/test/a64/traces/sim-sqsub-4h-trace-a64.h index 66d70d76..05388bac 100644 --- a/test/a64/traces/sim-sqsub-4h-trace-a64.h +++ b/test/a64/traces/sim-sqsub-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqsub-4s-trace-a64.h b/test/a64/traces/sim-sqsub-4s-trace-a64.h index f65de688..2eca3d49 100644 --- a/test/a64/traces/sim-sqsub-4s-trace-a64.h +++ b/test/a64/traces/sim-sqsub-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqsub-8b-trace-a64.h b/test/a64/traces/sim-sqsub-8b-trace-a64.h index 7a734cbb..2f5ce4c4 100644 --- a/test/a64/traces/sim-sqsub-8b-trace-a64.h +++ b/test/a64/traces/sim-sqsub-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqsub-8h-trace-a64.h b/test/a64/traces/sim-sqsub-8h-trace-a64.h index e94f0a61..23bc1e83 100644 --- a/test/a64/traces/sim-sqsub-8h-trace-a64.h +++ b/test/a64/traces/sim-sqsub-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqsub-b-trace-a64.h b/test/a64/traces/sim-sqsub-b-trace-a64.h index 09035765..1b7c2216 100644 --- a/test/a64/traces/sim-sqsub-b-trace-a64.h +++ b/test/a64/traces/sim-sqsub-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqsub-d-trace-a64.h b/test/a64/traces/sim-sqsub-d-trace-a64.h index fc36ff3e..4f93861e 100644 --- a/test/a64/traces/sim-sqsub-d-trace-a64.h +++ b/test/a64/traces/sim-sqsub-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqsub-h-trace-a64.h b/test/a64/traces/sim-sqsub-h-trace-a64.h index 17a02639..68aef532 100644 --- a/test/a64/traces/sim-sqsub-h-trace-a64.h +++ b/test/a64/traces/sim-sqsub-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqsub-s-trace-a64.h b/test/a64/traces/sim-sqsub-s-trace-a64.h index 5999dc3b..1ae965ee 100644 --- a/test/a64/traces/sim-sqsub-s-trace-a64.h +++ b/test/a64/traces/sim-sqsub-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtn-2s-trace-a64.h b/test/a64/traces/sim-sqxtn-2s-trace-a64.h index 6c2ac718..09255a09 100644 --- a/test/a64/traces/sim-sqxtn-2s-trace-a64.h +++ b/test/a64/traces/sim-sqxtn-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtn-4h-trace-a64.h b/test/a64/traces/sim-sqxtn-4h-trace-a64.h index 31730882..8c3804d7 100644 --- a/test/a64/traces/sim-sqxtn-4h-trace-a64.h +++ b/test/a64/traces/sim-sqxtn-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtn-8b-trace-a64.h b/test/a64/traces/sim-sqxtn-8b-trace-a64.h index a8771a68..e038c582 100644 --- a/test/a64/traces/sim-sqxtn-8b-trace-a64.h +++ b/test/a64/traces/sim-sqxtn-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtn-b-trace-a64.h b/test/a64/traces/sim-sqxtn-b-trace-a64.h index 8491177d..4e31b2f0 100644 --- a/test/a64/traces/sim-sqxtn-b-trace-a64.h +++ b/test/a64/traces/sim-sqxtn-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtn-h-trace-a64.h b/test/a64/traces/sim-sqxtn-h-trace-a64.h index 0eaae7f0..462c9d17 100644 --- a/test/a64/traces/sim-sqxtn-h-trace-a64.h +++ b/test/a64/traces/sim-sqxtn-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtn-s-trace-a64.h b/test/a64/traces/sim-sqxtn-s-trace-a64.h index 3af19756..66736542 100644 --- a/test/a64/traces/sim-sqxtn-s-trace-a64.h +++ b/test/a64/traces/sim-sqxtn-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtn2-16b-trace-a64.h b/test/a64/traces/sim-sqxtn2-16b-trace-a64.h index f5855562..4aa4eaeb 100644 --- a/test/a64/traces/sim-sqxtn2-16b-trace-a64.h +++ b/test/a64/traces/sim-sqxtn2-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtn2-4s-trace-a64.h b/test/a64/traces/sim-sqxtn2-4s-trace-a64.h index 79596c35..0d9cca73 100644 --- a/test/a64/traces/sim-sqxtn2-4s-trace-a64.h +++ b/test/a64/traces/sim-sqxtn2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtn2-8h-trace-a64.h b/test/a64/traces/sim-sqxtn2-8h-trace-a64.h index c05100aa..c83bc12e 100644 --- a/test/a64/traces/sim-sqxtn2-8h-trace-a64.h +++ b/test/a64/traces/sim-sqxtn2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtun-2s-trace-a64.h b/test/a64/traces/sim-sqxtun-2s-trace-a64.h index 3bb7b9e9..9006fff4 100644 --- a/test/a64/traces/sim-sqxtun-2s-trace-a64.h +++ b/test/a64/traces/sim-sqxtun-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtun-4h-trace-a64.h b/test/a64/traces/sim-sqxtun-4h-trace-a64.h index b9ed73af..57f6f794 100644 --- a/test/a64/traces/sim-sqxtun-4h-trace-a64.h +++ b/test/a64/traces/sim-sqxtun-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtun-8b-trace-a64.h b/test/a64/traces/sim-sqxtun-8b-trace-a64.h index 7221366e..50dc1cda 100644 --- a/test/a64/traces/sim-sqxtun-8b-trace-a64.h +++ b/test/a64/traces/sim-sqxtun-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtun-b-trace-a64.h b/test/a64/traces/sim-sqxtun-b-trace-a64.h index 16501ea0..257f5ae3 100644 --- a/test/a64/traces/sim-sqxtun-b-trace-a64.h +++ b/test/a64/traces/sim-sqxtun-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtun-h-trace-a64.h b/test/a64/traces/sim-sqxtun-h-trace-a64.h index c653c58a..d022aa52 100644 --- a/test/a64/traces/sim-sqxtun-h-trace-a64.h +++ b/test/a64/traces/sim-sqxtun-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtun-s-trace-a64.h b/test/a64/traces/sim-sqxtun-s-trace-a64.h index 1babed64..f7f31ee2 100644 --- a/test/a64/traces/sim-sqxtun-s-trace-a64.h +++ b/test/a64/traces/sim-sqxtun-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtun2-16b-trace-a64.h b/test/a64/traces/sim-sqxtun2-16b-trace-a64.h index 54995228..efb0c45c 100644 --- a/test/a64/traces/sim-sqxtun2-16b-trace-a64.h +++ b/test/a64/traces/sim-sqxtun2-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtun2-4s-trace-a64.h b/test/a64/traces/sim-sqxtun2-4s-trace-a64.h index da5c682c..136f9e7d 100644 --- a/test/a64/traces/sim-sqxtun2-4s-trace-a64.h +++ b/test/a64/traces/sim-sqxtun2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sqxtun2-8h-trace-a64.h b/test/a64/traces/sim-sqxtun2-8h-trace-a64.h index c0c51627..cec02fbe 100644 --- a/test/a64/traces/sim-sqxtun2-8h-trace-a64.h +++ b/test/a64/traces/sim-sqxtun2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srhadd-16b-trace-a64.h b/test/a64/traces/sim-srhadd-16b-trace-a64.h index f59a5b84..1cbf2422 100644 --- a/test/a64/traces/sim-srhadd-16b-trace-a64.h +++ b/test/a64/traces/sim-srhadd-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srhadd-2s-trace-a64.h b/test/a64/traces/sim-srhadd-2s-trace-a64.h index 1b0d9d25..e2b19d84 100644 --- a/test/a64/traces/sim-srhadd-2s-trace-a64.h +++ b/test/a64/traces/sim-srhadd-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srhadd-4h-trace-a64.h b/test/a64/traces/sim-srhadd-4h-trace-a64.h index 488ebc82..2c2593fd 100644 --- a/test/a64/traces/sim-srhadd-4h-trace-a64.h +++ b/test/a64/traces/sim-srhadd-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srhadd-4s-trace-a64.h b/test/a64/traces/sim-srhadd-4s-trace-a64.h index 3a33abed..df14525c 100644 --- a/test/a64/traces/sim-srhadd-4s-trace-a64.h +++ b/test/a64/traces/sim-srhadd-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srhadd-8b-trace-a64.h b/test/a64/traces/sim-srhadd-8b-trace-a64.h index 38eaaee1..adc1ac77 100644 --- a/test/a64/traces/sim-srhadd-8b-trace-a64.h +++ b/test/a64/traces/sim-srhadd-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srhadd-8h-trace-a64.h b/test/a64/traces/sim-srhadd-8h-trace-a64.h index feed3b9e..956066fa 100644 --- a/test/a64/traces/sim-srhadd-8h-trace-a64.h +++ b/test/a64/traces/sim-srhadd-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sri-16b-2opimm-trace-a64.h b/test/a64/traces/sim-sri-16b-2opimm-trace-a64.h index b35cfa07..059152f3 100644 --- a/test/a64/traces/sim-sri-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sri-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sri-2d-2opimm-trace-a64.h b/test/a64/traces/sim-sri-2d-2opimm-trace-a64.h index 1c88c687..7631259b 100644 --- a/test/a64/traces/sim-sri-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sri-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sri-2s-2opimm-trace-a64.h b/test/a64/traces/sim-sri-2s-2opimm-trace-a64.h index f627cbc8..6bf9d9e3 100644 --- a/test/a64/traces/sim-sri-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sri-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sri-4h-2opimm-trace-a64.h b/test/a64/traces/sim-sri-4h-2opimm-trace-a64.h index 774cac70..d88977d6 100644 --- a/test/a64/traces/sim-sri-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sri-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sri-4s-2opimm-trace-a64.h b/test/a64/traces/sim-sri-4s-2opimm-trace-a64.h index d563c869..aec16975 100644 --- a/test/a64/traces/sim-sri-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sri-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sri-8b-2opimm-trace-a64.h b/test/a64/traces/sim-sri-8b-2opimm-trace-a64.h index 9b38a568..5b6a8f56 100644 --- a/test/a64/traces/sim-sri-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sri-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sri-8h-2opimm-trace-a64.h b/test/a64/traces/sim-sri-8h-2opimm-trace-a64.h index ec180542..6accb8d7 100644 --- a/test/a64/traces/sim-sri-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sri-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sri-d-2opimm-trace-a64.h b/test/a64/traces/sim-sri-d-2opimm-trace-a64.h index b58bc899..3fe9a7da 100644 --- a/test/a64/traces/sim-sri-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sri-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshl-16b-trace-a64.h b/test/a64/traces/sim-srshl-16b-trace-a64.h index de5e0d17..36454e17 100644 --- a/test/a64/traces/sim-srshl-16b-trace-a64.h +++ b/test/a64/traces/sim-srshl-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshl-2d-trace-a64.h b/test/a64/traces/sim-srshl-2d-trace-a64.h index 99d390eb..86591cfd 100644 --- a/test/a64/traces/sim-srshl-2d-trace-a64.h +++ b/test/a64/traces/sim-srshl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshl-2s-trace-a64.h b/test/a64/traces/sim-srshl-2s-trace-a64.h index ce2c326b..8b433d51 100644 --- a/test/a64/traces/sim-srshl-2s-trace-a64.h +++ b/test/a64/traces/sim-srshl-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshl-4h-trace-a64.h b/test/a64/traces/sim-srshl-4h-trace-a64.h index f21f4fa7..059a3dff 100644 --- a/test/a64/traces/sim-srshl-4h-trace-a64.h +++ b/test/a64/traces/sim-srshl-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshl-4s-trace-a64.h b/test/a64/traces/sim-srshl-4s-trace-a64.h index ef4f6f51..5e44a9f7 100644 --- a/test/a64/traces/sim-srshl-4s-trace-a64.h +++ b/test/a64/traces/sim-srshl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshl-8b-trace-a64.h b/test/a64/traces/sim-srshl-8b-trace-a64.h index c42141c9..cda79428 100644 --- a/test/a64/traces/sim-srshl-8b-trace-a64.h +++ b/test/a64/traces/sim-srshl-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshl-8h-trace-a64.h b/test/a64/traces/sim-srshl-8h-trace-a64.h index aaf660e1..43fc114f 100644 --- a/test/a64/traces/sim-srshl-8h-trace-a64.h +++ b/test/a64/traces/sim-srshl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshl-d-trace-a64.h b/test/a64/traces/sim-srshl-d-trace-a64.h index 58b2cb3c..38c69266 100644 --- a/test/a64/traces/sim-srshl-d-trace-a64.h +++ b/test/a64/traces/sim-srshl-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshr-16b-2opimm-trace-a64.h b/test/a64/traces/sim-srshr-16b-2opimm-trace-a64.h index 998a1922..9d8710f7 100644 --- a/test/a64/traces/sim-srshr-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srshr-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshr-2d-2opimm-trace-a64.h b/test/a64/traces/sim-srshr-2d-2opimm-trace-a64.h index 3f3abd99..8970eb52 100644 --- a/test/a64/traces/sim-srshr-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srshr-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshr-2s-2opimm-trace-a64.h b/test/a64/traces/sim-srshr-2s-2opimm-trace-a64.h index 533cda50..3bb36819 100644 --- a/test/a64/traces/sim-srshr-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srshr-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshr-4h-2opimm-trace-a64.h b/test/a64/traces/sim-srshr-4h-2opimm-trace-a64.h index b8b903c2..6e886b05 100644 --- a/test/a64/traces/sim-srshr-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srshr-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshr-4s-2opimm-trace-a64.h b/test/a64/traces/sim-srshr-4s-2opimm-trace-a64.h index bc313e9a..0f9b353c 100644 --- a/test/a64/traces/sim-srshr-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srshr-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshr-8b-2opimm-trace-a64.h b/test/a64/traces/sim-srshr-8b-2opimm-trace-a64.h index c8dab33a..9f6f779b 100644 --- a/test/a64/traces/sim-srshr-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srshr-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshr-8h-2opimm-trace-a64.h b/test/a64/traces/sim-srshr-8h-2opimm-trace-a64.h index a54f6205..d2dad19e 100644 --- a/test/a64/traces/sim-srshr-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srshr-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srshr-d-2opimm-trace-a64.h b/test/a64/traces/sim-srshr-d-2opimm-trace-a64.h index a0a0ee32..367b1cdd 100644 --- a/test/a64/traces/sim-srshr-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srshr-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srsra-16b-2opimm-trace-a64.h b/test/a64/traces/sim-srsra-16b-2opimm-trace-a64.h index 9b32579c..5af95960 100644 --- a/test/a64/traces/sim-srsra-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srsra-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srsra-2d-2opimm-trace-a64.h b/test/a64/traces/sim-srsra-2d-2opimm-trace-a64.h index 41505d20..6cd53161 100644 --- a/test/a64/traces/sim-srsra-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srsra-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srsra-2s-2opimm-trace-a64.h b/test/a64/traces/sim-srsra-2s-2opimm-trace-a64.h index 4cb0f07f..dfdb96ea 100644 --- a/test/a64/traces/sim-srsra-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srsra-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srsra-4h-2opimm-trace-a64.h b/test/a64/traces/sim-srsra-4h-2opimm-trace-a64.h index 774e2157..076f660c 100644 --- a/test/a64/traces/sim-srsra-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srsra-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srsra-4s-2opimm-trace-a64.h b/test/a64/traces/sim-srsra-4s-2opimm-trace-a64.h index 7018a898..ad9b675f 100644 --- a/test/a64/traces/sim-srsra-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srsra-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srsra-8b-2opimm-trace-a64.h b/test/a64/traces/sim-srsra-8b-2opimm-trace-a64.h index 2f9d52db..23dd51a3 100644 --- a/test/a64/traces/sim-srsra-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srsra-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srsra-8h-2opimm-trace-a64.h b/test/a64/traces/sim-srsra-8h-2opimm-trace-a64.h index 44093715..5f027765 100644 --- a/test/a64/traces/sim-srsra-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srsra-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-srsra-d-2opimm-trace-a64.h b/test/a64/traces/sim-srsra-d-2opimm-trace-a64.h index c0710f1f..b9795d50 100644 --- a/test/a64/traces/sim-srsra-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-srsra-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshl-16b-trace-a64.h b/test/a64/traces/sim-sshl-16b-trace-a64.h index 69558116..5cc4d915 100644 --- a/test/a64/traces/sim-sshl-16b-trace-a64.h +++ b/test/a64/traces/sim-sshl-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshl-2d-trace-a64.h b/test/a64/traces/sim-sshl-2d-trace-a64.h index e2645bc9..badcf175 100644 --- a/test/a64/traces/sim-sshl-2d-trace-a64.h +++ b/test/a64/traces/sim-sshl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshl-2s-trace-a64.h b/test/a64/traces/sim-sshl-2s-trace-a64.h index ff80f97e..4538f9c1 100644 --- a/test/a64/traces/sim-sshl-2s-trace-a64.h +++ b/test/a64/traces/sim-sshl-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshl-4h-trace-a64.h b/test/a64/traces/sim-sshl-4h-trace-a64.h index 84378da8..a3639406 100644 --- a/test/a64/traces/sim-sshl-4h-trace-a64.h +++ b/test/a64/traces/sim-sshl-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshl-4s-trace-a64.h b/test/a64/traces/sim-sshl-4s-trace-a64.h index 92306bb3..c1627b51 100644 --- a/test/a64/traces/sim-sshl-4s-trace-a64.h +++ b/test/a64/traces/sim-sshl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshl-8b-trace-a64.h b/test/a64/traces/sim-sshl-8b-trace-a64.h index 92cea1fe..8f0b744d 100644 --- a/test/a64/traces/sim-sshl-8b-trace-a64.h +++ b/test/a64/traces/sim-sshl-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshl-8h-trace-a64.h b/test/a64/traces/sim-sshl-8h-trace-a64.h index 626ff832..46b18ca6 100644 --- a/test/a64/traces/sim-sshl-8h-trace-a64.h +++ b/test/a64/traces/sim-sshl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshl-d-trace-a64.h b/test/a64/traces/sim-sshl-d-trace-a64.h index 73b57ad4..acf05428 100644 --- a/test/a64/traces/sim-sshl-d-trace-a64.h +++ b/test/a64/traces/sim-sshl-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshll-2d-2opimm-trace-a64.h b/test/a64/traces/sim-sshll-2d-2opimm-trace-a64.h index b5fabad5..03cda2e5 100644 --- a/test/a64/traces/sim-sshll-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshll-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshll-4s-2opimm-trace-a64.h b/test/a64/traces/sim-sshll-4s-2opimm-trace-a64.h index ec38c456..ad12fda7 100644 --- a/test/a64/traces/sim-sshll-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshll-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshll-8h-2opimm-trace-a64.h b/test/a64/traces/sim-sshll-8h-2opimm-trace-a64.h index eac75532..aba476e1 100644 --- a/test/a64/traces/sim-sshll-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshll-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshll2-2d-2opimm-trace-a64.h b/test/a64/traces/sim-sshll2-2d-2opimm-trace-a64.h index fe7382ce..d5acaead 100644 --- a/test/a64/traces/sim-sshll2-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshll2-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshll2-4s-2opimm-trace-a64.h b/test/a64/traces/sim-sshll2-4s-2opimm-trace-a64.h index 2e96c926..6b82223b 100644 --- a/test/a64/traces/sim-sshll2-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshll2-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshll2-8h-2opimm-trace-a64.h b/test/a64/traces/sim-sshll2-8h-2opimm-trace-a64.h index 8a9686a9..6803ad16 100644 --- a/test/a64/traces/sim-sshll2-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshll2-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshr-16b-2opimm-trace-a64.h b/test/a64/traces/sim-sshr-16b-2opimm-trace-a64.h index 630f57cf..f7c0e71f 100644 --- a/test/a64/traces/sim-sshr-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshr-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshr-2d-2opimm-trace-a64.h b/test/a64/traces/sim-sshr-2d-2opimm-trace-a64.h index f833f81d..46440937 100644 --- a/test/a64/traces/sim-sshr-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshr-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshr-2s-2opimm-trace-a64.h b/test/a64/traces/sim-sshr-2s-2opimm-trace-a64.h index cd300910..56f1245e 100644 --- a/test/a64/traces/sim-sshr-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshr-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshr-4h-2opimm-trace-a64.h b/test/a64/traces/sim-sshr-4h-2opimm-trace-a64.h index 3611c15b..9797d688 100644 --- a/test/a64/traces/sim-sshr-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshr-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshr-4s-2opimm-trace-a64.h b/test/a64/traces/sim-sshr-4s-2opimm-trace-a64.h index 6077dc54..2146cf68 100644 --- a/test/a64/traces/sim-sshr-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshr-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshr-8b-2opimm-trace-a64.h b/test/a64/traces/sim-sshr-8b-2opimm-trace-a64.h index a2907d29..d15f608e 100644 --- a/test/a64/traces/sim-sshr-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshr-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshr-8h-2opimm-trace-a64.h b/test/a64/traces/sim-sshr-8h-2opimm-trace-a64.h index 707a9bce..91556401 100644 --- a/test/a64/traces/sim-sshr-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshr-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sshr-d-2opimm-trace-a64.h b/test/a64/traces/sim-sshr-d-2opimm-trace-a64.h index 938a7229..ce8e0ff9 100644 --- a/test/a64/traces/sim-sshr-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-sshr-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssra-16b-2opimm-trace-a64.h b/test/a64/traces/sim-ssra-16b-2opimm-trace-a64.h index 5e059a57..d8ce467f 100644 --- a/test/a64/traces/sim-ssra-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ssra-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssra-2d-2opimm-trace-a64.h b/test/a64/traces/sim-ssra-2d-2opimm-trace-a64.h index ccfd7133..d6a73aab 100644 --- a/test/a64/traces/sim-ssra-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ssra-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssra-2s-2opimm-trace-a64.h b/test/a64/traces/sim-ssra-2s-2opimm-trace-a64.h index b954507f..f70aea11 100644 --- a/test/a64/traces/sim-ssra-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ssra-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssra-4h-2opimm-trace-a64.h b/test/a64/traces/sim-ssra-4h-2opimm-trace-a64.h index 7f093b10..c446f5c3 100644 --- a/test/a64/traces/sim-ssra-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ssra-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssra-4s-2opimm-trace-a64.h b/test/a64/traces/sim-ssra-4s-2opimm-trace-a64.h index a0344d6a..09095f58 100644 --- a/test/a64/traces/sim-ssra-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ssra-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssra-8b-2opimm-trace-a64.h b/test/a64/traces/sim-ssra-8b-2opimm-trace-a64.h index 0df9f604..6e0254a4 100644 --- a/test/a64/traces/sim-ssra-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ssra-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssra-8h-2opimm-trace-a64.h b/test/a64/traces/sim-ssra-8h-2opimm-trace-a64.h index 579406aa..7d3b2d15 100644 --- a/test/a64/traces/sim-ssra-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ssra-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssra-d-2opimm-trace-a64.h b/test/a64/traces/sim-ssra-d-2opimm-trace-a64.h index 6e5f2b98..8275da05 100644 --- a/test/a64/traces/sim-ssra-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ssra-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssubl-2d-trace-a64.h b/test/a64/traces/sim-ssubl-2d-trace-a64.h index 000ad4d5..f77fa867 100644 --- a/test/a64/traces/sim-ssubl-2d-trace-a64.h +++ b/test/a64/traces/sim-ssubl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssubl-4s-trace-a64.h b/test/a64/traces/sim-ssubl-4s-trace-a64.h index 0de4c15e..a048c64d 100644 --- a/test/a64/traces/sim-ssubl-4s-trace-a64.h +++ b/test/a64/traces/sim-ssubl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssubl-8h-trace-a64.h b/test/a64/traces/sim-ssubl-8h-trace-a64.h index 79bf0ff7..78bb9fc0 100644 --- a/test/a64/traces/sim-ssubl-8h-trace-a64.h +++ b/test/a64/traces/sim-ssubl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssubl2-2d-trace-a64.h b/test/a64/traces/sim-ssubl2-2d-trace-a64.h index 03f8e459..7e1a004c 100644 --- a/test/a64/traces/sim-ssubl2-2d-trace-a64.h +++ b/test/a64/traces/sim-ssubl2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssubl2-4s-trace-a64.h b/test/a64/traces/sim-ssubl2-4s-trace-a64.h index a39c7970..bf372ba5 100644 --- a/test/a64/traces/sim-ssubl2-4s-trace-a64.h +++ b/test/a64/traces/sim-ssubl2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssubl2-8h-trace-a64.h b/test/a64/traces/sim-ssubl2-8h-trace-a64.h index 210e0297..a8b2e74d 100644 --- a/test/a64/traces/sim-ssubl2-8h-trace-a64.h +++ b/test/a64/traces/sim-ssubl2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssubw-2d-trace-a64.h b/test/a64/traces/sim-ssubw-2d-trace-a64.h index ff7395da..9eb60510 100644 --- a/test/a64/traces/sim-ssubw-2d-trace-a64.h +++ b/test/a64/traces/sim-ssubw-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssubw-4s-trace-a64.h b/test/a64/traces/sim-ssubw-4s-trace-a64.h index 355f492b..60508f04 100644 --- a/test/a64/traces/sim-ssubw-4s-trace-a64.h +++ b/test/a64/traces/sim-ssubw-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssubw-8h-trace-a64.h b/test/a64/traces/sim-ssubw-8h-trace-a64.h index c0b18c61..c88625db 100644 --- a/test/a64/traces/sim-ssubw-8h-trace-a64.h +++ b/test/a64/traces/sim-ssubw-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssubw2-2d-trace-a64.h b/test/a64/traces/sim-ssubw2-2d-trace-a64.h index 3836cb26..37c140c0 100644 --- a/test/a64/traces/sim-ssubw2-2d-trace-a64.h +++ b/test/a64/traces/sim-ssubw2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssubw2-4s-trace-a64.h b/test/a64/traces/sim-ssubw2-4s-trace-a64.h index 91dd3cdd..eb8fc8d3 100644 --- a/test/a64/traces/sim-ssubw2-4s-trace-a64.h +++ b/test/a64/traces/sim-ssubw2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ssubw2-8h-trace-a64.h b/test/a64/traces/sim-ssubw2-8h-trace-a64.h index d34f02e5..56f64376 100644 --- a/test/a64/traces/sim-ssubw2-8h-trace-a64.h +++ b/test/a64/traces/sim-ssubw2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sub-16b-trace-a64.h b/test/a64/traces/sim-sub-16b-trace-a64.h index b0fa3331..2b0236b6 100644 --- a/test/a64/traces/sim-sub-16b-trace-a64.h +++ b/test/a64/traces/sim-sub-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sub-2d-trace-a64.h b/test/a64/traces/sim-sub-2d-trace-a64.h index 43c5f355..1be6cdb5 100644 --- a/test/a64/traces/sim-sub-2d-trace-a64.h +++ b/test/a64/traces/sim-sub-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sub-2s-trace-a64.h b/test/a64/traces/sim-sub-2s-trace-a64.h index 560c5893..81913da1 100644 --- a/test/a64/traces/sim-sub-2s-trace-a64.h +++ b/test/a64/traces/sim-sub-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sub-4h-trace-a64.h b/test/a64/traces/sim-sub-4h-trace-a64.h index f7aec505..47842256 100644 --- a/test/a64/traces/sim-sub-4h-trace-a64.h +++ b/test/a64/traces/sim-sub-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sub-4s-trace-a64.h b/test/a64/traces/sim-sub-4s-trace-a64.h index 38ed21b4..7d6903fe 100644 --- a/test/a64/traces/sim-sub-4s-trace-a64.h +++ b/test/a64/traces/sim-sub-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sub-8b-trace-a64.h b/test/a64/traces/sim-sub-8b-trace-a64.h index 3621ff73..3b905669 100644 --- a/test/a64/traces/sim-sub-8b-trace-a64.h +++ b/test/a64/traces/sim-sub-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sub-8h-trace-a64.h b/test/a64/traces/sim-sub-8h-trace-a64.h index 518712c7..8070ae74 100644 --- a/test/a64/traces/sim-sub-8h-trace-a64.h +++ b/test/a64/traces/sim-sub-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-sub-d-trace-a64.h b/test/a64/traces/sim-sub-d-trace-a64.h index 996139a6..462167ce 100644 --- a/test/a64/traces/sim-sub-d-trace-a64.h +++ b/test/a64/traces/sim-sub-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-subhn-2s-trace-a64.h b/test/a64/traces/sim-subhn-2s-trace-a64.h index 87d70d2a..e463664e 100644 --- a/test/a64/traces/sim-subhn-2s-trace-a64.h +++ b/test/a64/traces/sim-subhn-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-subhn-4h-trace-a64.h b/test/a64/traces/sim-subhn-4h-trace-a64.h index 2ec8b0bd..beb41272 100644 --- a/test/a64/traces/sim-subhn-4h-trace-a64.h +++ b/test/a64/traces/sim-subhn-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-subhn-8b-trace-a64.h b/test/a64/traces/sim-subhn-8b-trace-a64.h index 73656e1d..d98b3ca1 100644 --- a/test/a64/traces/sim-subhn-8b-trace-a64.h +++ b/test/a64/traces/sim-subhn-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-subhn2-16b-trace-a64.h b/test/a64/traces/sim-subhn2-16b-trace-a64.h index e58e07ac..b2f4110b 100644 --- a/test/a64/traces/sim-subhn2-16b-trace-a64.h +++ b/test/a64/traces/sim-subhn2-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-subhn2-4s-trace-a64.h b/test/a64/traces/sim-subhn2-4s-trace-a64.h index 01ae1c7d..fa056bea 100644 --- a/test/a64/traces/sim-subhn2-4s-trace-a64.h +++ b/test/a64/traces/sim-subhn2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-subhn2-8h-trace-a64.h b/test/a64/traces/sim-subhn2-8h-trace-a64.h index 051b164c..344970db 100644 --- a/test/a64/traces/sim-subhn2-8h-trace-a64.h +++ b/test/a64/traces/sim-subhn2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-suqadd-16b-trace-a64.h b/test/a64/traces/sim-suqadd-16b-trace-a64.h index fb0d0fc8..4b8f14bf 100644 --- a/test/a64/traces/sim-suqadd-16b-trace-a64.h +++ b/test/a64/traces/sim-suqadd-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-suqadd-2d-trace-a64.h b/test/a64/traces/sim-suqadd-2d-trace-a64.h index 126d916c..98f8b6b8 100644 --- a/test/a64/traces/sim-suqadd-2d-trace-a64.h +++ b/test/a64/traces/sim-suqadd-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-suqadd-2s-trace-a64.h b/test/a64/traces/sim-suqadd-2s-trace-a64.h index 55b597fd..92af42cd 100644 --- a/test/a64/traces/sim-suqadd-2s-trace-a64.h +++ b/test/a64/traces/sim-suqadd-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-suqadd-4h-trace-a64.h b/test/a64/traces/sim-suqadd-4h-trace-a64.h index 17fb16d4..f0f0e942 100644 --- a/test/a64/traces/sim-suqadd-4h-trace-a64.h +++ b/test/a64/traces/sim-suqadd-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-suqadd-4s-trace-a64.h b/test/a64/traces/sim-suqadd-4s-trace-a64.h index bc7c15c4..b46fbae1 100644 --- a/test/a64/traces/sim-suqadd-4s-trace-a64.h +++ b/test/a64/traces/sim-suqadd-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-suqadd-8b-trace-a64.h b/test/a64/traces/sim-suqadd-8b-trace-a64.h index d13f3779..73ff41c9 100644 --- a/test/a64/traces/sim-suqadd-8b-trace-a64.h +++ b/test/a64/traces/sim-suqadd-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-suqadd-8h-trace-a64.h b/test/a64/traces/sim-suqadd-8h-trace-a64.h index e5b79e63..abaac22d 100644 --- a/test/a64/traces/sim-suqadd-8h-trace-a64.h +++ b/test/a64/traces/sim-suqadd-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-suqadd-b-trace-a64.h b/test/a64/traces/sim-suqadd-b-trace-a64.h index 5d210deb..dac9cefd 100644 --- a/test/a64/traces/sim-suqadd-b-trace-a64.h +++ b/test/a64/traces/sim-suqadd-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-suqadd-d-trace-a64.h b/test/a64/traces/sim-suqadd-d-trace-a64.h index da4a185f..7d3ff8cb 100644 --- a/test/a64/traces/sim-suqadd-d-trace-a64.h +++ b/test/a64/traces/sim-suqadd-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-suqadd-h-trace-a64.h b/test/a64/traces/sim-suqadd-h-trace-a64.h index e387d457..47665a3a 100644 --- a/test/a64/traces/sim-suqadd-h-trace-a64.h +++ b/test/a64/traces/sim-suqadd-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-suqadd-s-trace-a64.h b/test/a64/traces/sim-suqadd-s-trace-a64.h index c16828a4..8748f220 100644 --- a/test/a64/traces/sim-suqadd-s-trace-a64.h +++ b/test/a64/traces/sim-suqadd-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn1-16b-trace-a64.h b/test/a64/traces/sim-trn1-16b-trace-a64.h index 62d59f74..a8319fc0 100644 --- a/test/a64/traces/sim-trn1-16b-trace-a64.h +++ b/test/a64/traces/sim-trn1-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn1-2d-trace-a64.h b/test/a64/traces/sim-trn1-2d-trace-a64.h index 67775a37..3048390a 100644 --- a/test/a64/traces/sim-trn1-2d-trace-a64.h +++ b/test/a64/traces/sim-trn1-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn1-2s-trace-a64.h b/test/a64/traces/sim-trn1-2s-trace-a64.h index 1f64a92f..e0014290 100644 --- a/test/a64/traces/sim-trn1-2s-trace-a64.h +++ b/test/a64/traces/sim-trn1-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn1-4h-trace-a64.h b/test/a64/traces/sim-trn1-4h-trace-a64.h index 08119174..a9b742d1 100644 --- a/test/a64/traces/sim-trn1-4h-trace-a64.h +++ b/test/a64/traces/sim-trn1-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn1-4s-trace-a64.h b/test/a64/traces/sim-trn1-4s-trace-a64.h index a450bbb7..b64ff81d 100644 --- a/test/a64/traces/sim-trn1-4s-trace-a64.h +++ b/test/a64/traces/sim-trn1-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn1-8b-trace-a64.h b/test/a64/traces/sim-trn1-8b-trace-a64.h index d7dfbcb8..816f2f6b 100644 --- a/test/a64/traces/sim-trn1-8b-trace-a64.h +++ b/test/a64/traces/sim-trn1-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn1-8h-trace-a64.h b/test/a64/traces/sim-trn1-8h-trace-a64.h index af184b35..c654a0c6 100644 --- a/test/a64/traces/sim-trn1-8h-trace-a64.h +++ b/test/a64/traces/sim-trn1-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn2-16b-trace-a64.h b/test/a64/traces/sim-trn2-16b-trace-a64.h index 360f8db8..e1a2989d 100644 --- a/test/a64/traces/sim-trn2-16b-trace-a64.h +++ b/test/a64/traces/sim-trn2-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn2-2d-trace-a64.h b/test/a64/traces/sim-trn2-2d-trace-a64.h index da6dcf7c..926e40b3 100644 --- a/test/a64/traces/sim-trn2-2d-trace-a64.h +++ b/test/a64/traces/sim-trn2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn2-2s-trace-a64.h b/test/a64/traces/sim-trn2-2s-trace-a64.h index 9acc43d4..2a02b498 100644 --- a/test/a64/traces/sim-trn2-2s-trace-a64.h +++ b/test/a64/traces/sim-trn2-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn2-4h-trace-a64.h b/test/a64/traces/sim-trn2-4h-trace-a64.h index ba85634e..a5edc3d0 100644 --- a/test/a64/traces/sim-trn2-4h-trace-a64.h +++ b/test/a64/traces/sim-trn2-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn2-4s-trace-a64.h b/test/a64/traces/sim-trn2-4s-trace-a64.h index 0b800418..07acf773 100644 --- a/test/a64/traces/sim-trn2-4s-trace-a64.h +++ b/test/a64/traces/sim-trn2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn2-8b-trace-a64.h b/test/a64/traces/sim-trn2-8b-trace-a64.h index ffdebd27..7d21f0be 100644 --- a/test/a64/traces/sim-trn2-8b-trace-a64.h +++ b/test/a64/traces/sim-trn2-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-trn2-8h-trace-a64.h b/test/a64/traces/sim-trn2-8h-trace-a64.h index 413c2d6b..4e07b639 100644 --- a/test/a64/traces/sim-trn2-8h-trace-a64.h +++ b/test/a64/traces/sim-trn2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaba-16b-trace-a64.h b/test/a64/traces/sim-uaba-16b-trace-a64.h index d43ebe11..46aeec3e 100644 --- a/test/a64/traces/sim-uaba-16b-trace-a64.h +++ b/test/a64/traces/sim-uaba-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaba-2s-trace-a64.h b/test/a64/traces/sim-uaba-2s-trace-a64.h index 619dd0a1..123f3e8a 100644 --- a/test/a64/traces/sim-uaba-2s-trace-a64.h +++ b/test/a64/traces/sim-uaba-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaba-4h-trace-a64.h b/test/a64/traces/sim-uaba-4h-trace-a64.h index 3285989f..70e2f136 100644 --- a/test/a64/traces/sim-uaba-4h-trace-a64.h +++ b/test/a64/traces/sim-uaba-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaba-4s-trace-a64.h b/test/a64/traces/sim-uaba-4s-trace-a64.h index a5cccffc..4b4c9a37 100644 --- a/test/a64/traces/sim-uaba-4s-trace-a64.h +++ b/test/a64/traces/sim-uaba-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaba-8b-trace-a64.h b/test/a64/traces/sim-uaba-8b-trace-a64.h index a0b7ab44..d1c4a003 100644 --- a/test/a64/traces/sim-uaba-8b-trace-a64.h +++ b/test/a64/traces/sim-uaba-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaba-8h-trace-a64.h b/test/a64/traces/sim-uaba-8h-trace-a64.h index 1328c394..6340c49d 100644 --- a/test/a64/traces/sim-uaba-8h-trace-a64.h +++ b/test/a64/traces/sim-uaba-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabal-2d-trace-a64.h b/test/a64/traces/sim-uabal-2d-trace-a64.h index c1cbec16..903816b0 100644 --- a/test/a64/traces/sim-uabal-2d-trace-a64.h +++ b/test/a64/traces/sim-uabal-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabal-4s-trace-a64.h b/test/a64/traces/sim-uabal-4s-trace-a64.h index b6cd57be..999b498d 100644 --- a/test/a64/traces/sim-uabal-4s-trace-a64.h +++ b/test/a64/traces/sim-uabal-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabal-8h-trace-a64.h b/test/a64/traces/sim-uabal-8h-trace-a64.h index 582efaee..e2072cc8 100644 --- a/test/a64/traces/sim-uabal-8h-trace-a64.h +++ b/test/a64/traces/sim-uabal-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabal2-2d-trace-a64.h b/test/a64/traces/sim-uabal2-2d-trace-a64.h index 7931dd69..5522f294 100644 --- a/test/a64/traces/sim-uabal2-2d-trace-a64.h +++ b/test/a64/traces/sim-uabal2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabal2-4s-trace-a64.h b/test/a64/traces/sim-uabal2-4s-trace-a64.h index c61cc17e..cc1669a4 100644 --- a/test/a64/traces/sim-uabal2-4s-trace-a64.h +++ b/test/a64/traces/sim-uabal2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabal2-8h-trace-a64.h b/test/a64/traces/sim-uabal2-8h-trace-a64.h index 0e60c7d1..b1ab7cc1 100644 --- a/test/a64/traces/sim-uabal2-8h-trace-a64.h +++ b/test/a64/traces/sim-uabal2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabd-16b-trace-a64.h b/test/a64/traces/sim-uabd-16b-trace-a64.h index 3126ed3e..466b17eb 100644 --- a/test/a64/traces/sim-uabd-16b-trace-a64.h +++ b/test/a64/traces/sim-uabd-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabd-2s-trace-a64.h b/test/a64/traces/sim-uabd-2s-trace-a64.h index 6077f04f..e57b5ca1 100644 --- a/test/a64/traces/sim-uabd-2s-trace-a64.h +++ b/test/a64/traces/sim-uabd-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabd-4h-trace-a64.h b/test/a64/traces/sim-uabd-4h-trace-a64.h index 563ef8ce..80cdfd96 100644 --- a/test/a64/traces/sim-uabd-4h-trace-a64.h +++ b/test/a64/traces/sim-uabd-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabd-4s-trace-a64.h b/test/a64/traces/sim-uabd-4s-trace-a64.h index 787cd869..87140714 100644 --- a/test/a64/traces/sim-uabd-4s-trace-a64.h +++ b/test/a64/traces/sim-uabd-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabd-8b-trace-a64.h b/test/a64/traces/sim-uabd-8b-trace-a64.h index d5764abf..e00f91dd 100644 --- a/test/a64/traces/sim-uabd-8b-trace-a64.h +++ b/test/a64/traces/sim-uabd-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabd-8h-trace-a64.h b/test/a64/traces/sim-uabd-8h-trace-a64.h index 490e7b5e..6d87b724 100644 --- a/test/a64/traces/sim-uabd-8h-trace-a64.h +++ b/test/a64/traces/sim-uabd-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabdl-2d-trace-a64.h b/test/a64/traces/sim-uabdl-2d-trace-a64.h index 0d739d7b..a1401628 100644 --- a/test/a64/traces/sim-uabdl-2d-trace-a64.h +++ b/test/a64/traces/sim-uabdl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabdl-4s-trace-a64.h b/test/a64/traces/sim-uabdl-4s-trace-a64.h index 8c503911..040f70ce 100644 --- a/test/a64/traces/sim-uabdl-4s-trace-a64.h +++ b/test/a64/traces/sim-uabdl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabdl-8h-trace-a64.h b/test/a64/traces/sim-uabdl-8h-trace-a64.h index 6340ec5b..e37e2ee9 100644 --- a/test/a64/traces/sim-uabdl-8h-trace-a64.h +++ b/test/a64/traces/sim-uabdl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabdl2-2d-trace-a64.h b/test/a64/traces/sim-uabdl2-2d-trace-a64.h index 6e643d2a..499832f5 100644 --- a/test/a64/traces/sim-uabdl2-2d-trace-a64.h +++ b/test/a64/traces/sim-uabdl2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabdl2-4s-trace-a64.h b/test/a64/traces/sim-uabdl2-4s-trace-a64.h index 743462c4..c3563e32 100644 --- a/test/a64/traces/sim-uabdl2-4s-trace-a64.h +++ b/test/a64/traces/sim-uabdl2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uabdl2-8h-trace-a64.h b/test/a64/traces/sim-uabdl2-8h-trace-a64.h index 87ee0976..bca8f908 100644 --- a/test/a64/traces/sim-uabdl2-8h-trace-a64.h +++ b/test/a64/traces/sim-uabdl2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uadalp-1d-trace-a64.h b/test/a64/traces/sim-uadalp-1d-trace-a64.h index 566c0606..1d34705a 100644 --- a/test/a64/traces/sim-uadalp-1d-trace-a64.h +++ b/test/a64/traces/sim-uadalp-1d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uadalp-2d-trace-a64.h b/test/a64/traces/sim-uadalp-2d-trace-a64.h index 99e1b752..b5caa1c8 100644 --- a/test/a64/traces/sim-uadalp-2d-trace-a64.h +++ b/test/a64/traces/sim-uadalp-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uadalp-2s-trace-a64.h b/test/a64/traces/sim-uadalp-2s-trace-a64.h index 49ebd34c..b920afe1 100644 --- a/test/a64/traces/sim-uadalp-2s-trace-a64.h +++ b/test/a64/traces/sim-uadalp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uadalp-4h-trace-a64.h b/test/a64/traces/sim-uadalp-4h-trace-a64.h index a884f95a..402121b5 100644 --- a/test/a64/traces/sim-uadalp-4h-trace-a64.h +++ b/test/a64/traces/sim-uadalp-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uadalp-4s-trace-a64.h b/test/a64/traces/sim-uadalp-4s-trace-a64.h index f8a69f5e..5197ca25 100644 --- a/test/a64/traces/sim-uadalp-4s-trace-a64.h +++ b/test/a64/traces/sim-uadalp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uadalp-8h-trace-a64.h b/test/a64/traces/sim-uadalp-8h-trace-a64.h index ac717984..e7eb5777 100644 --- a/test/a64/traces/sim-uadalp-8h-trace-a64.h +++ b/test/a64/traces/sim-uadalp-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddl-2d-trace-a64.h b/test/a64/traces/sim-uaddl-2d-trace-a64.h index 86dd7073..a876fd34 100644 --- a/test/a64/traces/sim-uaddl-2d-trace-a64.h +++ b/test/a64/traces/sim-uaddl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddl-4s-trace-a64.h b/test/a64/traces/sim-uaddl-4s-trace-a64.h index 8d72c496..6ccc4322 100644 --- a/test/a64/traces/sim-uaddl-4s-trace-a64.h +++ b/test/a64/traces/sim-uaddl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddl-8h-trace-a64.h b/test/a64/traces/sim-uaddl-8h-trace-a64.h index 6c903e60..c88b7875 100644 --- a/test/a64/traces/sim-uaddl-8h-trace-a64.h +++ b/test/a64/traces/sim-uaddl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddl2-2d-trace-a64.h b/test/a64/traces/sim-uaddl2-2d-trace-a64.h index aff75bc2..9f6e5f77 100644 --- a/test/a64/traces/sim-uaddl2-2d-trace-a64.h +++ b/test/a64/traces/sim-uaddl2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddl2-4s-trace-a64.h b/test/a64/traces/sim-uaddl2-4s-trace-a64.h index 19498ba0..0ed7dda1 100644 --- a/test/a64/traces/sim-uaddl2-4s-trace-a64.h +++ b/test/a64/traces/sim-uaddl2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddl2-8h-trace-a64.h b/test/a64/traces/sim-uaddl2-8h-trace-a64.h index 7be45c92..d8f1c3f7 100644 --- a/test/a64/traces/sim-uaddl2-8h-trace-a64.h +++ b/test/a64/traces/sim-uaddl2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddlp-1d-trace-a64.h b/test/a64/traces/sim-uaddlp-1d-trace-a64.h index a36c3c10..eb8bf19b 100644 --- a/test/a64/traces/sim-uaddlp-1d-trace-a64.h +++ b/test/a64/traces/sim-uaddlp-1d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddlp-2d-trace-a64.h b/test/a64/traces/sim-uaddlp-2d-trace-a64.h index d6a8ee34..dc3dae3b 100644 --- a/test/a64/traces/sim-uaddlp-2d-trace-a64.h +++ b/test/a64/traces/sim-uaddlp-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddlp-2s-trace-a64.h b/test/a64/traces/sim-uaddlp-2s-trace-a64.h index 29ad0fb7..82cc75c9 100644 --- a/test/a64/traces/sim-uaddlp-2s-trace-a64.h +++ b/test/a64/traces/sim-uaddlp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddlp-4h-trace-a64.h b/test/a64/traces/sim-uaddlp-4h-trace-a64.h index 9f24c7fd..035711b8 100644 --- a/test/a64/traces/sim-uaddlp-4h-trace-a64.h +++ b/test/a64/traces/sim-uaddlp-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddlp-4s-trace-a64.h b/test/a64/traces/sim-uaddlp-4s-trace-a64.h index 6fbbe967..5d15ef05 100644 --- a/test/a64/traces/sim-uaddlp-4s-trace-a64.h +++ b/test/a64/traces/sim-uaddlp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddlp-8h-trace-a64.h b/test/a64/traces/sim-uaddlp-8h-trace-a64.h index 78c0f17b..14661c90 100644 --- a/test/a64/traces/sim-uaddlp-8h-trace-a64.h +++ b/test/a64/traces/sim-uaddlp-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddlv-d-4s-trace-a64.h b/test/a64/traces/sim-uaddlv-d-4s-trace-a64.h index 3368efe7..7479d828 100644 --- a/test/a64/traces/sim-uaddlv-d-4s-trace-a64.h +++ b/test/a64/traces/sim-uaddlv-d-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddlv-h-16b-trace-a64.h b/test/a64/traces/sim-uaddlv-h-16b-trace-a64.h index f4ab0d39..d978605a 100644 --- a/test/a64/traces/sim-uaddlv-h-16b-trace-a64.h +++ b/test/a64/traces/sim-uaddlv-h-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddlv-h-8b-trace-a64.h b/test/a64/traces/sim-uaddlv-h-8b-trace-a64.h index 03947d05..c850bd33 100644 --- a/test/a64/traces/sim-uaddlv-h-8b-trace-a64.h +++ b/test/a64/traces/sim-uaddlv-h-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddlv-s-4h-trace-a64.h b/test/a64/traces/sim-uaddlv-s-4h-trace-a64.h index cf5ae1c4..a16c1e40 100644 --- a/test/a64/traces/sim-uaddlv-s-4h-trace-a64.h +++ b/test/a64/traces/sim-uaddlv-s-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddlv-s-8h-trace-a64.h b/test/a64/traces/sim-uaddlv-s-8h-trace-a64.h index 9c232f68..c96cc8d3 100644 --- a/test/a64/traces/sim-uaddlv-s-8h-trace-a64.h +++ b/test/a64/traces/sim-uaddlv-s-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddw-2d-trace-a64.h b/test/a64/traces/sim-uaddw-2d-trace-a64.h index 289fb4be..3cc7a5d2 100644 --- a/test/a64/traces/sim-uaddw-2d-trace-a64.h +++ b/test/a64/traces/sim-uaddw-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddw-4s-trace-a64.h b/test/a64/traces/sim-uaddw-4s-trace-a64.h index ea735317..383b2105 100644 --- a/test/a64/traces/sim-uaddw-4s-trace-a64.h +++ b/test/a64/traces/sim-uaddw-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddw-8h-trace-a64.h b/test/a64/traces/sim-uaddw-8h-trace-a64.h index d714372f..6bc73248 100644 --- a/test/a64/traces/sim-uaddw-8h-trace-a64.h +++ b/test/a64/traces/sim-uaddw-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddw2-2d-trace-a64.h b/test/a64/traces/sim-uaddw2-2d-trace-a64.h index 54746622..c4f69cc6 100644 --- a/test/a64/traces/sim-uaddw2-2d-trace-a64.h +++ b/test/a64/traces/sim-uaddw2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddw2-4s-trace-a64.h b/test/a64/traces/sim-uaddw2-4s-trace-a64.h index c67b0885..150aced4 100644 --- a/test/a64/traces/sim-uaddw2-4s-trace-a64.h +++ b/test/a64/traces/sim-uaddw2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uaddw2-8h-trace-a64.h b/test/a64/traces/sim-uaddw2-8h-trace-a64.h index b5fcf2a0..2597d2c1 100644 --- a/test/a64/traces/sim-uaddw2-8h-trace-a64.h +++ b/test/a64/traces/sim-uaddw2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ucvtf-2d-2opimm-trace-a64.h b/test/a64/traces/sim-ucvtf-2d-2opimm-trace-a64.h index 3118302d..48fba8b5 100644 --- a/test/a64/traces/sim-ucvtf-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ucvtf-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ucvtf-2s-2opimm-trace-a64.h b/test/a64/traces/sim-ucvtf-2s-2opimm-trace-a64.h index f028b9da..0aea058f 100644 --- a/test/a64/traces/sim-ucvtf-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ucvtf-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ucvtf-4s-2opimm-trace-a64.h b/test/a64/traces/sim-ucvtf-4s-2opimm-trace-a64.h index 9474e13f..dbaee9eb 100644 --- a/test/a64/traces/sim-ucvtf-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ucvtf-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ucvtf-d-2opimm-trace-a64.h b/test/a64/traces/sim-ucvtf-d-2opimm-trace-a64.h index c983b8f4..8becec41 100644 --- a/test/a64/traces/sim-ucvtf-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ucvtf-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ucvtf-s-2opimm-trace-a64.h b/test/a64/traces/sim-ucvtf-s-2opimm-trace-a64.h index a292e08f..10ba3f1b 100644 --- a/test/a64/traces/sim-ucvtf-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ucvtf-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uhadd-16b-trace-a64.h b/test/a64/traces/sim-uhadd-16b-trace-a64.h index effe8853..48d18f50 100644 --- a/test/a64/traces/sim-uhadd-16b-trace-a64.h +++ b/test/a64/traces/sim-uhadd-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uhadd-2s-trace-a64.h b/test/a64/traces/sim-uhadd-2s-trace-a64.h index 7b7c143e..2d977783 100644 --- a/test/a64/traces/sim-uhadd-2s-trace-a64.h +++ b/test/a64/traces/sim-uhadd-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uhadd-4h-trace-a64.h b/test/a64/traces/sim-uhadd-4h-trace-a64.h index a794db25..de352d6b 100644 --- a/test/a64/traces/sim-uhadd-4h-trace-a64.h +++ b/test/a64/traces/sim-uhadd-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uhadd-4s-trace-a64.h b/test/a64/traces/sim-uhadd-4s-trace-a64.h index f29f2742..74c65118 100644 --- a/test/a64/traces/sim-uhadd-4s-trace-a64.h +++ b/test/a64/traces/sim-uhadd-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uhadd-8b-trace-a64.h b/test/a64/traces/sim-uhadd-8b-trace-a64.h index 297f4ddc..21660c1b 100644 --- a/test/a64/traces/sim-uhadd-8b-trace-a64.h +++ b/test/a64/traces/sim-uhadd-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uhadd-8h-trace-a64.h b/test/a64/traces/sim-uhadd-8h-trace-a64.h index d453d97e..11b5957a 100644 --- a/test/a64/traces/sim-uhadd-8h-trace-a64.h +++ b/test/a64/traces/sim-uhadd-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uhsub-16b-trace-a64.h b/test/a64/traces/sim-uhsub-16b-trace-a64.h index 4bc423b3..ea7dfbb7 100644 --- a/test/a64/traces/sim-uhsub-16b-trace-a64.h +++ b/test/a64/traces/sim-uhsub-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uhsub-2s-trace-a64.h b/test/a64/traces/sim-uhsub-2s-trace-a64.h index 84f55904..27d82432 100644 --- a/test/a64/traces/sim-uhsub-2s-trace-a64.h +++ b/test/a64/traces/sim-uhsub-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uhsub-4h-trace-a64.h b/test/a64/traces/sim-uhsub-4h-trace-a64.h index 0b2b5fbd..f251f68d 100644 --- a/test/a64/traces/sim-uhsub-4h-trace-a64.h +++ b/test/a64/traces/sim-uhsub-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uhsub-4s-trace-a64.h b/test/a64/traces/sim-uhsub-4s-trace-a64.h index a1614eeb..c232ef0c 100644 --- a/test/a64/traces/sim-uhsub-4s-trace-a64.h +++ b/test/a64/traces/sim-uhsub-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uhsub-8b-trace-a64.h b/test/a64/traces/sim-uhsub-8b-trace-a64.h index de5251c2..b3677f7b 100644 --- a/test/a64/traces/sim-uhsub-8b-trace-a64.h +++ b/test/a64/traces/sim-uhsub-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uhsub-8h-trace-a64.h b/test/a64/traces/sim-uhsub-8h-trace-a64.h index c37bb183..228a432d 100644 --- a/test/a64/traces/sim-uhsub-8h-trace-a64.h +++ b/test/a64/traces/sim-uhsub-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umax-16b-trace-a64.h b/test/a64/traces/sim-umax-16b-trace-a64.h index 8de9811f..a5d8d906 100644 --- a/test/a64/traces/sim-umax-16b-trace-a64.h +++ b/test/a64/traces/sim-umax-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umax-2s-trace-a64.h b/test/a64/traces/sim-umax-2s-trace-a64.h index 685d58c1..918c37de 100644 --- a/test/a64/traces/sim-umax-2s-trace-a64.h +++ b/test/a64/traces/sim-umax-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umax-4h-trace-a64.h b/test/a64/traces/sim-umax-4h-trace-a64.h index 9072a521..1910e920 100644 --- a/test/a64/traces/sim-umax-4h-trace-a64.h +++ b/test/a64/traces/sim-umax-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umax-4s-trace-a64.h b/test/a64/traces/sim-umax-4s-trace-a64.h index cf4283cc..e9c11afa 100644 --- a/test/a64/traces/sim-umax-4s-trace-a64.h +++ b/test/a64/traces/sim-umax-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umax-8b-trace-a64.h b/test/a64/traces/sim-umax-8b-trace-a64.h index 72d6fc0e..35289de1 100644 --- a/test/a64/traces/sim-umax-8b-trace-a64.h +++ b/test/a64/traces/sim-umax-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umax-8h-trace-a64.h b/test/a64/traces/sim-umax-8h-trace-a64.h index 65083e5b..a6561df4 100644 --- a/test/a64/traces/sim-umax-8h-trace-a64.h +++ b/test/a64/traces/sim-umax-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umaxp-16b-trace-a64.h b/test/a64/traces/sim-umaxp-16b-trace-a64.h index 1631aef7..6347846e 100644 --- a/test/a64/traces/sim-umaxp-16b-trace-a64.h +++ b/test/a64/traces/sim-umaxp-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umaxp-2s-trace-a64.h b/test/a64/traces/sim-umaxp-2s-trace-a64.h index 54567e56..e024c06b 100644 --- a/test/a64/traces/sim-umaxp-2s-trace-a64.h +++ b/test/a64/traces/sim-umaxp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umaxp-4h-trace-a64.h b/test/a64/traces/sim-umaxp-4h-trace-a64.h index 9977dfa8..6b6e3b98 100644 --- a/test/a64/traces/sim-umaxp-4h-trace-a64.h +++ b/test/a64/traces/sim-umaxp-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umaxp-4s-trace-a64.h b/test/a64/traces/sim-umaxp-4s-trace-a64.h index 23cb091c..b5a64133 100644 --- a/test/a64/traces/sim-umaxp-4s-trace-a64.h +++ b/test/a64/traces/sim-umaxp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umaxp-8b-trace-a64.h b/test/a64/traces/sim-umaxp-8b-trace-a64.h index 1c2524b7..bc2b23d7 100644 --- a/test/a64/traces/sim-umaxp-8b-trace-a64.h +++ b/test/a64/traces/sim-umaxp-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umaxp-8h-trace-a64.h b/test/a64/traces/sim-umaxp-8h-trace-a64.h index b046a112..8dc11af6 100644 --- a/test/a64/traces/sim-umaxp-8h-trace-a64.h +++ b/test/a64/traces/sim-umaxp-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umaxv-b-16b-trace-a64.h b/test/a64/traces/sim-umaxv-b-16b-trace-a64.h index bd1f2dd7..83c65ca1 100644 --- a/test/a64/traces/sim-umaxv-b-16b-trace-a64.h +++ b/test/a64/traces/sim-umaxv-b-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umaxv-b-8b-trace-a64.h b/test/a64/traces/sim-umaxv-b-8b-trace-a64.h index e34802be..d4ec983a 100644 --- a/test/a64/traces/sim-umaxv-b-8b-trace-a64.h +++ b/test/a64/traces/sim-umaxv-b-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umaxv-h-4h-trace-a64.h b/test/a64/traces/sim-umaxv-h-4h-trace-a64.h index 4e750c36..bdebe161 100644 --- a/test/a64/traces/sim-umaxv-h-4h-trace-a64.h +++ b/test/a64/traces/sim-umaxv-h-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umaxv-h-8h-trace-a64.h b/test/a64/traces/sim-umaxv-h-8h-trace-a64.h index a471cd45..a923a186 100644 --- a/test/a64/traces/sim-umaxv-h-8h-trace-a64.h +++ b/test/a64/traces/sim-umaxv-h-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umaxv-s-4s-trace-a64.h b/test/a64/traces/sim-umaxv-s-4s-trace-a64.h index e896ec10..5430b1db 100644 --- a/test/a64/traces/sim-umaxv-s-4s-trace-a64.h +++ b/test/a64/traces/sim-umaxv-s-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umin-16b-trace-a64.h b/test/a64/traces/sim-umin-16b-trace-a64.h index 550d57bf..f9063c01 100644 --- a/test/a64/traces/sim-umin-16b-trace-a64.h +++ b/test/a64/traces/sim-umin-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umin-2s-trace-a64.h b/test/a64/traces/sim-umin-2s-trace-a64.h index ee32a1e3..1c6575b0 100644 --- a/test/a64/traces/sim-umin-2s-trace-a64.h +++ b/test/a64/traces/sim-umin-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umin-4h-trace-a64.h b/test/a64/traces/sim-umin-4h-trace-a64.h index 15177385..033150f0 100644 --- a/test/a64/traces/sim-umin-4h-trace-a64.h +++ b/test/a64/traces/sim-umin-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umin-4s-trace-a64.h b/test/a64/traces/sim-umin-4s-trace-a64.h index c7f7c81c..e83955d7 100644 --- a/test/a64/traces/sim-umin-4s-trace-a64.h +++ b/test/a64/traces/sim-umin-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umin-8b-trace-a64.h b/test/a64/traces/sim-umin-8b-trace-a64.h index 77a02895..5e0eca8a 100644 --- a/test/a64/traces/sim-umin-8b-trace-a64.h +++ b/test/a64/traces/sim-umin-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umin-8h-trace-a64.h b/test/a64/traces/sim-umin-8h-trace-a64.h index 0739a6ed..1d1d8dcb 100644 --- a/test/a64/traces/sim-umin-8h-trace-a64.h +++ b/test/a64/traces/sim-umin-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uminp-16b-trace-a64.h b/test/a64/traces/sim-uminp-16b-trace-a64.h index 681f18d9..d02f5df9 100644 --- a/test/a64/traces/sim-uminp-16b-trace-a64.h +++ b/test/a64/traces/sim-uminp-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uminp-2s-trace-a64.h b/test/a64/traces/sim-uminp-2s-trace-a64.h index 8183b0f4..18e0bfcb 100644 --- a/test/a64/traces/sim-uminp-2s-trace-a64.h +++ b/test/a64/traces/sim-uminp-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uminp-4h-trace-a64.h b/test/a64/traces/sim-uminp-4h-trace-a64.h index 6fa9c5fa..57721a28 100644 --- a/test/a64/traces/sim-uminp-4h-trace-a64.h +++ b/test/a64/traces/sim-uminp-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uminp-4s-trace-a64.h b/test/a64/traces/sim-uminp-4s-trace-a64.h index 7e477c83..4c4dfb13 100644 --- a/test/a64/traces/sim-uminp-4s-trace-a64.h +++ b/test/a64/traces/sim-uminp-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uminp-8b-trace-a64.h b/test/a64/traces/sim-uminp-8b-trace-a64.h index ca93e638..403dc45b 100644 --- a/test/a64/traces/sim-uminp-8b-trace-a64.h +++ b/test/a64/traces/sim-uminp-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uminp-8h-trace-a64.h b/test/a64/traces/sim-uminp-8h-trace-a64.h index 999c45fa..516a0527 100644 --- a/test/a64/traces/sim-uminp-8h-trace-a64.h +++ b/test/a64/traces/sim-uminp-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uminv-b-16b-trace-a64.h b/test/a64/traces/sim-uminv-b-16b-trace-a64.h index a47cf989..3e0df5f2 100644 --- a/test/a64/traces/sim-uminv-b-16b-trace-a64.h +++ b/test/a64/traces/sim-uminv-b-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uminv-b-8b-trace-a64.h b/test/a64/traces/sim-uminv-b-8b-trace-a64.h index b44568f4..ab51f75a 100644 --- a/test/a64/traces/sim-uminv-b-8b-trace-a64.h +++ b/test/a64/traces/sim-uminv-b-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uminv-h-4h-trace-a64.h b/test/a64/traces/sim-uminv-h-4h-trace-a64.h index 462361ab..b8894bea 100644 --- a/test/a64/traces/sim-uminv-h-4h-trace-a64.h +++ b/test/a64/traces/sim-uminv-h-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uminv-h-8h-trace-a64.h b/test/a64/traces/sim-uminv-h-8h-trace-a64.h index 8dc205d5..bc161d75 100644 --- a/test/a64/traces/sim-uminv-h-8h-trace-a64.h +++ b/test/a64/traces/sim-uminv-h-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uminv-s-4s-trace-a64.h b/test/a64/traces/sim-uminv-s-4s-trace-a64.h index 3d9f9f35..fbce1562 100644 --- a/test/a64/traces/sim-uminv-s-4s-trace-a64.h +++ b/test/a64/traces/sim-uminv-s-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlal-2d-2s-s-trace-a64.h b/test/a64/traces/sim-umlal-2d-2s-s-trace-a64.h index 827ac89d..34eb2492 100644 --- a/test/a64/traces/sim-umlal-2d-2s-s-trace-a64.h +++ b/test/a64/traces/sim-umlal-2d-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlal-2d-trace-a64.h b/test/a64/traces/sim-umlal-2d-trace-a64.h index 2382f4c8..a405b02e 100644 --- a/test/a64/traces/sim-umlal-2d-trace-a64.h +++ b/test/a64/traces/sim-umlal-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlal-4s-4h-h-trace-a64.h b/test/a64/traces/sim-umlal-4s-4h-h-trace-a64.h index 34f7155b..6dbbad63 100644 --- a/test/a64/traces/sim-umlal-4s-4h-h-trace-a64.h +++ b/test/a64/traces/sim-umlal-4s-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlal-4s-trace-a64.h b/test/a64/traces/sim-umlal-4s-trace-a64.h index cc54ebfe..9cd9be50 100644 --- a/test/a64/traces/sim-umlal-4s-trace-a64.h +++ b/test/a64/traces/sim-umlal-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlal-8h-trace-a64.h b/test/a64/traces/sim-umlal-8h-trace-a64.h index a27b8bdc..c7cb95aa 100644 --- a/test/a64/traces/sim-umlal-8h-trace-a64.h +++ b/test/a64/traces/sim-umlal-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlal2-2d-4s-s-trace-a64.h b/test/a64/traces/sim-umlal2-2d-4s-s-trace-a64.h index b40f8b2e..fa6bbda6 100644 --- a/test/a64/traces/sim-umlal2-2d-4s-s-trace-a64.h +++ b/test/a64/traces/sim-umlal2-2d-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlal2-2d-trace-a64.h b/test/a64/traces/sim-umlal2-2d-trace-a64.h index 62beca66..9efe3cc3 100644 --- a/test/a64/traces/sim-umlal2-2d-trace-a64.h +++ b/test/a64/traces/sim-umlal2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlal2-4s-8h-h-trace-a64.h b/test/a64/traces/sim-umlal2-4s-8h-h-trace-a64.h index dda4cd1b..67a236d0 100644 --- a/test/a64/traces/sim-umlal2-4s-8h-h-trace-a64.h +++ b/test/a64/traces/sim-umlal2-4s-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlal2-4s-trace-a64.h b/test/a64/traces/sim-umlal2-4s-trace-a64.h index ee5a57bf..c0b355c7 100644 --- a/test/a64/traces/sim-umlal2-4s-trace-a64.h +++ b/test/a64/traces/sim-umlal2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlal2-8h-trace-a64.h b/test/a64/traces/sim-umlal2-8h-trace-a64.h index 8217f347..b9984d3a 100644 --- a/test/a64/traces/sim-umlal2-8h-trace-a64.h +++ b/test/a64/traces/sim-umlal2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlsl-2d-2s-s-trace-a64.h b/test/a64/traces/sim-umlsl-2d-2s-s-trace-a64.h index bd517c71..687a6a13 100644 --- a/test/a64/traces/sim-umlsl-2d-2s-s-trace-a64.h +++ b/test/a64/traces/sim-umlsl-2d-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlsl-2d-trace-a64.h b/test/a64/traces/sim-umlsl-2d-trace-a64.h index 80fc9f55..c694f561 100644 --- a/test/a64/traces/sim-umlsl-2d-trace-a64.h +++ b/test/a64/traces/sim-umlsl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlsl-4s-4h-h-trace-a64.h b/test/a64/traces/sim-umlsl-4s-4h-h-trace-a64.h index f02e187b..6d5c9015 100644 --- a/test/a64/traces/sim-umlsl-4s-4h-h-trace-a64.h +++ b/test/a64/traces/sim-umlsl-4s-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlsl-4s-trace-a64.h b/test/a64/traces/sim-umlsl-4s-trace-a64.h index 0f02dc64..f234833c 100644 --- a/test/a64/traces/sim-umlsl-4s-trace-a64.h +++ b/test/a64/traces/sim-umlsl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlsl-8h-trace-a64.h b/test/a64/traces/sim-umlsl-8h-trace-a64.h index cf6560c0..69404b4d 100644 --- a/test/a64/traces/sim-umlsl-8h-trace-a64.h +++ b/test/a64/traces/sim-umlsl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlsl2-2d-4s-s-trace-a64.h b/test/a64/traces/sim-umlsl2-2d-4s-s-trace-a64.h index 221cd3e4..c25cbf21 100644 --- a/test/a64/traces/sim-umlsl2-2d-4s-s-trace-a64.h +++ b/test/a64/traces/sim-umlsl2-2d-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlsl2-2d-trace-a64.h b/test/a64/traces/sim-umlsl2-2d-trace-a64.h index 73ecee00..ff3c4973 100644 --- a/test/a64/traces/sim-umlsl2-2d-trace-a64.h +++ b/test/a64/traces/sim-umlsl2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlsl2-4s-8h-h-trace-a64.h b/test/a64/traces/sim-umlsl2-4s-8h-h-trace-a64.h index 91eaafd0..912631e6 100644 --- a/test/a64/traces/sim-umlsl2-4s-8h-h-trace-a64.h +++ b/test/a64/traces/sim-umlsl2-4s-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlsl2-4s-trace-a64.h b/test/a64/traces/sim-umlsl2-4s-trace-a64.h index 75ec47c7..3a26852f 100644 --- a/test/a64/traces/sim-umlsl2-4s-trace-a64.h +++ b/test/a64/traces/sim-umlsl2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umlsl2-8h-trace-a64.h b/test/a64/traces/sim-umlsl2-8h-trace-a64.h index c2f808e6..7b94b46d 100644 --- a/test/a64/traces/sim-umlsl2-8h-trace-a64.h +++ b/test/a64/traces/sim-umlsl2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umull-2d-2s-s-trace-a64.h b/test/a64/traces/sim-umull-2d-2s-s-trace-a64.h index 131d70f0..3db865bc 100644 --- a/test/a64/traces/sim-umull-2d-2s-s-trace-a64.h +++ b/test/a64/traces/sim-umull-2d-2s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umull-2d-trace-a64.h b/test/a64/traces/sim-umull-2d-trace-a64.h index 1ff88241..3bae809b 100644 --- a/test/a64/traces/sim-umull-2d-trace-a64.h +++ b/test/a64/traces/sim-umull-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umull-4s-4h-h-trace-a64.h b/test/a64/traces/sim-umull-4s-4h-h-trace-a64.h index eb29becd..a9038864 100644 --- a/test/a64/traces/sim-umull-4s-4h-h-trace-a64.h +++ b/test/a64/traces/sim-umull-4s-4h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umull-4s-trace-a64.h b/test/a64/traces/sim-umull-4s-trace-a64.h index 56edbef4..0fc61277 100644 --- a/test/a64/traces/sim-umull-4s-trace-a64.h +++ b/test/a64/traces/sim-umull-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umull-8h-trace-a64.h b/test/a64/traces/sim-umull-8h-trace-a64.h index c563d292..3caf021d 100644 --- a/test/a64/traces/sim-umull-8h-trace-a64.h +++ b/test/a64/traces/sim-umull-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umull2-2d-4s-s-trace-a64.h b/test/a64/traces/sim-umull2-2d-4s-s-trace-a64.h index c6874731..c9eb0688 100644 --- a/test/a64/traces/sim-umull2-2d-4s-s-trace-a64.h +++ b/test/a64/traces/sim-umull2-2d-4s-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umull2-2d-trace-a64.h b/test/a64/traces/sim-umull2-2d-trace-a64.h index 15581214..a3c70fad 100644 --- a/test/a64/traces/sim-umull2-2d-trace-a64.h +++ b/test/a64/traces/sim-umull2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umull2-4s-8h-h-trace-a64.h b/test/a64/traces/sim-umull2-4s-8h-h-trace-a64.h index 473b881c..df908429 100644 --- a/test/a64/traces/sim-umull2-4s-8h-h-trace-a64.h +++ b/test/a64/traces/sim-umull2-4s-8h-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umull2-4s-trace-a64.h b/test/a64/traces/sim-umull2-4s-trace-a64.h index 7d9c76be..092bb0f5 100644 --- a/test/a64/traces/sim-umull2-4s-trace-a64.h +++ b/test/a64/traces/sim-umull2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-umull2-8h-trace-a64.h b/test/a64/traces/sim-umull2-8h-trace-a64.h index 065d8030..ca5c513e 100644 --- a/test/a64/traces/sim-umull2-8h-trace-a64.h +++ b/test/a64/traces/sim-umull2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqadd-16b-trace-a64.h b/test/a64/traces/sim-uqadd-16b-trace-a64.h index c4488fc2..358feef7 100644 --- a/test/a64/traces/sim-uqadd-16b-trace-a64.h +++ b/test/a64/traces/sim-uqadd-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqadd-2d-trace-a64.h b/test/a64/traces/sim-uqadd-2d-trace-a64.h index cb270c5a..122dd34d 100644 --- a/test/a64/traces/sim-uqadd-2d-trace-a64.h +++ b/test/a64/traces/sim-uqadd-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqadd-2s-trace-a64.h b/test/a64/traces/sim-uqadd-2s-trace-a64.h index e300ae41..cbf2a57e 100644 --- a/test/a64/traces/sim-uqadd-2s-trace-a64.h +++ b/test/a64/traces/sim-uqadd-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqadd-4h-trace-a64.h b/test/a64/traces/sim-uqadd-4h-trace-a64.h index cae2842f..b60339ad 100644 --- a/test/a64/traces/sim-uqadd-4h-trace-a64.h +++ b/test/a64/traces/sim-uqadd-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqadd-4s-trace-a64.h b/test/a64/traces/sim-uqadd-4s-trace-a64.h index f86d2aa9..cfbe18bd 100644 --- a/test/a64/traces/sim-uqadd-4s-trace-a64.h +++ b/test/a64/traces/sim-uqadd-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqadd-8b-trace-a64.h b/test/a64/traces/sim-uqadd-8b-trace-a64.h index af92d4ed..fa8c6325 100644 --- a/test/a64/traces/sim-uqadd-8b-trace-a64.h +++ b/test/a64/traces/sim-uqadd-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqadd-8h-trace-a64.h b/test/a64/traces/sim-uqadd-8h-trace-a64.h index 430a2ca0..d764686d 100644 --- a/test/a64/traces/sim-uqadd-8h-trace-a64.h +++ b/test/a64/traces/sim-uqadd-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqadd-d-trace-a64.h b/test/a64/traces/sim-uqadd-d-trace-a64.h index 37b28a51..998049e4 100644 --- a/test/a64/traces/sim-uqadd-d-trace-a64.h +++ b/test/a64/traces/sim-uqadd-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshl-16b-trace-a64.h b/test/a64/traces/sim-uqrshl-16b-trace-a64.h index cea54ba2..1fbbd78d 100644 --- a/test/a64/traces/sim-uqrshl-16b-trace-a64.h +++ b/test/a64/traces/sim-uqrshl-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshl-2d-trace-a64.h b/test/a64/traces/sim-uqrshl-2d-trace-a64.h index 76f0cd63..340dfa78 100644 --- a/test/a64/traces/sim-uqrshl-2d-trace-a64.h +++ b/test/a64/traces/sim-uqrshl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshl-2s-trace-a64.h b/test/a64/traces/sim-uqrshl-2s-trace-a64.h index 8fd69a60..f4180b0c 100644 --- a/test/a64/traces/sim-uqrshl-2s-trace-a64.h +++ b/test/a64/traces/sim-uqrshl-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshl-4h-trace-a64.h b/test/a64/traces/sim-uqrshl-4h-trace-a64.h index 91d045eb..baeb5bb1 100644 --- a/test/a64/traces/sim-uqrshl-4h-trace-a64.h +++ b/test/a64/traces/sim-uqrshl-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshl-4s-trace-a64.h b/test/a64/traces/sim-uqrshl-4s-trace-a64.h index 76a06574..a6e16a82 100644 --- a/test/a64/traces/sim-uqrshl-4s-trace-a64.h +++ b/test/a64/traces/sim-uqrshl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshl-8b-trace-a64.h b/test/a64/traces/sim-uqrshl-8b-trace-a64.h index 4b9c0a1b..baa6a828 100644 --- a/test/a64/traces/sim-uqrshl-8b-trace-a64.h +++ b/test/a64/traces/sim-uqrshl-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshl-8h-trace-a64.h b/test/a64/traces/sim-uqrshl-8h-trace-a64.h index cc6efa0c..c4326fb3 100644 --- a/test/a64/traces/sim-uqrshl-8h-trace-a64.h +++ b/test/a64/traces/sim-uqrshl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshl-b-trace-a64.h b/test/a64/traces/sim-uqrshl-b-trace-a64.h index a9cf6777..680fb9ef 100644 --- a/test/a64/traces/sim-uqrshl-b-trace-a64.h +++ b/test/a64/traces/sim-uqrshl-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshl-d-trace-a64.h b/test/a64/traces/sim-uqrshl-d-trace-a64.h index 0e87e6e8..a7f33d3b 100644 --- a/test/a64/traces/sim-uqrshl-d-trace-a64.h +++ b/test/a64/traces/sim-uqrshl-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshl-h-trace-a64.h b/test/a64/traces/sim-uqrshl-h-trace-a64.h index 4d0b6a57..15e99750 100644 --- a/test/a64/traces/sim-uqrshl-h-trace-a64.h +++ b/test/a64/traces/sim-uqrshl-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshl-s-trace-a64.h b/test/a64/traces/sim-uqrshl-s-trace-a64.h index de2cddba..702342a3 100644 --- a/test/a64/traces/sim-uqrshl-s-trace-a64.h +++ b/test/a64/traces/sim-uqrshl-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshrn-2s-2opimm-trace-a64.h b/test/a64/traces/sim-uqrshrn-2s-2opimm-trace-a64.h index 090531b6..9523306b 100644 --- a/test/a64/traces/sim-uqrshrn-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqrshrn-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshrn-4h-2opimm-trace-a64.h b/test/a64/traces/sim-uqrshrn-4h-2opimm-trace-a64.h index 66e38454..c10a5643 100644 --- a/test/a64/traces/sim-uqrshrn-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqrshrn-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshrn-8b-2opimm-trace-a64.h b/test/a64/traces/sim-uqrshrn-8b-2opimm-trace-a64.h index b101ea46..697ae914 100644 --- a/test/a64/traces/sim-uqrshrn-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqrshrn-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshrn-b-2opimm-trace-a64.h b/test/a64/traces/sim-uqrshrn-b-2opimm-trace-a64.h index cda31349..d8f18218 100644 --- a/test/a64/traces/sim-uqrshrn-b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqrshrn-b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshrn-h-2opimm-trace-a64.h b/test/a64/traces/sim-uqrshrn-h-2opimm-trace-a64.h index a95cccef..5bb25d74 100644 --- a/test/a64/traces/sim-uqrshrn-h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqrshrn-h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshrn-s-2opimm-trace-a64.h b/test/a64/traces/sim-uqrshrn-s-2opimm-trace-a64.h index 468c3b94..98b297bb 100644 --- a/test/a64/traces/sim-uqrshrn-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqrshrn-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshrn2-16b-2opimm-trace-a64.h b/test/a64/traces/sim-uqrshrn2-16b-2opimm-trace-a64.h index ba29a322..6d5a5b18 100644 --- a/test/a64/traces/sim-uqrshrn2-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqrshrn2-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshrn2-4s-2opimm-trace-a64.h b/test/a64/traces/sim-uqrshrn2-4s-2opimm-trace-a64.h index a8bb6db0..8662adea 100644 --- a/test/a64/traces/sim-uqrshrn2-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqrshrn2-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqrshrn2-8h-2opimm-trace-a64.h b/test/a64/traces/sim-uqrshrn2-8h-2opimm-trace-a64.h index dfa96218..35c750b7 100644 --- a/test/a64/traces/sim-uqrshrn2-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqrshrn2-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-16b-2opimm-trace-a64.h b/test/a64/traces/sim-uqshl-16b-2opimm-trace-a64.h index bf6e2bd4..1f77d956 100644 --- a/test/a64/traces/sim-uqshl-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshl-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-16b-trace-a64.h b/test/a64/traces/sim-uqshl-16b-trace-a64.h index 695a5381..ed00c0e0 100644 --- a/test/a64/traces/sim-uqshl-16b-trace-a64.h +++ b/test/a64/traces/sim-uqshl-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-2d-2opimm-trace-a64.h b/test/a64/traces/sim-uqshl-2d-2opimm-trace-a64.h index d7433a34..14f55245 100644 --- a/test/a64/traces/sim-uqshl-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshl-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-2d-trace-a64.h b/test/a64/traces/sim-uqshl-2d-trace-a64.h index e413be27..59af6f46 100644 --- a/test/a64/traces/sim-uqshl-2d-trace-a64.h +++ b/test/a64/traces/sim-uqshl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-2s-2opimm-trace-a64.h b/test/a64/traces/sim-uqshl-2s-2opimm-trace-a64.h index b0fca439..4e6e5ca9 100644 --- a/test/a64/traces/sim-uqshl-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshl-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-2s-trace-a64.h b/test/a64/traces/sim-uqshl-2s-trace-a64.h index 13914126..a2e93507 100644 --- a/test/a64/traces/sim-uqshl-2s-trace-a64.h +++ b/test/a64/traces/sim-uqshl-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-4h-2opimm-trace-a64.h b/test/a64/traces/sim-uqshl-4h-2opimm-trace-a64.h index 75369e3e..f435452a 100644 --- a/test/a64/traces/sim-uqshl-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshl-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-4h-trace-a64.h b/test/a64/traces/sim-uqshl-4h-trace-a64.h index b73be938..dc5df9b7 100644 --- a/test/a64/traces/sim-uqshl-4h-trace-a64.h +++ b/test/a64/traces/sim-uqshl-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-4s-2opimm-trace-a64.h b/test/a64/traces/sim-uqshl-4s-2opimm-trace-a64.h index ed14b6ef..dc35c0b2 100644 --- a/test/a64/traces/sim-uqshl-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshl-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-4s-trace-a64.h b/test/a64/traces/sim-uqshl-4s-trace-a64.h index 498ad014..df30de22 100644 --- a/test/a64/traces/sim-uqshl-4s-trace-a64.h +++ b/test/a64/traces/sim-uqshl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-8b-2opimm-trace-a64.h b/test/a64/traces/sim-uqshl-8b-2opimm-trace-a64.h index b4a51356..36a31b80 100644 --- a/test/a64/traces/sim-uqshl-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshl-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-8b-trace-a64.h b/test/a64/traces/sim-uqshl-8b-trace-a64.h index 1ab6a667..2bccc8ad 100644 --- a/test/a64/traces/sim-uqshl-8b-trace-a64.h +++ b/test/a64/traces/sim-uqshl-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-8h-2opimm-trace-a64.h b/test/a64/traces/sim-uqshl-8h-2opimm-trace-a64.h index aecca54d..d1603d06 100644 --- a/test/a64/traces/sim-uqshl-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshl-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-8h-trace-a64.h b/test/a64/traces/sim-uqshl-8h-trace-a64.h index 6c406516..d91d538e 100644 --- a/test/a64/traces/sim-uqshl-8h-trace-a64.h +++ b/test/a64/traces/sim-uqshl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-b-2opimm-trace-a64.h b/test/a64/traces/sim-uqshl-b-2opimm-trace-a64.h index f9142378..c1367aba 100644 --- a/test/a64/traces/sim-uqshl-b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshl-b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-b-trace-a64.h b/test/a64/traces/sim-uqshl-b-trace-a64.h index edd5ca6e..0a7c3a55 100644 --- a/test/a64/traces/sim-uqshl-b-trace-a64.h +++ b/test/a64/traces/sim-uqshl-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-d-2opimm-trace-a64.h b/test/a64/traces/sim-uqshl-d-2opimm-trace-a64.h index 573c2323..1fb78550 100644 --- a/test/a64/traces/sim-uqshl-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshl-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-d-trace-a64.h b/test/a64/traces/sim-uqshl-d-trace-a64.h index 76015d4d..b6580f02 100644 --- a/test/a64/traces/sim-uqshl-d-trace-a64.h +++ b/test/a64/traces/sim-uqshl-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-h-2opimm-trace-a64.h b/test/a64/traces/sim-uqshl-h-2opimm-trace-a64.h index 229f3a42..f23913f2 100644 --- a/test/a64/traces/sim-uqshl-h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshl-h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-h-trace-a64.h b/test/a64/traces/sim-uqshl-h-trace-a64.h index ab5ff987..fbe74ef7 100644 --- a/test/a64/traces/sim-uqshl-h-trace-a64.h +++ b/test/a64/traces/sim-uqshl-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-s-2opimm-trace-a64.h b/test/a64/traces/sim-uqshl-s-2opimm-trace-a64.h index dbc9d8a1..b4468501 100644 --- a/test/a64/traces/sim-uqshl-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshl-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshl-s-trace-a64.h b/test/a64/traces/sim-uqshl-s-trace-a64.h index 774db6c7..d6c6e617 100644 --- a/test/a64/traces/sim-uqshl-s-trace-a64.h +++ b/test/a64/traces/sim-uqshl-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshrn-2s-2opimm-trace-a64.h b/test/a64/traces/sim-uqshrn-2s-2opimm-trace-a64.h index d6ce60d8..b4b05eb6 100644 --- a/test/a64/traces/sim-uqshrn-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshrn-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshrn-4h-2opimm-trace-a64.h b/test/a64/traces/sim-uqshrn-4h-2opimm-trace-a64.h index d25ff8df..cedcc099 100644 --- a/test/a64/traces/sim-uqshrn-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshrn-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshrn-8b-2opimm-trace-a64.h b/test/a64/traces/sim-uqshrn-8b-2opimm-trace-a64.h index ce0684d7..d6e535ba 100644 --- a/test/a64/traces/sim-uqshrn-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshrn-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshrn-b-2opimm-trace-a64.h b/test/a64/traces/sim-uqshrn-b-2opimm-trace-a64.h index a207dae9..edc53453 100644 --- a/test/a64/traces/sim-uqshrn-b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshrn-b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshrn-h-2opimm-trace-a64.h b/test/a64/traces/sim-uqshrn-h-2opimm-trace-a64.h index e9eade1f..dc1f1ac5 100644 --- a/test/a64/traces/sim-uqshrn-h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshrn-h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshrn-s-2opimm-trace-a64.h b/test/a64/traces/sim-uqshrn-s-2opimm-trace-a64.h index 701ee25d..00137cad 100644 --- a/test/a64/traces/sim-uqshrn-s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshrn-s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshrn2-16b-2opimm-trace-a64.h b/test/a64/traces/sim-uqshrn2-16b-2opimm-trace-a64.h index 37fad160..0ff99e03 100644 --- a/test/a64/traces/sim-uqshrn2-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshrn2-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshrn2-4s-2opimm-trace-a64.h b/test/a64/traces/sim-uqshrn2-4s-2opimm-trace-a64.h index 6110e6ea..b7897235 100644 --- a/test/a64/traces/sim-uqshrn2-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshrn2-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqshrn2-8h-2opimm-trace-a64.h b/test/a64/traces/sim-uqshrn2-8h-2opimm-trace-a64.h index 8a6c0701..36b02200 100644 --- a/test/a64/traces/sim-uqshrn2-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-uqshrn2-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqsub-16b-trace-a64.h b/test/a64/traces/sim-uqsub-16b-trace-a64.h index bd9a8dd7..086d0aac 100644 --- a/test/a64/traces/sim-uqsub-16b-trace-a64.h +++ b/test/a64/traces/sim-uqsub-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqsub-2d-trace-a64.h b/test/a64/traces/sim-uqsub-2d-trace-a64.h index 61c2f568..a63629c2 100644 --- a/test/a64/traces/sim-uqsub-2d-trace-a64.h +++ b/test/a64/traces/sim-uqsub-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqsub-2s-trace-a64.h b/test/a64/traces/sim-uqsub-2s-trace-a64.h index 85da2cfa..4ee0fc6b 100644 --- a/test/a64/traces/sim-uqsub-2s-trace-a64.h +++ b/test/a64/traces/sim-uqsub-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqsub-4h-trace-a64.h b/test/a64/traces/sim-uqsub-4h-trace-a64.h index 6435a63d..a18c21d2 100644 --- a/test/a64/traces/sim-uqsub-4h-trace-a64.h +++ b/test/a64/traces/sim-uqsub-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqsub-4s-trace-a64.h b/test/a64/traces/sim-uqsub-4s-trace-a64.h index ae577201..afceff28 100644 --- a/test/a64/traces/sim-uqsub-4s-trace-a64.h +++ b/test/a64/traces/sim-uqsub-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqsub-8b-trace-a64.h b/test/a64/traces/sim-uqsub-8b-trace-a64.h index b0c4ca35..3cd26b3d 100644 --- a/test/a64/traces/sim-uqsub-8b-trace-a64.h +++ b/test/a64/traces/sim-uqsub-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqsub-8h-trace-a64.h b/test/a64/traces/sim-uqsub-8h-trace-a64.h index 805d0adc..f40fb3a7 100644 --- a/test/a64/traces/sim-uqsub-8h-trace-a64.h +++ b/test/a64/traces/sim-uqsub-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqsub-d-trace-a64.h b/test/a64/traces/sim-uqsub-d-trace-a64.h index 5581bcf2..e907de2a 100644 --- a/test/a64/traces/sim-uqsub-d-trace-a64.h +++ b/test/a64/traces/sim-uqsub-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqxtn-2s-trace-a64.h b/test/a64/traces/sim-uqxtn-2s-trace-a64.h index 9f163741..02fca3fb 100644 --- a/test/a64/traces/sim-uqxtn-2s-trace-a64.h +++ b/test/a64/traces/sim-uqxtn-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqxtn-4h-trace-a64.h b/test/a64/traces/sim-uqxtn-4h-trace-a64.h index 47209411..c9853c2a 100644 --- a/test/a64/traces/sim-uqxtn-4h-trace-a64.h +++ b/test/a64/traces/sim-uqxtn-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqxtn-8b-trace-a64.h b/test/a64/traces/sim-uqxtn-8b-trace-a64.h index b2c9bf6a..89493607 100644 --- a/test/a64/traces/sim-uqxtn-8b-trace-a64.h +++ b/test/a64/traces/sim-uqxtn-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqxtn-b-trace-a64.h b/test/a64/traces/sim-uqxtn-b-trace-a64.h index d9ce6ec1..f27fd282 100644 --- a/test/a64/traces/sim-uqxtn-b-trace-a64.h +++ b/test/a64/traces/sim-uqxtn-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqxtn-h-trace-a64.h b/test/a64/traces/sim-uqxtn-h-trace-a64.h index b5123df0..d78f6288 100644 --- a/test/a64/traces/sim-uqxtn-h-trace-a64.h +++ b/test/a64/traces/sim-uqxtn-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqxtn-s-trace-a64.h b/test/a64/traces/sim-uqxtn-s-trace-a64.h index 3b83b0ef..52df32d3 100644 --- a/test/a64/traces/sim-uqxtn-s-trace-a64.h +++ b/test/a64/traces/sim-uqxtn-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqxtn2-16b-trace-a64.h b/test/a64/traces/sim-uqxtn2-16b-trace-a64.h index 60b909e7..5958e566 100644 --- a/test/a64/traces/sim-uqxtn2-16b-trace-a64.h +++ b/test/a64/traces/sim-uqxtn2-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqxtn2-4s-trace-a64.h b/test/a64/traces/sim-uqxtn2-4s-trace-a64.h index d40532b8..62017616 100644 --- a/test/a64/traces/sim-uqxtn2-4s-trace-a64.h +++ b/test/a64/traces/sim-uqxtn2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uqxtn2-8h-trace-a64.h b/test/a64/traces/sim-uqxtn2-8h-trace-a64.h index f3cc9b37..f430c67c 100644 --- a/test/a64/traces/sim-uqxtn2-8h-trace-a64.h +++ b/test/a64/traces/sim-uqxtn2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urecpe-2s-trace-a64.h b/test/a64/traces/sim-urecpe-2s-trace-a64.h index f82a0488..3b7f87c4 100644 --- a/test/a64/traces/sim-urecpe-2s-trace-a64.h +++ b/test/a64/traces/sim-urecpe-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urecpe-4s-trace-a64.h b/test/a64/traces/sim-urecpe-4s-trace-a64.h index f8404d28..45154493 100644 --- a/test/a64/traces/sim-urecpe-4s-trace-a64.h +++ b/test/a64/traces/sim-urecpe-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urhadd-16b-trace-a64.h b/test/a64/traces/sim-urhadd-16b-trace-a64.h index d4396d87..5c27eb34 100644 --- a/test/a64/traces/sim-urhadd-16b-trace-a64.h +++ b/test/a64/traces/sim-urhadd-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urhadd-2s-trace-a64.h b/test/a64/traces/sim-urhadd-2s-trace-a64.h index c0136d5d..3ed6aec1 100644 --- a/test/a64/traces/sim-urhadd-2s-trace-a64.h +++ b/test/a64/traces/sim-urhadd-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urhadd-4h-trace-a64.h b/test/a64/traces/sim-urhadd-4h-trace-a64.h index 89dcd49d..5f3fb542 100644 --- a/test/a64/traces/sim-urhadd-4h-trace-a64.h +++ b/test/a64/traces/sim-urhadd-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urhadd-4s-trace-a64.h b/test/a64/traces/sim-urhadd-4s-trace-a64.h index b6f71f4c..b9dbb798 100644 --- a/test/a64/traces/sim-urhadd-4s-trace-a64.h +++ b/test/a64/traces/sim-urhadd-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urhadd-8b-trace-a64.h b/test/a64/traces/sim-urhadd-8b-trace-a64.h index 58c69941..2171b471 100644 --- a/test/a64/traces/sim-urhadd-8b-trace-a64.h +++ b/test/a64/traces/sim-urhadd-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urhadd-8h-trace-a64.h b/test/a64/traces/sim-urhadd-8h-trace-a64.h index bbafee08..7b8c841a 100644 --- a/test/a64/traces/sim-urhadd-8h-trace-a64.h +++ b/test/a64/traces/sim-urhadd-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshl-16b-trace-a64.h b/test/a64/traces/sim-urshl-16b-trace-a64.h index 4188bc87..0d9cd902 100644 --- a/test/a64/traces/sim-urshl-16b-trace-a64.h +++ b/test/a64/traces/sim-urshl-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshl-2d-trace-a64.h b/test/a64/traces/sim-urshl-2d-trace-a64.h index 3923c322..1bd3ec0d 100644 --- a/test/a64/traces/sim-urshl-2d-trace-a64.h +++ b/test/a64/traces/sim-urshl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshl-2s-trace-a64.h b/test/a64/traces/sim-urshl-2s-trace-a64.h index d3e6df5a..6f536653 100644 --- a/test/a64/traces/sim-urshl-2s-trace-a64.h +++ b/test/a64/traces/sim-urshl-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshl-4h-trace-a64.h b/test/a64/traces/sim-urshl-4h-trace-a64.h index 47990c67..b5588126 100644 --- a/test/a64/traces/sim-urshl-4h-trace-a64.h +++ b/test/a64/traces/sim-urshl-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshl-4s-trace-a64.h b/test/a64/traces/sim-urshl-4s-trace-a64.h index aa934513..3485e6d3 100644 --- a/test/a64/traces/sim-urshl-4s-trace-a64.h +++ b/test/a64/traces/sim-urshl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshl-8b-trace-a64.h b/test/a64/traces/sim-urshl-8b-trace-a64.h index aa1befc8..ca9a8f6c 100644 --- a/test/a64/traces/sim-urshl-8b-trace-a64.h +++ b/test/a64/traces/sim-urshl-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshl-8h-trace-a64.h b/test/a64/traces/sim-urshl-8h-trace-a64.h index e6ead440..e7aababa 100644 --- a/test/a64/traces/sim-urshl-8h-trace-a64.h +++ b/test/a64/traces/sim-urshl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshl-d-trace-a64.h b/test/a64/traces/sim-urshl-d-trace-a64.h index 1f237642..bf066628 100644 --- a/test/a64/traces/sim-urshl-d-trace-a64.h +++ b/test/a64/traces/sim-urshl-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshr-16b-2opimm-trace-a64.h b/test/a64/traces/sim-urshr-16b-2opimm-trace-a64.h index 84e6a6b7..2be33daa 100644 --- a/test/a64/traces/sim-urshr-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-urshr-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshr-2d-2opimm-trace-a64.h b/test/a64/traces/sim-urshr-2d-2opimm-trace-a64.h index a59a061f..b4ac9966 100644 --- a/test/a64/traces/sim-urshr-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-urshr-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshr-2s-2opimm-trace-a64.h b/test/a64/traces/sim-urshr-2s-2opimm-trace-a64.h index b0fcf04f..ddccc6e0 100644 --- a/test/a64/traces/sim-urshr-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-urshr-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshr-4h-2opimm-trace-a64.h b/test/a64/traces/sim-urshr-4h-2opimm-trace-a64.h index 8faeae7f..8a35a3c4 100644 --- a/test/a64/traces/sim-urshr-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-urshr-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshr-4s-2opimm-trace-a64.h b/test/a64/traces/sim-urshr-4s-2opimm-trace-a64.h index af7477cc..9d9ea62c 100644 --- a/test/a64/traces/sim-urshr-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-urshr-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshr-8b-2opimm-trace-a64.h b/test/a64/traces/sim-urshr-8b-2opimm-trace-a64.h index 084c3115..f776eaec 100644 --- a/test/a64/traces/sim-urshr-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-urshr-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshr-8h-2opimm-trace-a64.h b/test/a64/traces/sim-urshr-8h-2opimm-trace-a64.h index 7fe8b0b3..95f5521f 100644 --- a/test/a64/traces/sim-urshr-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-urshr-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-urshr-d-2opimm-trace-a64.h b/test/a64/traces/sim-urshr-d-2opimm-trace-a64.h index af95403b..872e639e 100644 --- a/test/a64/traces/sim-urshr-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-urshr-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ursqrte-2s-trace-a64.h b/test/a64/traces/sim-ursqrte-2s-trace-a64.h index e5f52b8e..90eef21f 100644 --- a/test/a64/traces/sim-ursqrte-2s-trace-a64.h +++ b/test/a64/traces/sim-ursqrte-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ursqrte-4s-trace-a64.h b/test/a64/traces/sim-ursqrte-4s-trace-a64.h index 1dfbea60..93f978fa 100644 --- a/test/a64/traces/sim-ursqrte-4s-trace-a64.h +++ b/test/a64/traces/sim-ursqrte-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ursra-16b-2opimm-trace-a64.h b/test/a64/traces/sim-ursra-16b-2opimm-trace-a64.h index 146c764d..03197d9d 100644 --- a/test/a64/traces/sim-ursra-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ursra-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ursra-2d-2opimm-trace-a64.h b/test/a64/traces/sim-ursra-2d-2opimm-trace-a64.h index f666722b..c454d352 100644 --- a/test/a64/traces/sim-ursra-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ursra-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ursra-2s-2opimm-trace-a64.h b/test/a64/traces/sim-ursra-2s-2opimm-trace-a64.h index 497a3d1c..b4b42bba 100644 --- a/test/a64/traces/sim-ursra-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ursra-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ursra-4h-2opimm-trace-a64.h b/test/a64/traces/sim-ursra-4h-2opimm-trace-a64.h index 9baa46e4..fb8b2e32 100644 --- a/test/a64/traces/sim-ursra-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ursra-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ursra-4s-2opimm-trace-a64.h b/test/a64/traces/sim-ursra-4s-2opimm-trace-a64.h index a8e4ef74..f38e17e1 100644 --- a/test/a64/traces/sim-ursra-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ursra-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ursra-8b-2opimm-trace-a64.h b/test/a64/traces/sim-ursra-8b-2opimm-trace-a64.h index 5962619c..5a8a1f95 100644 --- a/test/a64/traces/sim-ursra-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ursra-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ursra-8h-2opimm-trace-a64.h b/test/a64/traces/sim-ursra-8h-2opimm-trace-a64.h index 784591d3..1600f100 100644 --- a/test/a64/traces/sim-ursra-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ursra-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ursra-d-2opimm-trace-a64.h b/test/a64/traces/sim-ursra-d-2opimm-trace-a64.h index 9d6a7e95..17b877df 100644 --- a/test/a64/traces/sim-ursra-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ursra-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushl-16b-trace-a64.h b/test/a64/traces/sim-ushl-16b-trace-a64.h index 488459a1..cdd49839 100644 --- a/test/a64/traces/sim-ushl-16b-trace-a64.h +++ b/test/a64/traces/sim-ushl-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushl-2d-trace-a64.h b/test/a64/traces/sim-ushl-2d-trace-a64.h index 0cebd990..fde7934a 100644 --- a/test/a64/traces/sim-ushl-2d-trace-a64.h +++ b/test/a64/traces/sim-ushl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushl-2s-trace-a64.h b/test/a64/traces/sim-ushl-2s-trace-a64.h index 3ed99aff..8423c061 100644 --- a/test/a64/traces/sim-ushl-2s-trace-a64.h +++ b/test/a64/traces/sim-ushl-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushl-4h-trace-a64.h b/test/a64/traces/sim-ushl-4h-trace-a64.h index 552de545..9707bba4 100644 --- a/test/a64/traces/sim-ushl-4h-trace-a64.h +++ b/test/a64/traces/sim-ushl-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushl-4s-trace-a64.h b/test/a64/traces/sim-ushl-4s-trace-a64.h index 7b334bd6..95dee69b 100644 --- a/test/a64/traces/sim-ushl-4s-trace-a64.h +++ b/test/a64/traces/sim-ushl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushl-8b-trace-a64.h b/test/a64/traces/sim-ushl-8b-trace-a64.h index 39f066a8..80a8ca49 100644 --- a/test/a64/traces/sim-ushl-8b-trace-a64.h +++ b/test/a64/traces/sim-ushl-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushl-8h-trace-a64.h b/test/a64/traces/sim-ushl-8h-trace-a64.h index 1317dc47..7d890199 100644 --- a/test/a64/traces/sim-ushl-8h-trace-a64.h +++ b/test/a64/traces/sim-ushl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushl-d-trace-a64.h b/test/a64/traces/sim-ushl-d-trace-a64.h index e52b8762..340292c9 100644 --- a/test/a64/traces/sim-ushl-d-trace-a64.h +++ b/test/a64/traces/sim-ushl-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushll-2d-2opimm-trace-a64.h b/test/a64/traces/sim-ushll-2d-2opimm-trace-a64.h index a853db97..27b9a990 100644 --- a/test/a64/traces/sim-ushll-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushll-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushll-4s-2opimm-trace-a64.h b/test/a64/traces/sim-ushll-4s-2opimm-trace-a64.h index 3466837b..0ef23ff6 100644 --- a/test/a64/traces/sim-ushll-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushll-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushll-8h-2opimm-trace-a64.h b/test/a64/traces/sim-ushll-8h-2opimm-trace-a64.h index 0d52445a..7a1cceb0 100644 --- a/test/a64/traces/sim-ushll-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushll-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushll2-2d-2opimm-trace-a64.h b/test/a64/traces/sim-ushll2-2d-2opimm-trace-a64.h index 7a70b467..630385f5 100644 --- a/test/a64/traces/sim-ushll2-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushll2-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushll2-4s-2opimm-trace-a64.h b/test/a64/traces/sim-ushll2-4s-2opimm-trace-a64.h index dd124ec4..3962a174 100644 --- a/test/a64/traces/sim-ushll2-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushll2-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushll2-8h-2opimm-trace-a64.h b/test/a64/traces/sim-ushll2-8h-2opimm-trace-a64.h index a22b89ed..09383133 100644 --- a/test/a64/traces/sim-ushll2-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushll2-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushr-16b-2opimm-trace-a64.h b/test/a64/traces/sim-ushr-16b-2opimm-trace-a64.h index 9f23cb84..e31f8ffb 100644 --- a/test/a64/traces/sim-ushr-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushr-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushr-2d-2opimm-trace-a64.h b/test/a64/traces/sim-ushr-2d-2opimm-trace-a64.h index ab9840e4..c4ae9469 100644 --- a/test/a64/traces/sim-ushr-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushr-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushr-2s-2opimm-trace-a64.h b/test/a64/traces/sim-ushr-2s-2opimm-trace-a64.h index 5493b5ab..f83a4506 100644 --- a/test/a64/traces/sim-ushr-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushr-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushr-4h-2opimm-trace-a64.h b/test/a64/traces/sim-ushr-4h-2opimm-trace-a64.h index f1888ae8..88f9243a 100644 --- a/test/a64/traces/sim-ushr-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushr-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushr-4s-2opimm-trace-a64.h b/test/a64/traces/sim-ushr-4s-2opimm-trace-a64.h index 9856e829..5eba9a0c 100644 --- a/test/a64/traces/sim-ushr-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushr-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushr-8b-2opimm-trace-a64.h b/test/a64/traces/sim-ushr-8b-2opimm-trace-a64.h index 85821491..b3080a02 100644 --- a/test/a64/traces/sim-ushr-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushr-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushr-8h-2opimm-trace-a64.h b/test/a64/traces/sim-ushr-8h-2opimm-trace-a64.h index 9de8f911..4ef79564 100644 --- a/test/a64/traces/sim-ushr-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushr-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-ushr-d-2opimm-trace-a64.h b/test/a64/traces/sim-ushr-d-2opimm-trace-a64.h index f106cc91..b6212ece 100644 --- a/test/a64/traces/sim-ushr-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-ushr-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usqadd-16b-trace-a64.h b/test/a64/traces/sim-usqadd-16b-trace-a64.h index 932a1d04..d8c7fba6 100644 --- a/test/a64/traces/sim-usqadd-16b-trace-a64.h +++ b/test/a64/traces/sim-usqadd-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usqadd-2d-trace-a64.h b/test/a64/traces/sim-usqadd-2d-trace-a64.h index 162717b0..ca4e0bfc 100644 --- a/test/a64/traces/sim-usqadd-2d-trace-a64.h +++ b/test/a64/traces/sim-usqadd-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usqadd-2s-trace-a64.h b/test/a64/traces/sim-usqadd-2s-trace-a64.h index 1243d6e9..649f8cb3 100644 --- a/test/a64/traces/sim-usqadd-2s-trace-a64.h +++ b/test/a64/traces/sim-usqadd-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usqadd-4h-trace-a64.h b/test/a64/traces/sim-usqadd-4h-trace-a64.h index dbc0e654..6546fd54 100644 --- a/test/a64/traces/sim-usqadd-4h-trace-a64.h +++ b/test/a64/traces/sim-usqadd-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usqadd-4s-trace-a64.h b/test/a64/traces/sim-usqadd-4s-trace-a64.h index 8dbd4d0c..b438fa98 100644 --- a/test/a64/traces/sim-usqadd-4s-trace-a64.h +++ b/test/a64/traces/sim-usqadd-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usqadd-8b-trace-a64.h b/test/a64/traces/sim-usqadd-8b-trace-a64.h index 1ac5345d..56d4e8cf 100644 --- a/test/a64/traces/sim-usqadd-8b-trace-a64.h +++ b/test/a64/traces/sim-usqadd-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usqadd-8h-trace-a64.h b/test/a64/traces/sim-usqadd-8h-trace-a64.h index 14dc28a4..f9a3b916 100644 --- a/test/a64/traces/sim-usqadd-8h-trace-a64.h +++ b/test/a64/traces/sim-usqadd-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usqadd-b-trace-a64.h b/test/a64/traces/sim-usqadd-b-trace-a64.h index 8f1b8863..104e7dee 100644 --- a/test/a64/traces/sim-usqadd-b-trace-a64.h +++ b/test/a64/traces/sim-usqadd-b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usqadd-d-trace-a64.h b/test/a64/traces/sim-usqadd-d-trace-a64.h index e7ebd45d..9ce58c78 100644 --- a/test/a64/traces/sim-usqadd-d-trace-a64.h +++ b/test/a64/traces/sim-usqadd-d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usqadd-h-trace-a64.h b/test/a64/traces/sim-usqadd-h-trace-a64.h index 0e098821..aeab5ba3 100644 --- a/test/a64/traces/sim-usqadd-h-trace-a64.h +++ b/test/a64/traces/sim-usqadd-h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usqadd-s-trace-a64.h b/test/a64/traces/sim-usqadd-s-trace-a64.h index f0c43178..00ce2408 100644 --- a/test/a64/traces/sim-usqadd-s-trace-a64.h +++ b/test/a64/traces/sim-usqadd-s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usra-16b-2opimm-trace-a64.h b/test/a64/traces/sim-usra-16b-2opimm-trace-a64.h index 5fbf674e..238dfbb2 100644 --- a/test/a64/traces/sim-usra-16b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-usra-16b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usra-2d-2opimm-trace-a64.h b/test/a64/traces/sim-usra-2d-2opimm-trace-a64.h index b87edf7e..952c18d0 100644 --- a/test/a64/traces/sim-usra-2d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-usra-2d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usra-2s-2opimm-trace-a64.h b/test/a64/traces/sim-usra-2s-2opimm-trace-a64.h index 43ff8dcd..79cc8ae8 100644 --- a/test/a64/traces/sim-usra-2s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-usra-2s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usra-4h-2opimm-trace-a64.h b/test/a64/traces/sim-usra-4h-2opimm-trace-a64.h index 7894d159..4b916fc1 100644 --- a/test/a64/traces/sim-usra-4h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-usra-4h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usra-4s-2opimm-trace-a64.h b/test/a64/traces/sim-usra-4s-2opimm-trace-a64.h index cf77bc10..3013bbc6 100644 --- a/test/a64/traces/sim-usra-4s-2opimm-trace-a64.h +++ b/test/a64/traces/sim-usra-4s-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usra-8b-2opimm-trace-a64.h b/test/a64/traces/sim-usra-8b-2opimm-trace-a64.h index 0c6e7389..0d9bc5e6 100644 --- a/test/a64/traces/sim-usra-8b-2opimm-trace-a64.h +++ b/test/a64/traces/sim-usra-8b-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usra-8h-2opimm-trace-a64.h b/test/a64/traces/sim-usra-8h-2opimm-trace-a64.h index 5c016d78..38b24be4 100644 --- a/test/a64/traces/sim-usra-8h-2opimm-trace-a64.h +++ b/test/a64/traces/sim-usra-8h-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usra-d-2opimm-trace-a64.h b/test/a64/traces/sim-usra-d-2opimm-trace-a64.h index 9e237862..3a1292e2 100644 --- a/test/a64/traces/sim-usra-d-2opimm-trace-a64.h +++ b/test/a64/traces/sim-usra-d-2opimm-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usubl-2d-trace-a64.h b/test/a64/traces/sim-usubl-2d-trace-a64.h index 7e026d83..2192a973 100644 --- a/test/a64/traces/sim-usubl-2d-trace-a64.h +++ b/test/a64/traces/sim-usubl-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usubl-4s-trace-a64.h b/test/a64/traces/sim-usubl-4s-trace-a64.h index 50fe58b1..5702929c 100644 --- a/test/a64/traces/sim-usubl-4s-trace-a64.h +++ b/test/a64/traces/sim-usubl-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usubl-8h-trace-a64.h b/test/a64/traces/sim-usubl-8h-trace-a64.h index 6e2897cf..39d57b70 100644 --- a/test/a64/traces/sim-usubl-8h-trace-a64.h +++ b/test/a64/traces/sim-usubl-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usubl2-2d-trace-a64.h b/test/a64/traces/sim-usubl2-2d-trace-a64.h index 62609c76..48cad308 100644 --- a/test/a64/traces/sim-usubl2-2d-trace-a64.h +++ b/test/a64/traces/sim-usubl2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usubl2-4s-trace-a64.h b/test/a64/traces/sim-usubl2-4s-trace-a64.h index 9d762a05..486ea3cc 100644 --- a/test/a64/traces/sim-usubl2-4s-trace-a64.h +++ b/test/a64/traces/sim-usubl2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usubl2-8h-trace-a64.h b/test/a64/traces/sim-usubl2-8h-trace-a64.h index 46342912..7c43743a 100644 --- a/test/a64/traces/sim-usubl2-8h-trace-a64.h +++ b/test/a64/traces/sim-usubl2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usubw-2d-trace-a64.h b/test/a64/traces/sim-usubw-2d-trace-a64.h index 88e51093..c21af254 100644 --- a/test/a64/traces/sim-usubw-2d-trace-a64.h +++ b/test/a64/traces/sim-usubw-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usubw-4s-trace-a64.h b/test/a64/traces/sim-usubw-4s-trace-a64.h index 440d70bc..0233bca3 100644 --- a/test/a64/traces/sim-usubw-4s-trace-a64.h +++ b/test/a64/traces/sim-usubw-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usubw-8h-trace-a64.h b/test/a64/traces/sim-usubw-8h-trace-a64.h index daed4072..b972c038 100644 --- a/test/a64/traces/sim-usubw-8h-trace-a64.h +++ b/test/a64/traces/sim-usubw-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usubw2-2d-trace-a64.h b/test/a64/traces/sim-usubw2-2d-trace-a64.h index 5aaa0ffa..c58489c9 100644 --- a/test/a64/traces/sim-usubw2-2d-trace-a64.h +++ b/test/a64/traces/sim-usubw2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usubw2-4s-trace-a64.h b/test/a64/traces/sim-usubw2-4s-trace-a64.h index 9c35013e..fafc866c 100644 --- a/test/a64/traces/sim-usubw2-4s-trace-a64.h +++ b/test/a64/traces/sim-usubw2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-usubw2-8h-trace-a64.h b/test/a64/traces/sim-usubw2-8h-trace-a64.h index af1eb173..d387c4d0 100644 --- a/test/a64/traces/sim-usubw2-8h-trace-a64.h +++ b/test/a64/traces/sim-usubw2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp1-16b-trace-a64.h b/test/a64/traces/sim-uzp1-16b-trace-a64.h index 4636fcd7..91d598c8 100644 --- a/test/a64/traces/sim-uzp1-16b-trace-a64.h +++ b/test/a64/traces/sim-uzp1-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp1-2d-trace-a64.h b/test/a64/traces/sim-uzp1-2d-trace-a64.h index b9f7b887..d69b43e7 100644 --- a/test/a64/traces/sim-uzp1-2d-trace-a64.h +++ b/test/a64/traces/sim-uzp1-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp1-2s-trace-a64.h b/test/a64/traces/sim-uzp1-2s-trace-a64.h index b8848e28..8809cc66 100644 --- a/test/a64/traces/sim-uzp1-2s-trace-a64.h +++ b/test/a64/traces/sim-uzp1-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp1-4h-trace-a64.h b/test/a64/traces/sim-uzp1-4h-trace-a64.h index b098444f..1745224f 100644 --- a/test/a64/traces/sim-uzp1-4h-trace-a64.h +++ b/test/a64/traces/sim-uzp1-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp1-4s-trace-a64.h b/test/a64/traces/sim-uzp1-4s-trace-a64.h index 6e23c508..42a8d203 100644 --- a/test/a64/traces/sim-uzp1-4s-trace-a64.h +++ b/test/a64/traces/sim-uzp1-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp1-8b-trace-a64.h b/test/a64/traces/sim-uzp1-8b-trace-a64.h index 5f7c7a92..bf9ed052 100644 --- a/test/a64/traces/sim-uzp1-8b-trace-a64.h +++ b/test/a64/traces/sim-uzp1-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp1-8h-trace-a64.h b/test/a64/traces/sim-uzp1-8h-trace-a64.h index e7d44531..f973db78 100644 --- a/test/a64/traces/sim-uzp1-8h-trace-a64.h +++ b/test/a64/traces/sim-uzp1-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp2-16b-trace-a64.h b/test/a64/traces/sim-uzp2-16b-trace-a64.h index 73359032..74d5ffa6 100644 --- a/test/a64/traces/sim-uzp2-16b-trace-a64.h +++ b/test/a64/traces/sim-uzp2-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp2-2d-trace-a64.h b/test/a64/traces/sim-uzp2-2d-trace-a64.h index 6cf4cd55..25484cdd 100644 --- a/test/a64/traces/sim-uzp2-2d-trace-a64.h +++ b/test/a64/traces/sim-uzp2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp2-2s-trace-a64.h b/test/a64/traces/sim-uzp2-2s-trace-a64.h index 4873a937..bc5b6cee 100644 --- a/test/a64/traces/sim-uzp2-2s-trace-a64.h +++ b/test/a64/traces/sim-uzp2-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp2-4h-trace-a64.h b/test/a64/traces/sim-uzp2-4h-trace-a64.h index b5373808..159c0d4f 100644 --- a/test/a64/traces/sim-uzp2-4h-trace-a64.h +++ b/test/a64/traces/sim-uzp2-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp2-4s-trace-a64.h b/test/a64/traces/sim-uzp2-4s-trace-a64.h index 7fa602bf..454acf70 100644 --- a/test/a64/traces/sim-uzp2-4s-trace-a64.h +++ b/test/a64/traces/sim-uzp2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp2-8b-trace-a64.h b/test/a64/traces/sim-uzp2-8b-trace-a64.h index ecf71aa5..7887b4a5 100644 --- a/test/a64/traces/sim-uzp2-8b-trace-a64.h +++ b/test/a64/traces/sim-uzp2-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-uzp2-8h-trace-a64.h b/test/a64/traces/sim-uzp2-8h-trace-a64.h index 4ed38200..b8838b34 100644 --- a/test/a64/traces/sim-uzp2-8h-trace-a64.h +++ b/test/a64/traces/sim-uzp2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-xtn-2s-trace-a64.h b/test/a64/traces/sim-xtn-2s-trace-a64.h index 0f3f529d..eb52ccd5 100644 --- a/test/a64/traces/sim-xtn-2s-trace-a64.h +++ b/test/a64/traces/sim-xtn-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-xtn-4h-trace-a64.h b/test/a64/traces/sim-xtn-4h-trace-a64.h index 29ca6af6..fd1236a1 100644 --- a/test/a64/traces/sim-xtn-4h-trace-a64.h +++ b/test/a64/traces/sim-xtn-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-xtn-8b-trace-a64.h b/test/a64/traces/sim-xtn-8b-trace-a64.h index f681a48d..07869137 100644 --- a/test/a64/traces/sim-xtn-8b-trace-a64.h +++ b/test/a64/traces/sim-xtn-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-xtn2-16b-trace-a64.h b/test/a64/traces/sim-xtn2-16b-trace-a64.h index 37d555d1..43266612 100644 --- a/test/a64/traces/sim-xtn2-16b-trace-a64.h +++ b/test/a64/traces/sim-xtn2-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-xtn2-4s-trace-a64.h b/test/a64/traces/sim-xtn2-4s-trace-a64.h index 3a985e74..1a9f4a6e 100644 --- a/test/a64/traces/sim-xtn2-4s-trace-a64.h +++ b/test/a64/traces/sim-xtn2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-xtn2-8h-trace-a64.h b/test/a64/traces/sim-xtn2-8h-trace-a64.h index a5a32807..0fe7a1bc 100644 --- a/test/a64/traces/sim-xtn2-8h-trace-a64.h +++ b/test/a64/traces/sim-xtn2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip1-16b-trace-a64.h b/test/a64/traces/sim-zip1-16b-trace-a64.h index 1219f6a3..47443f80 100644 --- a/test/a64/traces/sim-zip1-16b-trace-a64.h +++ b/test/a64/traces/sim-zip1-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip1-2d-trace-a64.h b/test/a64/traces/sim-zip1-2d-trace-a64.h index 7241bce3..9957d33b 100644 --- a/test/a64/traces/sim-zip1-2d-trace-a64.h +++ b/test/a64/traces/sim-zip1-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip1-2s-trace-a64.h b/test/a64/traces/sim-zip1-2s-trace-a64.h index b5ff6eb9..41dd2788 100644 --- a/test/a64/traces/sim-zip1-2s-trace-a64.h +++ b/test/a64/traces/sim-zip1-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip1-4h-trace-a64.h b/test/a64/traces/sim-zip1-4h-trace-a64.h index 3525ef51..4336cf57 100644 --- a/test/a64/traces/sim-zip1-4h-trace-a64.h +++ b/test/a64/traces/sim-zip1-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip1-4s-trace-a64.h b/test/a64/traces/sim-zip1-4s-trace-a64.h index e30daf4d..eb8eb2a9 100644 --- a/test/a64/traces/sim-zip1-4s-trace-a64.h +++ b/test/a64/traces/sim-zip1-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip1-8b-trace-a64.h b/test/a64/traces/sim-zip1-8b-trace-a64.h index f53ebb49..4a229e31 100644 --- a/test/a64/traces/sim-zip1-8b-trace-a64.h +++ b/test/a64/traces/sim-zip1-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip1-8h-trace-a64.h b/test/a64/traces/sim-zip1-8h-trace-a64.h index 652cba30..97186658 100644 --- a/test/a64/traces/sim-zip1-8h-trace-a64.h +++ b/test/a64/traces/sim-zip1-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip2-16b-trace-a64.h b/test/a64/traces/sim-zip2-16b-trace-a64.h index 34ad61c3..3fb964ca 100644 --- a/test/a64/traces/sim-zip2-16b-trace-a64.h +++ b/test/a64/traces/sim-zip2-16b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip2-2d-trace-a64.h b/test/a64/traces/sim-zip2-2d-trace-a64.h index 3a3a1433..8e987728 100644 --- a/test/a64/traces/sim-zip2-2d-trace-a64.h +++ b/test/a64/traces/sim-zip2-2d-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip2-2s-trace-a64.h b/test/a64/traces/sim-zip2-2s-trace-a64.h index 7273a03f..98532473 100644 --- a/test/a64/traces/sim-zip2-2s-trace-a64.h +++ b/test/a64/traces/sim-zip2-2s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip2-4h-trace-a64.h b/test/a64/traces/sim-zip2-4h-trace-a64.h index 3963b834..1c774888 100644 --- a/test/a64/traces/sim-zip2-4h-trace-a64.h +++ b/test/a64/traces/sim-zip2-4h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip2-4s-trace-a64.h b/test/a64/traces/sim-zip2-4s-trace-a64.h index 57d48483..05174543 100644 --- a/test/a64/traces/sim-zip2-4s-trace-a64.h +++ b/test/a64/traces/sim-zip2-4s-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip2-8b-trace-a64.h b/test/a64/traces/sim-zip2-8b-trace-a64.h index cbb4720f..961917b6 100644 --- a/test/a64/traces/sim-zip2-8b-trace-a64.h +++ b/test/a64/traces/sim-zip2-8b-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/a64/traces/sim-zip2-8h-trace-a64.h b/test/a64/traces/sim-zip2-8h-trace-a64.h index 543522a3..28b06e93 100644 --- a/test/a64/traces/sim-zip2-8h-trace-a64.h +++ b/test/a64/traces/sim-zip2-8h-trace-a64.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/test-invalset.cc b/test/test-invalset.cc index 4985fbf6..f8af5bf8 100644 --- a/test/test-invalset.cc +++ b/test/test-invalset.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/test-runner.cc b/test/test-runner.cc index 3382eb10..6a455049 100644 --- a/test/test-runner.cc +++ b/test/test-runner.cc @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/test-runner.h b/test/test-runner.h index e056c087..5b60f650 100644 --- a/test/test-runner.h +++ b/test/test-runner.h @@ -1,4 +1,4 @@ -// Copyright 2014, ARM Limited +// Copyright 2014, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/test-utils.cc b/test/test-utils.cc index abbc6b9e..cc6d2d16 100644 --- a/test/test-utils.cc +++ b/test/test-utils.cc @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/test/test-utils.h b/test/test-utils.h index 5ae32ad4..bf250a2e 100644 --- a/test/test-utils.h +++ b/test/test-utils.h @@ -1,4 +1,4 @@ -// Copyright 2015, ARM Limited +// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/third_party/android/Android.mk.template b/third_party/android/Android.mk.template index dc1c2965..30210fc7 100644 --- a/third_party/android/Android.mk.template +++ b/third_party/android/Android.mk.template @@ -30,7 +30,7 @@ # SUCH DAMAGE. # # -# Copyright (c) 2015 ARM Ltd +# Copyright (c) 2015 VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/third_party/android/generate_android_mk.py b/third_party/android/generate_android_mk.py index 80cff31f..2c5c6329 100755 --- a/third_party/android/generate_android_mk.py +++ b/third_party/android/generate_android_mk.py @@ -1,6 +1,6 @@ #!/usr/bin/env python2.7 -# Copyright 2015, ARM Limited +# Copyright 2015, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/clang_format.py b/tools/clang_format.py index d838cabb..12a14be4 100755 --- a/tools/clang_format.py +++ b/tools/clang_format.py @@ -1,6 +1,6 @@ #!/usr/bin/env python2.7 -# Copyright 2016, ARM Limited +# Copyright 2016, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/config.py b/tools/config.py index 883045a5..4fceec78 100644 --- a/tools/config.py +++ b/tools/config.py @@ -1,4 +1,4 @@ -# Copyright 2015, ARM Limited +# Copyright 2015, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/cross_build_gcc.sh b/tools/cross_build_gcc.sh index 1a646dde..97448ae2 100755 --- a/tools/cross_build_gcc.sh +++ b/tools/cross_build_gcc.sh @@ -1,6 +1,6 @@ #!/bin/sh -# Copyright 2013, ARM Limited +# Copyright 2013, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/generate_simulator_traces.py b/tools/generate_simulator_traces.py index 4a5ffe89..ef1fd33e 100755 --- a/tools/generate_simulator_traces.py +++ b/tools/generate_simulator_traces.py @@ -1,6 +1,6 @@ #!/usr/bin/env python2.7 -# Copyright 2015, ARM Limited +# Copyright 2015, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -32,7 +32,7 @@ import argparse import re import util -copyright_header = """// Copyright 2015, ARM Limited +copyright_header = """// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/tools/generate_test_trace_a64_reference.py b/tools/generate_test_trace_a64_reference.py index fd2bdb7d..cef06fb3 100755 --- a/tools/generate_test_trace_a64_reference.py +++ b/tools/generate_test_trace_a64_reference.py @@ -1,6 +1,6 @@ #!/usr/bin/env python2.7 -# Copyright 2016, ARM Limited +# Copyright 2016, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/generate_tests.py b/tools/generate_tests.py index 634da52e..1c29bf23 100755 --- a/tools/generate_tests.py +++ b/tools/generate_tests.py @@ -1,6 +1,6 @@ #!/usr/bin/env python3 -# Copyright 2016, ARM Limited +# Copyright 2016, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/git.py b/tools/git.py index 2fca3edf..7c234cdb 100644 --- a/tools/git.py +++ b/tools/git.py @@ -1,4 +1,4 @@ -# Copyright 2014, ARM Limited +# Copyright 2014, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/lint.py b/tools/lint.py index fa995252..14db8b99 100755 --- a/tools/lint.py +++ b/tools/lint.py @@ -1,6 +1,6 @@ #!/usr/bin/env python2.7 -# Copyright 2015, ARM Limited +# Copyright 2015, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/make_instruction_doc.pl b/tools/make_instruction_doc.pl index d5c2c679..f33fd15a 100755 --- a/tools/make_instruction_doc.pl +++ b/tools/make_instruction_doc.pl @@ -1,6 +1,6 @@ #!/usr/bin/perl -# Copyright 2015, ARM Limited +# Copyright 2015, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/printer.py b/tools/printer.py index dc97a5bc..4a37a340 100644 --- a/tools/printer.py +++ b/tools/printer.py @@ -1,6 +1,6 @@ #!/usr/bin/env python2.7 -# Copyright 2014, ARM Limited +# Copyright 2014, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/test.py b/tools/test.py index 5445191f..8bfd2c2c 100755 --- a/tools/test.py +++ b/tools/test.py @@ -1,6 +1,6 @@ #!/usr/bin/env python2.7 -# Copyright 2015, ARM Limited +# Copyright 2015, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/test_generator/data_types.py b/tools/test_generator/data_types.py index 432191b8..99571698 100644 --- a/tools/test_generator/data_types.py +++ b/tools/test_generator/data_types.py @@ -1,4 +1,4 @@ -# Copyright 2016, ARM Limited +# Copyright 2016, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/test_generator/generator.py b/tools/test_generator/generator.py index d8665ce5..75b99aa9 100644 --- a/tools/test_generator/generator.py +++ b/tools/test_generator/generator.py @@ -1,4 +1,4 @@ -# Copyright 2016, ARM Limited +# Copyright 2016, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/test_generator/parser.py b/tools/test_generator/parser.py index 3f3a0248..b9a6797c 100644 --- a/tools/test_generator/parser.py +++ b/tools/test_generator/parser.py @@ -1,4 +1,4 @@ -# Copyright 2016, ARM Limited +# Copyright 2016, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/threaded_tests.py b/tools/threaded_tests.py index 37001422..e48b3bb4 100644 --- a/tools/threaded_tests.py +++ b/tools/threaded_tests.py @@ -1,4 +1,4 @@ -# Copyright 2015, ARM Limited +# Copyright 2015, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/util.py b/tools/util.py index 6a713601..f087d86f 100644 --- a/tools/util.py +++ b/tools/util.py @@ -1,4 +1,4 @@ -# Copyright 2015, ARM Limited +# Copyright 2015, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tools/verify_assembler_traces.py b/tools/verify_assembler_traces.py index 1162a85f..3508c86f 100755 --- a/tools/verify_assembler_traces.py +++ b/tools/verify_assembler_traces.py @@ -1,6 +1,6 @@ #!/usr/bin/env python3 -# Copyright 2016, ARM Limited +# Copyright 2016, VIXL authors # All rights reserved. # # Redistribution and use in source and binary forms, with or without