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<instructionsection id="STSMAXH_LDSMAXH" title="STSMAXH, STSMAXLH -- A64" type="alias">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A64" />
  </docvars>
  <heading>STSMAXH, STSMAXLH</heading>
  <desc>
    <brief>
      <para>Atomic signed maximum on halfword in memory, without return</para>
    </brief>
    <authored>
      <para>Atomic signed maximum on halfword in memory, without return, atomically loads a 16-bit halfword from memory, compares it against the value held in a register, and stores the larger value back to memory, treating the values as signed numbers.</para>
      <list type="unordered">
        <listitem><content><instruction>STSMAXH</instruction> does not have release semantics.</content></listitem>
        <listitem><content><instruction>STSMAXLH</instruction> stores to memory with release semantics, as described in <xref linkend="BEIHCHEF">Load-Acquire, Store-Release</xref>.</content></listitem>
      </list>
      <para>For information about memory accesses see <xref linkend="CHDIIIBB">Load/Store addressing modes</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <aliasto refiform="ldsmaxh.xml" iformid="LDSMAXH">LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH</aliasto>
  <classes>
    <iclass name="Integer" oneof="1" id="iclass_general" no_encodings="2" isa="A64">
      <docvars>
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A64" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.1" feature="FEAT_LSE" />
      </arch_variants>
      <regdiagram form="32" psname="aarch64/instrs/memory/atomicops/ld" tworows="1">
        <box hibit="31" width="2" name="size" usename="1" settings="2" psbits="xx">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="29" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="26" name="V" settings="1">
          <c>0</c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" name="A" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="22" name="R" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="5" name="Rs" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" name="o3" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="opc" usename="1" settings="3" psbits="xxx">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rt" usename="1" settings="5" psbits="xxxxx">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
      </regdiagram>
      <encoding name="STSMAXH_LDSMAXH_32_memop" oneofinclass="2" oneof="2" label="No memory ordering" bitdiffs="R == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="STSMAXH" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A64" />
          <docvar key="loadstore-order" value="no-order" />
          <docvar key="mnemonic" value="LDSMAXH" />
        </docvars>
        <box hibit="22" width="1" name="R">
          <c>0</c>
        </box>
        <asmtemplate><text>STSMAXH  </text><a link="sa_ws" hover="32-bit general-purpose register holding data value to be operated on with the contents of memory location (field &quot;Rs&quot;)">&lt;Ws&gt;</a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="ldsmaxh.xml#LDSMAXH_32_memop">LDSMAXH</a><text> </text><a link="sa_ws" hover="32-bit general-purpose register holding data value to be operated on with the contents of memory location (field &quot;Rs&quot;)">&lt;Ws&gt;</a><text>, WZR, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="STSMAXLH_LDSMAXLH_32_memop" oneofinclass="2" oneof="2" label="Release" bitdiffs="R == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="STSMAXLH" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A64" />
          <docvar key="loadstore-order" value="release" />
          <docvar key="mnemonic" value="LDSMAXLH" />
        </docvars>
        <box hibit="22" width="1" name="R">
          <c>1</c>
        </box>
        <asmtemplate><text>STSMAXLH  </text><a link="sa_ws" hover="32-bit general-purpose register holding data value to be operated on with the contents of memory location (field &quot;Rs&quot;)">&lt;Ws&gt;</a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="ldsmaxh.xml#LDSMAXLH_32_memop">LDSMAXLH</a><text> </text><a link="sa_ws" hover="32-bit general-purpose register holding data value to be operated on with the contents of memory location (field &quot;Rs&quot;)">&lt;Ws&gt;</a><text>, WZR, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STSMAXH_LDSMAXH_32_memop" symboldefcount="1">
      <symbol link="sa_ws">&lt;Ws&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STSMAXH_LDSMAXH_32_memop" symboldefcount="1">
      <symbol link="sa_xn_sp">&lt;Xn|SP&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
