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<instructionsection id="FRINT64X_advsimd" title="FRINT64X (vector) -- A64" type="instruction">
  <docvars>
    <docvar key="advsimd-datatype" value="simd-single-and-double" />
    <docvar key="advsimd-type" value="simd" />
    <docvar key="datatype" value="single-and-double" />
    <docvar key="instr-class" value="advsimd" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="FRINT64X" />
  </docvars>
  <heading>FRINT64X (vector)</heading>
  <desc>
    <brief>
      <para>Floating-point Round to 64-bit Integer, using current rounding mode (vector)</para>
    </brief>
    <authored>
      <para>Floating-point Round to 64-bit Integer, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point values that fit into a 64-bit integer size using the rounding mode that is determined by the <xref linkend="AArch64.fpcr">FPCR</xref>, and writes the result to the SIMD&amp;FP destination register.</para>
      <para>A zero input returns a zero result with the same sign. When one of the result values is not numerically equal to the corresponding input value, an Inexact exception is raised. When an input is infinite, NaN or out-of-range, the instruction returns for the corresponding result value the most negative integer representable in the destination size, and an Invalid Operation floating-point exception is raised.</para>
      <para>A floating-point exception can be generated by this instruction. Depending on the settings in <xref linkend="AArch64.fpcr">FPCR</xref>, the exception results in either a flag being set in <xref linkend="AArch64.fpsr">FPSR</xref>, or a synchronous exception being generated. For more information, see <xref linkend="BEIJDDAG">Floating-point exception traps</xref>.</para>
      <para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="Vector single-precision and double-precision" oneof="1" id="iclass_simd_single_and_double" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="advsimd-datatype" value="simd-single-and-double" />
        <docvar key="advsimd-type" value="simd" />
        <docvar key="datatype" value="single-and-double" />
        <docvar key="instr-class" value="advsimd" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="FRINT64X" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.5" feature="FEAT_FRINTTS" />
      </arch_variants>
      <regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/unary/float/round/frint_32_64" tworows="1">
        <box hibit="31" settings="1">
          <c>0</c>
        </box>
        <box hibit="30" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="29" name="U" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="28" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="5" settings="5">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="16" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="12" name="op" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="FRINT64X_asimdmisc_R" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="advsimd-datatype" value="simd-single-and-double" />
          <docvar key="advsimd-type" value="simd" />
          <docvar key="datatype" value="single-and-double" />
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FRINT64X" />
        </docvars>
        <asmtemplate><text>FRINT64X  </text><a link="sa_vd" hover="SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Vd&gt;</a><text>.</text><a link="sa_t" hover="Arrangement specifier (field &quot;sz:Q&quot;) [2D,2S,4S]">&lt;T&gt;</a><text>, </text><a link="sa_vn" hover="SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Vn&gt;</a><text>.</text><a link="sa_t" hover="Arrangement specifier (field &quot;sz:Q&quot;) [2D,2S,4S]">&lt;T&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/vector/arithmetic/unary/float/round/frint_32_64" mylink="aarch64.instrs.vector.arithmetic.unary.float.round.frint_32_64" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFrintExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveFrintExt()">HaveFrintExt</a>() then UNDEFINED;
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);

if sz:Q == '10' then UNDEFINED;
integer esize = 32 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
integer datasize = if Q == '1' then 128 else 64;
integer elements = datasize DIV esize;
integer intsize = if op == '0' then 32 else 64; 
<a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = if U == '0' then <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a> else <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR[]);</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="FRINT64X_asimdmisc_R" symboldefcount="1">
      <symbol link="sa_vd">&lt;Vd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the name of the SIMD&amp;FP destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FRINT64X_asimdmisc_R" symboldefcount="1">
      <symbol link="sa_t">&lt;T&gt;</symbol>
      <definition encodedin="sz:Q">
        <intro>Is an arrangement specifier, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="bitfield">Q</entry>
                <entry class="symbol">&lt;T&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">2S</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">4S</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">2D</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="FRINT64X_asimdmisc_R" symboldefcount="1">
      <symbol link="sa_vn">&lt;Vn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the name of the SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/vector/arithmetic/unary/float/round/frint_32_64" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
bits(datasize) operand = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, datasize];
bits(datasize) result;
bits(esize) element;

for e = 0 to elements-1
    element = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.FPRoundIntN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundIntN(bits(N) op, FPCRType fpcr, FPRounding rounding, integer intsize)">FPRoundIntN</a>(element, FPCR[], rounding, intsize);

<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, datasize] = result;</pstext>
    </ps>
  </ps_section>
</instructionsection>
