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<instructionsection id="SM3TT1B_advsimd" title="SM3TT1B -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="advsimd" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="SM3TT1B" />
  </docvars>
  <heading>SM3TT1B</heading>
  <desc>
    <brief>
      <para>SM3TT1B</para>
    </brief>
    <authored>
      <para>SM3TT1B takes three 128-bit vectors from three source SIMD&amp;FP registers and a 2-bit immediate index value, and returns a 128-bit result in the destination SIMD&amp;FP register. It performs a 32-bit majority function between the three 32-bit fields held in the upper three elements of the first source vector, and adds the resulting 32-bit value and the following three other 32-bit values:</para>
      <list type="unordered">
        <listitem><content>The bottom 32-bit element of the first source vector, Vd, that was used for the 32-bit majority function.</content></listitem>
        <listitem><content>The result of the exclusive-OR of the top 32-bit element of the second source vector, Vn, with a rotation left by 12 of the top 32-bit element of the first source vector.</content></listitem>
        <listitem><content>A 32-bit element indexed out of the third source vector, Vm.</content></listitem>
      </list>
      <para>The result of this addition is returned as the top element of the result. The other elements of the result are taken from elements of the first source vector, with the element returned in bits&lt;63:32&gt; being rotated left by 9.</para>
      <para>This instruction is implemented only when <xref linkend="v8.2.SM3">FEAT_SM3</xref> is implemented.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If PSTATE.DIT is 1:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="Advanced SIMD" oneof="1" id="iclass_advsimd" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="advsimd" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="SM3TT1B" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_SM3" />
      </arch_variants>
      <regdiagram form="32" psname="aarch64/instrs/vector/crypto/sm3/sm3tt1b">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" width="5" name="Rm" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="11" width="2" name="opcode" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="SM3TT1B_VVV4_crypto3_imm2" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="SM3TT1B" />
        </docvars>
        <asmtemplate><text>SM3TT1B  </text><a link="sa_vd" hover="SIMD&amp;FP source and destination register (field &quot;Rd&quot;)">&lt;Vd&gt;</a><text>.4S, </text><a link="sa_vn" hover="Second SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Vn&gt;</a><text>.4S, </text><a link="sa_vm" hover="Third SIMD&amp;FP source register (field &quot;Rm&quot;)">&lt;Vm&gt;</a><text>.S[</text><a link="sa_imm2" hover="32-bit element indexed out of &lt;Vm&gt; (field &quot;imm2&quot;)">&lt;imm2&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/vector/crypto/sm3/sm3tt1b" mylink="aarch64.instrs.vector.crypto.sm3.sm3tt1b" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveSM3Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSM3Ext()">HaveSM3Ext</a>() then UNDEFINED;
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
integer i = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm2);</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SM3TT1B_VVV4_crypto3_imm2" symboldefcount="1">
      <symbol link="sa_vd">&lt;Vd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the name of the SIMD&amp;FP source and destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SM3TT1B_VVV4_crypto3_imm2" symboldefcount="1">
      <symbol link="sa_vn">&lt;Vn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the name of the second SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SM3TT1B_VVV4_crypto3_imm2" symboldefcount="1">
      <symbol link="sa_vm">&lt;Vm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the name of the third SIMD&amp;FP source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SM3TT1B_VVV4_crypto3_imm2" symboldefcount="1">
      <symbol link="sa_imm2">&lt;imm2&gt;</symbol>
      <account encodedin="imm2">
        <intro>
          <para>Is a 32-bit element indexed out of &lt;Vm&gt;, encoded in "imm2".</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/vector/crypto/sm3/sm3tt1b" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="AArch64.CheckFPAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</a>();

bits(128) Vm = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[m, 128];
bits(128) Vn = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, 128];
bits(128) Vd = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[d, 128];
bits(32) WjPrime;
bits(128) result; 
bits(32) TT1;
bits(32) SS2;

WjPrime = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[Vm,i,32];
SS2 = Vn&lt;127:96&gt; EOR <a link="impl-shared.ROL.2" file="shared_pseudocode.xml" hover="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(Vd&lt;127:96&gt;,12); 
TT1 = (Vd&lt;127:96&gt; AND Vd&lt;63:32&gt;) OR (Vd&lt;127:96&gt; AND Vd&lt;95:64&gt;) OR (Vd&lt;63:32&gt; AND Vd&lt;95:64&gt;); 
TT1 = (TT1 + Vd&lt;31:0&gt; + SS2 + WjPrime)&lt;31:0&gt;;
result&lt;31:0&gt; = Vd&lt;63:32&gt;;
result&lt;63:32&gt; = <a link="impl-shared.ROL.2" file="shared_pseudocode.xml" hover="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(Vd&lt;95:64&gt;,9); 
result&lt;95:64&gt; = Vd&lt;127:96&gt;; 
result&lt;127:96&gt; = TT1; 
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = result;</pstext>
    </ps>
  </ps_section>
</instructionsection>
