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<instructionsection id="EON" title="EON (shifted register) -- A64" type="instruction">
  <docvars>
    <docvar key="cond-setting" value="no-s" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="EON" />
    <docvar key="reguse" value="shifted-reg" />
  </docvars>
  <heading>EON (shifted register)</heading>
  <desc>
    <brief>
      <para>Bitwise Exclusive-OR NOT (shifted register)</para>
    </brief>
    <authored>
      <para>Bitwise Exclusive-OR NOT (shifted register) performs a bitwise exclusive-OR NOT of a register value and an optionally-shifted register value, and writes the result to the destination register.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If PSTATE.DIT is 1:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="Not setting the condition flags" oneof="1" id="iclass_no_s" no_encodings="2" isa="A64">
      <docvars>
        <docvar key="cond-setting" value="no-s" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="EON" />
        <docvar key="reguse" value="shifted-reg" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch64/instrs/integer/logical/shiftedreg" tworows="1">
        <box hibit="31" name="sf" usename="1">
          <c></c>
        </box>
        <box hibit="30" width="2" name="opc" usename="1" settings="2" psbits="xx">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="28" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="2" name="shift" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="21" name="N" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="20" width="5" name="Rm" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="EON_32_log_shift" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0">
        <docvars>
          <docvar key="cond-setting" value="no-s" />
          <docvar key="datatype" value="32" />
          <docvar key="datatype-reguse" value="32-shifted-reg" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="EON" />
          <docvar key="reguse" value="shifted-reg" />
        </docvars>
        <box hibit="31" width="1" name="sf">
          <c>0</c>
        </box>
        <asmtemplate><text>EON  </text><a link="sa_wd" hover="32-bit general-purpose destination register (field &quot;Rd&quot;)">&lt;Wd&gt;</a><text>, </text><a link="sa_wn" hover="First 32-bit general-purpose source register (field &quot;Rn&quot;)">&lt;Wn&gt;</a><text>, </text><a link="sa_wm" hover="Second 32-bit general-purpose source register (field &quot;Rm&quot;)">&lt;Wm&gt;</a><text>{</text><text>, </text><a link="sa_shift" hover="Optional shift applied to final source, default LSL (field &quot;shift&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [0-31], default 0 (field &quot;imm6&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="EON_64_log_shift" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
        <docvars>
          <docvar key="cond-setting" value="no-s" />
          <docvar key="datatype" value="64" />
          <docvar key="datatype-reguse" value="64-shifted-reg" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="EON" />
          <docvar key="reguse" value="shifted-reg" />
        </docvars>
        <box hibit="31" width="1" name="sf">
          <c>1</c>
        </box>
        <asmtemplate><text>EON  </text><a link="sa_xd" hover="64-bit general-purpose destination register (field &quot;Rd&quot;)">&lt;Xd&gt;</a><text>, </text><a link="sa_xn" hover="First 64-bit general-purpose source register (field &quot;Rn&quot;)">&lt;Xn&gt;</a><text>, </text><a link="sa_xm" hover="Second 64-bit general-purpose source register (field &quot;Rm&quot;)">&lt;Xm&gt;</a><text>{</text><text>, </text><a link="sa_shift" hover="Optional shift applied to final source, default LSL (field &quot;shift&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [0-63], default 0 (field &quot;imm6&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/integer/logical/shiftedreg" mylink="aarch64.instrs.integer.logical.shiftedreg" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
integer datasize = if sf == '1' then 64 else 32;
boolean setflags;
<a link="LogicalOp" file="shared_pseudocode.xml" hover="enumeration LogicalOp   {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp</a> op;
case opc of
    when '00' op = <a link="LogicalOp_AND" file="shared_pseudocode.xml" hover="enumeration LogicalOp   {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_AND</a>; setflags = FALSE;
    when '01' op = <a link="LogicalOp_ORR" file="shared_pseudocode.xml" hover="enumeration LogicalOp   {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_ORR</a>; setflags = FALSE;
    when '10' op = <a link="LogicalOp_EOR" file="shared_pseudocode.xml" hover="enumeration LogicalOp   {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_EOR</a>; setflags = FALSE;
    when '11' op = <a link="LogicalOp_AND" file="shared_pseudocode.xml" hover="enumeration LogicalOp   {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_AND</a>; setflags = TRUE;

if sf == '0' &amp;&amp; imm6&lt;5&gt; == '1' then UNDEFINED;

<a link="ShiftType" file="shared_pseudocode.xml" hover="enumeration ShiftType   {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR}">ShiftType</a> shift_type = <a link="impl-aarch64.DecodeShift.1" file="shared_pseudocode.xml" hover="function: ShiftType DecodeShift(bits(2) op)">DecodeShift</a>(shift);
integer shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);
boolean invert = (N == '1');</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="EON_32_log_shift" symboldefcount="1">
      <symbol link="sa_wd">&lt;Wd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EON_32_log_shift" symboldefcount="1">
      <symbol link="sa_wn">&lt;Wn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EON_32_log_shift" symboldefcount="1">
      <symbol link="sa_wm">&lt;Wm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EON_64_log_shift" symboldefcount="1">
      <symbol link="sa_xd">&lt;Xd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EON_64_log_shift" symboldefcount="1">
      <symbol link="sa_xn">&lt;Xn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EON_64_log_shift" symboldefcount="1">
      <symbol link="sa_xm">&lt;Xm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 64-bit name of the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EON_32_log_shift, EON_64_log_shift" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="shift">
        <intro>Is the optional shift to be applied to the final source, defaulting to LSL and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">shift</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="EON_32_log_shift" symboldefcount="1">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm6">
        <docvars>
          <docvar key="datatype" value="32" />
          <docvar key="datatype-reguse" value="32-shifted-reg" />
        </docvars>
        <intro>
          <para>For the 32-bit variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EON_64_log_shift" symboldefcount="2">
      <symbol link="sa_amount_1">&lt;amount&gt;</symbol>
      <account encodedin="imm6">
        <docvars>
          <docvar key="datatype" value="64" />
          <docvar key="datatype-reguse" value="64-shifted-reg" />
        </docvars>
        <intro>
          <para>For the 64-bit variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field,</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/integer/logical/shiftedreg" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(datasize) operand1 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, datasize];
bits(datasize) operand2 = <a link="impl-aarch64.ShiftReg.4" file="shared_pseudocode.xml" hover="function: bits(N) ShiftReg(integer reg, ShiftType shiftype, integer amount, integer N)">ShiftReg</a>(m, shift_type, shift_amount, datasize);
bits(datasize) result;

if invert then operand2 = NOT(operand2);

case op of
    when <a link="LogicalOp_AND" file="shared_pseudocode.xml" hover="enumeration LogicalOp   {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_AND</a> result = operand1 AND operand2;
    when <a link="LogicalOp_ORR" file="shared_pseudocode.xml" hover="enumeration LogicalOp   {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_ORR</a> result = operand1 OR  operand2;
    when <a link="LogicalOp_EOR" file="shared_pseudocode.xml" hover="enumeration LogicalOp   {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_EOR</a> result = operand1 EOR operand2;

if setflags then
    PSTATE.&lt;N,Z,C,V&gt; = result&lt;datasize-1&gt;:<a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result):'00';

<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, datasize] = result;</pstext>
    </ps>
  </ps_section>
</instructionsection>
