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<instructionsection id="ld1h_mzx_p_bi" title="LD1H (scalar plus immediate, strided registers)" type="instruction">
  <docvars>
    <docvar key="instr-class" value="mortlach2" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="LD1H" />
  </docvars>
  <heading>LD1H (scalar plus immediate, strided registers)</heading>
  <desc>
    <brief>Contiguous load of halfwords to multiple strided vectors (immediate index)</brief>
    <description>
      <para>Contiguous load of unsigned halfwords to elements of two or four strided vector registers from the memory address generated by a 64-bit scalar base and immediate index which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address.</para>
      <para>Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.</para>
    </description>
    <status>Green</status>
    <predicated>True</predicated>
    <sm_policy>SM_1_only</sm_policy>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from 2 classes:</txt>
      <a href="#iclass_to_2reg">Two registers</a>
      <txt> and </txt>
      <a href="#iclass_to_4reg">Four registers</a>
    </classesintro>
    <iclass name="Two registers" oneof="2" id="iclass_to_2reg" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="mortlach2" />
        <docvar key="isa" value="A64" />
        <docvar key="ldstruct-regcount" value="to-2reg" />
        <docvar key="mnemonic" value="LD1H" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
      </arch_variants>
      <regdiagram form="32" psname="LD1H-MZx.P.BI-2x8" tworows="1">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" name="msz&lt;1&gt;" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="13" name="msz&lt;0&gt;" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="12" width="3" name="PNg" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" name="T" usename="1">
          <c></c>
        </box>
        <box hibit="3" name="N" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="2" width="3" name="Zt" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="ld1h_mzx_p_bi_2x8" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="instr-class" value="mortlach2" />
          <docvar key="isa" value="A64" />
          <docvar key="ldstruct-regcount" value="to-2reg" />
          <docvar key="mnemonic" value="LD1H" />
        </docvars>
        <asmtemplate><text>LD1H    </text><text>{</text><text> </text><a link="sa_zt1" hover="First scalable vector register Z0-Z7 or Z16-Z23 to be transferred (field T:'0':Zt)">&lt;Zt1&gt;</a><text>.H, </text><a link="sa_zt2" hover="Second scalable vector register Z8-Z15 or Z24-Z31 to be transferred (field T:'1':Zt)">&lt;Zt2&gt;</a><text>.H </text><text>}</text><text>, </text><a link="sa_png" hover="Governing scalable predicate register PN8-PN15 (field &quot;PNg&quot;)">&lt;PNg&gt;</a><text>/Z, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>{</text><text>, #</text><a link="sa_imm" hover="Optional signed immediate vector offset, multiple of 2 [-16-14], default 0 (field &quot;imm4&quot;)">&lt;imm&gt;</a><text>, MUL VL</text><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="LD1H-MZx.P.BI-2x8" mylink="LD1H-MZx.P.BI-2x8" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('1':PNg);
constant integer nreg = 2;
integer tstride = 8;
integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(T:'0':Zt);
constant integer esize = 16;
integer offset = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(imm4);</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="Four registers" oneof="2" id="iclass_to_4reg" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="mortlach2" />
        <docvar key="isa" value="A64" />
        <docvar key="ldstruct-regcount" value="to-4reg" />
        <docvar key="mnemonic" value="LD1H" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
      </arch_variants>
      <regdiagram form="32" psname="LD1H-MZx.P.BI-4x4" tworows="1">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>1</c>
        </box>
        <box hibit="14" name="msz&lt;1&gt;" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="13" name="msz&lt;0&gt;" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="12" width="3" name="PNg" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" name="T" usename="1">
          <c></c>
        </box>
        <box hibit="3" name="N" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="2" settings="1">
          <c>0</c>
        </box>
        <box hibit="1" width="2" name="Zt" usename="1">
          <c colspan="2"></c>
        </box>
      </regdiagram>
      <encoding name="ld1h_mzx_p_bi_4x4" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="instr-class" value="mortlach2" />
          <docvar key="isa" value="A64" />
          <docvar key="ldstruct-regcount" value="to-4reg" />
          <docvar key="mnemonic" value="LD1H" />
        </docvars>
        <asmtemplate><text>LD1H    </text><text>{</text><text> </text><a link="sa_zt1_1" hover="First scalable vector register Z0-Z3 or Z16-Z19 to be transferred (field T:'00':Zt)">&lt;Zt1&gt;</a><text>.H, </text><a link="sa_zt2_1" hover="Second scalable vector register Z4-Z7 or Z20-Z23 to be transferred (field T:'01':Zt)">&lt;Zt2&gt;</a><text>.H, </text><a link="sa_zt3" hover="Third scalable vector register Z8-Z11 or Z24-Z27 to be transferred (field T:'10':Zt)">&lt;Zt3&gt;</a><text>.H, </text><a link="sa_zt4" hover="Fourth scalable vector register Z12-Z15 or Z28-Z31 to be transferred (field T:'11':Zt)">&lt;Zt4&gt;</a><text>.H </text><text>}</text><text>, </text><a link="sa_png" hover="Governing scalable predicate register PN8-PN15 (field &quot;PNg&quot;)">&lt;PNg&gt;</a><text>/Z, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>{</text><text>, #</text><a link="sa_imm_1" hover="Optional signed immediate vector offset, multiple of 4 [-32-28], default 0 (field &quot;imm4&quot;)">&lt;imm&gt;</a><text>, MUL VL</text><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="LD1H-MZx.P.BI-4x4" mylink="LD1H-MZx.P.BI-4x4" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('1':PNg);
constant integer nreg = 4;
integer tstride = 4;
integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(T:'00':Zt);
constant integer esize = 16;
integer offset = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(imm4);</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ld1h_mzx_p_bi_2x8" symboldefcount="1">
      <symbol link="sa_zt1">&lt;Zt1&gt;</symbol>
      <account encodedin="0:T:Zt">
        <docvars>
          <docvar key="ldstruct-regcount" value="to-2reg" />
        </docvars>
        <intro>
          <para>For the two registers variant: is the name of the first scalable vector register Z0-Z7 or Z16-Z23 to be transferred, encoded as "T:'0':Zt".</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ld1h_mzx_p_bi_4x4" symboldefcount="2">
      <symbol link="sa_zt1_1">&lt;Zt1&gt;</symbol>
      <account encodedin="00:T:Zt">
        <docvars>
          <docvar key="ldstruct-regcount" value="to-4reg" />
        </docvars>
        <intro>
          <para>For the four registers variant: is the name of the first scalable vector register Z0-Z3 or Z16-Z19 to be transferred, encoded as "T:'00':Zt".</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ld1h_mzx_p_bi_2x8" symboldefcount="1">
      <symbol link="sa_zt2">&lt;Zt2&gt;</symbol>
      <account encodedin="1:T:Zt">
        <docvars>
          <docvar key="ldstruct-regcount" value="to-2reg" />
        </docvars>
        <intro>
          <para>For the two registers variant: is the name of the second scalable vector register Z8-Z15 or Z24-Z31 to be transferred, encoded as "T:'1':Zt".</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ld1h_mzx_p_bi_4x4" symboldefcount="2">
      <symbol link="sa_zt2_1">&lt;Zt2&gt;</symbol>
      <account encodedin="01:T:Zt">
        <docvars>
          <docvar key="ldstruct-regcount" value="to-4reg" />
        </docvars>
        <intro>
          <para>For the four registers variant: is the name of the second scalable vector register Z4-Z7 or Z20-Z23 to be transferred, encoded as "T:'01':Zt".</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ld1h_mzx_p_bi_4x4" symboldefcount="1">
      <symbol link="sa_zt3">&lt;Zt3&gt;</symbol>
      <account encodedin="10:T:Zt">
        <intro>
          <para>Is the name of the third scalable vector register Z8-Z11 or Z24-Z27 to be transferred, encoded as "T:'10':Zt".</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ld1h_mzx_p_bi_4x4" symboldefcount="1">
      <symbol link="sa_zt4">&lt;Zt4&gt;</symbol>
      <account encodedin="11:T:Zt">
        <intro>
          <para>Is the name of the fourth scalable vector register Z12-Z15 or Z28-Z31 to be transferred, encoded as "T:'11':Zt".</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ld1h_mzx_p_bi_2x8, ld1h_mzx_p_bi_4x4" symboldefcount="1">
      <symbol link="sa_png">&lt;PNg&gt;</symbol>
      <account encodedin="PNg">
        <intro>
          <para>Is the name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ld1h_mzx_p_bi_2x8, ld1h_mzx_p_bi_4x4" symboldefcount="1">
      <symbol link="sa_xn_sp">&lt;Xn|SP&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ld1h_mzx_p_bi_2x8" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm4">
        <docvars>
          <docvar key="ldstruct-regcount" value="to-2reg" />
        </docvars>
        <intro>
          <para>For the two registers variant: is the optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ld1h_mzx_p_bi_4x4" symboldefcount="2">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm4">
        <docvars>
          <docvar key="ldstruct-regcount" value="to-4reg" />
        </docvars>
        <intro>
          <para>For the four registers variant: is the optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="LD1H-MZx.P.BI-2x8" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEEnabled()">CheckStreamingSVEEnabled</a>();
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
constant integer mbytes = esize DIV 8;
bits(64) base;
bits(PL) pred = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
bits(PL * nreg) mask = <a link="impl-aarch64.CounterToPredicate.2" file="shared_pseudocode.xml" hover="function: bits(width) CounterToPredicate(bits(16) pred, integer width)">CounterToPredicate</a>(pred&lt;15:0&gt;, PL * nreg);
array [0..3] of bits(VL) values;
boolean contiguous = TRUE;
boolean nontemporal = FALSE;
boolean tagchecked = n != 31;
<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescSVE.4" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescSVE(MemOp memop, boolean nontemporal, boolean contiguous, boolean tagchecked)">CreateAccDescSVE</a>(<a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>, nontemporal, contiguous, tagchecked);

if !<a link="impl-aarch64.AnyActiveElement.2" file="shared_pseudocode.xml" hover="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then
    if n == 31 &amp;&amp; <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_CHECKSPNONEACTIVE" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_CHECKSPNONEACTIVE</a>) then
        <a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
else
    if n == 31 then <a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
    base = if n == 31 then <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[] else <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];

for r = 0 to nreg-1
    for e = 0 to elements-1
        if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, r * elements + e, esize) then
            bits(64) addr = base + (offset * nreg * elements + r * elements + e) * mbytes;
            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[values[r], e, esize] = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[addr, mbytes, accdesc];
        else
            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[values[r], e, esize] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(esize);

for r = 0 to nreg-1
    <a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[t, VL] = values[r];
    t = t + tstride;</pstext>
    </ps>
  </ps_section>
</instructionsection>
