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<instructionsection id="SMOV_advsimd" title="SMOV -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="advsimd" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="SMOV" />
    <docvar key="vector-xfer-type" value="general-from-element" />
  </docvars>
  <heading>SMOV</heading>
  <desc>
    <brief>
      <para>Signed Move vector element to general-purpose register</para>
    </brief>
    <authored>
      <para>Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&amp;FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.</para>
      <para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If PSTATE.DIT is 1:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="Advanced SIMD" oneof="1" id="iclass_advsimd" no_encodings="2" isa="A64">
      <docvars>
        <docvar key="instr-class" value="advsimd" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="SMOV" />
        <docvar key="vector-xfer-type" value="general-from-element" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch64/instrs/vector/transfer/integer/move/signed">
        <box hibit="31" settings="1">
          <c>0</c>
        </box>
        <box hibit="30" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="29" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="28" width="8" settings="8">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="2" name="imm4[3:2]" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="12" name="imm4[1]" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" name="imm4[0]" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="SMOV_asimdins_W_w" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="Q == 0">
        <docvars>
          <docvar key="datatype" value="32" />
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="SMOV" />
          <docvar key="vector-xfer-type" value="general-from-element" />
        </docvars>
        <box hibit="30" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>SMOV  </text><a link="sa_wd" hover="32-bit general-purpose destination register (field &quot;Rd&quot;)">&lt;Wd&gt;</a><text>, </text><a link="sa_vn" hover="SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Vn&gt;</a><text>.</text><a link="sa_ts" hover="Element size specifier (field &quot;imm5&quot;) [B,H]">&lt;Ts&gt;</a><text>[</text><a link="sa_index" hover="Element index (field &quot;imm5&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="SMOV_asimdins_X_x" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="Q == 1">
        <docvars>
          <docvar key="atomic-ops" value="SMOV-64-reg" />
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="SMOV" />
          <docvar key="reg-type" value="64-reg" />
          <docvar key="vector-xfer-type" value="general-from-element" />
        </docvars>
        <box hibit="30" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>SMOV  </text><a link="sa_xd" hover="64-bit general-purpose destination register (field &quot;Rd&quot;)">&lt;Xd&gt;</a><text>, </text><a link="sa_vn" hover="SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Vn&gt;</a><text>.</text><a link="sa_ts_1" hover="Element size specifier (field &quot;imm5&quot;) [B,H,S]">&lt;Ts&gt;</a><text>[</text><a link="sa_index_1" hover="Element index (field &quot;imm5&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/vector/transfer/integer/move/signed" mylink="aarch64.instrs.vector.transfer.integer.move.signed" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);

integer size;
case Q:imm5 of
    when 'xxxxx1' size = 0;    // SMOV [WX]d, Vn.B
    when 'xxxx10' size = 1;    // SMOV [WX]d, Vn.H
    when '1xx100' size = 2;    // SMOV Xd, Vn.S
    otherwise     UNDEFINED;

integer idxdsize = if imm5&lt;4&gt; == '1' then 128 else 64;
integer index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm5&lt;4:size+1&gt;);
integer esize = 8 &lt;&lt; size;
integer datasize = if Q == '1' then 64 else 32;</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SMOV_asimdins_W_w" symboldefcount="1">
      <symbol link="sa_wd">&lt;Wd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMOV_asimdins_X_x" symboldefcount="1">
      <symbol link="sa_xd">&lt;Xd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMOV_asimdins_W_w, SMOV_asimdins_X_x" symboldefcount="1">
      <symbol link="sa_vn">&lt;Vn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the name of the SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMOV_asimdins_W_w" symboldefcount="1">
      <symbol link="sa_ts">&lt;Ts&gt;</symbol>
      <definition encodedin="imm5">
        <intro>For the 32-bit variant: is an element size specifier, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">imm5</entry>
                <entry class="symbol">&lt;Ts&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">xxx00</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">xxxx1</entry>
                <entry class="symbol">B</entry>
              </row>
              <row>
                <entry class="bitfield">xxx10</entry>
                <entry class="symbol">H</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="SMOV_asimdins_X_x" symboldefcount="2">
      <symbol link="sa_ts_1">&lt;Ts&gt;</symbol>
      <definition encodedin="imm5">
        <intro>For the 64-bit variant: is an element size specifier, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">imm5</entry>
                <entry class="symbol">&lt;Ts&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">xx000</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">xxxx1</entry>
                <entry class="symbol">B</entry>
              </row>
              <row>
                <entry class="bitfield">xxx10</entry>
                <entry class="symbol">H</entry>
              </row>
              <row>
                <entry class="bitfield">xx100</entry>
                <entry class="symbol">S</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="SMOV_asimdins_W_w" symboldefcount="1">
      <symbol link="sa_index">&lt;index&gt;</symbol>
      <definition encodedin="imm5">
        <intro>For the 32-bit variant: is the element index </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">imm5</entry>
                <entry class="symbol">&lt;index&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">xxx00</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">xxxx1</entry>
                <entry class="symbol">imm5&lt;4:1&gt;</entry>
              </row>
              <row>
                <entry class="bitfield">xxx10</entry>
                <entry class="symbol">imm5&lt;4:2&gt;</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="SMOV_asimdins_X_x" symboldefcount="2">
      <symbol link="sa_index_1">&lt;index&gt;</symbol>
      <definition encodedin="imm5">
        <intro>For the 64-bit variant: is the element index </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">imm5</entry>
                <entry class="symbol">&lt;index&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">xx000</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">xxxx1</entry>
                <entry class="symbol">imm5&lt;4:1&gt;</entry>
              </row>
              <row>
                <entry class="bitfield">xxx10</entry>
                <entry class="symbol">imm5&lt;4:2&gt;</entry>
              </row>
              <row>
                <entry class="bitfield">xx100</entry>
                <entry class="symbol">imm5&lt;4:3&gt;</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/vector/transfer/integer/move/signed" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if index == 0 then
    <a link="impl-aarch64.CheckFPEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPEnabled64()">CheckFPEnabled64</a>();
else
    <a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
bits(idxdsize) operand = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, idxdsize];

<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, datasize] = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, index, esize], datasize);</pstext>
    </ps>
  </ps_section>
</instructionsection>
