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<instructionsection id="LD64B" title="LD64B -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="LD64B" />
  </docvars>
  <heading>LD64B</heading>
  <desc>
    <brief>
      <para>Single-copy Atomic 64-byte Load</para>
    </brief>
    <authored>
      <para>Single-copy Atomic 64-byte Load derives an address from a base register value, loads eight 64-bit doublewords from a memory location, and writes them to consecutive registers, <syntax>Xt</syntax> to <syntax>X(t+7)</syntax>. The data that is loaded is atomic and is required to be 64-byte aligned.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="Integer" oneof="1" id="iclass_general" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="LD64B" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.7" feature="FEAT_LS64" />
      </arch_variants>
      <regdiagram form="32" psname="aarch64/instrs/memory/atomicops/ld_acc">
        <box hibit="31" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="29" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="26" name="V" settings="1">
          <c>0</c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" name="A" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="R" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="5" name="Rs" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" name="o3" settings="1">
          <c>1</c>
        </box>
        <box hibit="14" width="3" name="opc" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rt" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="LD64B_64L_memop" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="LD64B" />
        </docvars>
        <asmtemplate><text>LD64B  </text><a link="sa_xt" hover="First 64-bit general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Xt&gt;</a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text> {,#0}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/memory/atomicops/ld_acc" mylink="aarch64.instrs.memory.atomicops.ld_acc" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFeatLS64.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatLS64()">HaveFeatLS64</a>() then UNDEFINED;
if Rt&lt;4:3&gt; == '11' || Rt&lt;0&gt; == '1' then UNDEFINED;

integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);
<a link="MemOp" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop = <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>;
boolean tagchecked = n != 31;</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LD64B_64L_memop" symboldefcount="1">
      <symbol link="sa_xt">&lt;Xt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LD64B_64L_memop" symboldefcount="1">
      <symbol link="sa_xn_sp">&lt;Xn|SP&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/memory/atomicops/ld_acc" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckLDST64BEnabled.0" file="shared_pseudocode.xml" hover="function: CheckLDST64BEnabled()">CheckLDST64BEnabled</a>();

bits(512) data;
bits(64) address;
bits(64) value;

<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescLS64.2" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescLS64(MemOp memop, boolean tagchecked)">CreateAccDescLS64</a>(memop, tagchecked);
if n == 31 then
    <a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
    address = <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[];
else
    address = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];

data = <a link="impl-aarch64.MemLoad64B.2" file="shared_pseudocode.xml" hover="function: bits(512) MemLoad64B(bits(64) address, AccessDescriptor accdesc_in)">MemLoad64B</a>(address, accdesc);

for i = 0 to 7
    value = data&lt;63+64*i : 64*i&gt;;
    if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(accdesc.acctype) then value = <a link="impl-shared.BigEndianReverse.1" file="shared_pseudocode.xml" hover="function: bits(width) BigEndianReverse (bits(width) value)">BigEndianReverse</a>(value);
    <a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[t+i, 64] = value;</pstext>
    </ps>
  </ps_section>
</instructionsection>
