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<instructionsection id="fcvtl_mz2_z" title="FCVTL" type="instruction">
  <docvars>
    <docvar key="instr-class" value="mortlach2" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="FCVTL" />
  </docvars>
  <heading>FCVTL</heading>
  <desc>
    <brief>Multi-vector floating-point convert from half-precision to deinterleaved single-precision</brief>
    <description>
      <para>Convert to single-precision from half-precision, each element of the source vector, and place the deinterleaved results in the double-width destination elements of the destination vectors.</para>
      <para>This instruction follows SME2 floating-point numerical behaviors corresponding to instructions that place their results in one or more SVE Z vectors.</para>
      <para>This instruction is unpredicated.</para>
      <para>ID_AA64SMFR0_EL1.F16F16 indicates whether this instruction is implemented.</para>
    </description>
    <status>Amber</status>
    <predicated>False</predicated>
    <sm_policy>SM_1_only</sm_policy>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="SME2" oneof="1" id="iclass_mortlach2" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="mortlach2" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="FCVTL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="FEAT_SME_F16F16" feature="FEAT_SME_F16F16" />
      </arch_variants>
      <regdiagram form="32" psname="FCVTL-MZ2.Z-_" tworows="1">
        <box hibit="31" width="22" settings="22">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Zn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="4" name="Zd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="0" name="L" usename="1" settings="1">
          <c>1</c>
        </box>
      </regdiagram>
      <encoding name="fcvtl_mz2_z_" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="instr-class" value="mortlach2" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FCVTL" />
        </docvars>
        <asmtemplate><text>FCVTL   </text><text>{</text><text> </text><a link="sa_zd1" hover="First destination scalable vector register of a multi-vector sequence (field Zd)">&lt;Zd1&gt;</a><text>.S-</text><a link="sa_zd2" hover="Second destination scalable vector register of a multi-vector sequence (field Zd)">&lt;Zd2&gt;</a><text>.S </text><text>}</text><text>, </text><a link="sa_zn" hover="Source scalable vector register (field &quot;Zn&quot;)">&lt;Zn&gt;</a><text>.H</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="FCVTL-MZ2.Z-_" mylink="FCVTL-MZ2.Z-_" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSMEF16F16.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEF16F16()">HaveSMEF16F16</a>() then UNDEFINED;
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd:'0');</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="fcvtl_mz2_z_" symboldefcount="1">
      <symbol link="sa_zd1">&lt;Zd1&gt;</symbol>
      <account encodedin="Zd">
        <intro>
          <para>Is the name of the first destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="fcvtl_mz2_z_" symboldefcount="1">
      <symbol link="sa_zd2">&lt;Zd2&gt;</symbol>
      <account encodedin="Zd">
        <intro>
          <para>Is the name of the second destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 2 plus 1.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="fcvtl_mz2_z_" symboldefcount="1">
      <symbol link="sa_zn">&lt;Zn&gt;</symbol>
      <account encodedin="Zn">
        <intro>
          <para>Is the name of the source scalable vector register, encoded in the "Zn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="FCVTL-MZ2.Z-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEEnabled()">CheckStreamingSVEEnabled</a>();
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
constant integer pairs = VL DIV 32;
bits(VL) operand = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
bits(VL) result0;
bits(VL) result1;

for p = 0 to pairs-1
    bits(16) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*p+0, 16];
    bits(16) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*p+1, 16];
    bits(32) res1 = <a link="impl-aarch64.FPConvertSVE.3" file="shared_pseudocode.xml" hover="function: bits(M) FPConvertSVE(bits(N) op, FPCRType fpcr_in, integer M)">FPConvertSVE</a>(element1, FPCR[], 32);
    bits(32) res2 = <a link="impl-aarch64.FPConvertSVE.3" file="shared_pseudocode.xml" hover="function: bits(M) FPConvertSVE(bits(N) op, FPCRType fpcr_in, integer M)">FPConvertSVE</a>(element2, FPCR[], 32);
    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result0, p, 32] = res1;
    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result1, p, 32] = res2;

<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d+0, VL] = result0;
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d+1, VL] = result1;</pstext>
    </ps>
  </ps_section>
</instructionsection>
