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<instructionsection id="ST64BV0" title="ST64BV0 -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="ST64BV0" />
  </docvars>
  <heading>ST64BV0</heading>
  <desc>
    <brief>
      <para>Single-copy Atomic 64-byte EL0 Store with Return</para>
    </brief>
    <authored>
      <para>Single-copy Atomic 64-byte EL0 Store with Return stores eight 64-bit doublewords from consecutive registers, <syntax>Xt</syntax> to <syntax>X(t+7)</syntax>, to a memory location, with the bottom 32 bits taken from <xref linkend="AArch64.accdata_el1">ACCDATA_EL1</xref>, and writes the status result of the store to a register. The data that is stored is atomic and is required to be 64-byte aligned.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="Integer" oneof="1" id="iclass_general" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="ST64BV0" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.7" feature="FEAT_LS64_ACCDATA" />
      </arch_variants>
      <regdiagram form="32" psname="aarch64/instrs/memory/atomicops/st_acc/st64bv0">
        <box hibit="31" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="29" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="26" name="V" settings="1">
          <c>0</c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" name="A" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="R" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="5" name="Rs" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" name="o3" settings="1">
          <c>1</c>
        </box>
        <box hibit="14" width="3" name="opc" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rt" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="ST64BV0_64_memop" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="ST64BV0" />
        </docvars>
        <asmtemplate><text>ST64BV0  </text><a link="sa_xs" hover="64-bit general-purpose register into which the status result of this instruction is written (field &quot;Rs&quot;)">&lt;Xs&gt;</a><text>, </text><a link="sa_xt" hover="First 64-bit general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Xt&gt;</a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/memory/atomicops/st_acc/st64bv0" mylink="aarch64.instrs.memory.atomicops.st_acc.st64bv0" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFeatLS64_ACCDATA.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatLS64_ACCDATA()">HaveFeatLS64_ACCDATA</a>() then UNDEFINED;
if Rt&lt;4:3&gt; == '11' || Rt&lt;0&gt; == '1' then UNDEFINED;

integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);
<a link="MemOp" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop = <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;
integer s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);
boolean tagchecked = n != 31;</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ST64BV0_64_memop" symboldefcount="1">
      <symbol link="sa_xs">&lt;Xs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the 64-bit name of the general-purpose register into which the status result of this instruction is written, encoded in the "Rs" field.</para>
          <para>The value returned is:</para>
          <list type="param">
            <listitem>
              <param>0xFFFFFFFF_FFFFFFFF</param><content>If the memory location accessed does not support this instruction. In this case, the value at the memory location is UNKNOWN.</content>
            </listitem>
            <listitem>
              <param>!= 0xFFFFFFFF_FFFFFFFF</param><content>If the memory location accessed does support this instruction. In this case, the peripheral that provides the response defines the returned value and provides information on the state of the memory update at the memory location.</content>
            </listitem>
          </list>
          <para>If XZR is used, then the return value is ignored.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ST64BV0_64_memop" symboldefcount="1">
      <symbol link="sa_xt">&lt;Xt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ST64BV0_64_memop" symboldefcount="1">
      <symbol link="sa_xn_sp">&lt;Xn|SP&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/memory/atomicops/st_acc/st64bv0" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckST64BV0Enabled.0" file="shared_pseudocode.xml" hover="function: CheckST64BV0Enabled()">CheckST64BV0Enabled</a>();

bits(512) data;
bits(64) address;
bits(64) value;
bits(64) status;

<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescLS64.2" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescLS64(MemOp memop, boolean tagchecked)">CreateAccDescLS64</a>(memop, tagchecked);
bits(64) Xt = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[t, 64];
value&lt;31:0&gt;  = ACCDATA_EL1&lt;31:0&gt;;
value&lt;63:32&gt; = Xt&lt;63:32&gt;;
if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(accdesc.acctype) then value = <a link="impl-shared.BigEndianReverse.1" file="shared_pseudocode.xml" hover="function: bits(width) BigEndianReverse (bits(width) value)">BigEndianReverse</a>(value);
data&lt;63:0&gt; = value;
for i = 1 to 7
    value = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[t+i, 64];
    if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(accdesc.acctype) then value = <a link="impl-shared.BigEndianReverse.1" file="shared_pseudocode.xml" hover="function: bits(width) BigEndianReverse (bits(width) value)">BigEndianReverse</a>(value);
    data&lt;63+64*i : 64*i&gt; = value;

if n == 31 then
    <a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
    address = <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[];
else
    address = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];

status = <a link="impl-aarch64.MemStore64BWithRet.3" file="shared_pseudocode.xml" hover="function: bits(64) MemStore64BWithRet(bits(64) address, bits(512) value, AccessDescriptor accdesc_in)">MemStore64BWithRet</a>(address, data, accdesc);

if s != 31 then <a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[s, 64] = status;</pstext>
    </ps>
  </ps_section>
</instructionsection>
