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<instructionsection id="CPP_SYS" title="CPP -- A64" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="CPP" />
    <docvar key="instr-class" value="system" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="SYS" />
  </docvars>
  <heading>CPP</heading>
  <desc>
    <brief>
      <para>Cache Prefetch Prediction Restriction by Context</para>
    </brief>
    <authored>
      <para>Cache Prefetch Prediction Restriction by Context prevents cache allocation predictions that predict execution addresses based on information gathered from earlier execution within a particular execution context. The actions of code in the target execution context or contexts appearing in program order before the instruction cannot exploitatively control cache prefetch predictions occurring after the instruction is complete and synchronized.</para>
      <para>For more information, see <xref linkend="AArch64.cpp_rctx">CPP RCTX, Cache Prefetch Prediction Restriction by Context</xref>.</para>
    </authored>
  </desc>
  <aliasto refiform="sys.xml" iformid="SYS">SYS</aliasto>
  <classes>
    <iclass name="System" oneof="1" id="iclass_system" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="system" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="SYS" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.5" feature="FEAT_SPECRES" />
      </arch_variants>
      <regdiagram form="32" psname="aarch64/instrs/system/sysops" tworows="1">
        <box hibit="31" width="10" settings="10">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="21" name="L" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="20" width="2" name="op0" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="18" width="3" name="op1" usename="1" settings="3" psbits="xxx">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="CRn" usename="1" settings="4" psbits="xxxx">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="CRm" usename="1" settings="4" psbits="xxxx">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="3" name="op2" usename="1" settings="3" psbits="xxx">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" width="5" name="Rt" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="CPP_SYS_CR_systeminstrs" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="alias_mnemonic" value="CPP" />
          <docvar key="instr-class" value="system" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="SYS" />
        </docvars>
        <asmtemplate><text>CPP  RCTX, </text><a link="sa_xt_1" hover="64-bit general-purpose source register (field &quot;Rt&quot;)">&lt;Xt&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="sys.xml#SYS_CR_systeminstrs">SYS</a><text> #3, C7, C3, #7, </text><a link="sa_xt_1" hover="64-bit general-purpose source register (field &quot;Rt&quot;)">&lt;Xt&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="CPP_SYS_CR_systeminstrs" symboldefcount="1">
      <symbol link="sa_xt_1">&lt;Xt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the 64-bit name of the general-purpose source register, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
