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<instructionsection id="ld1rw_z_p_bi" title="LD1RW" type="instruction">
  <docvars>
    <docvar key="instr-class" value="sve" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="LD1RW" />
  </docvars>
  <heading>LD1RW</heading>
  <desc>
    <brief>Load and broadcast unsigned word to vector</brief>
    <description>
      <para>Load a single unsigned word from a memory address generated by a 64-bit scalar base address plus an immediate offset which is a multiple of 4 in the range 0 to 252.</para>
      <para>Broadcast the loaded data into all active elements of the destination vector, setting the inactive elements to zero. If all elements are inactive then the instruction will not perform a read from Device memory or cause a data abort.</para>
    </description>
    <status>Green</status>
    <predicated>True</predicated>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from 2 classes:</txt>
      <a href="#iclass_32_elem">32-bit element</a>
      <txt> and </txt>
      <a href="#iclass_64_elem">64-bit element</a>
    </classesintro>
    <iclass name="32-bit element" oneof="2" id="iclass_32_elem" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="sve" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="LD1RW" />
        <docvar key="sve-elem-type" value="32-elem" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="LD1RW-Z.P.BI-U32" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="dtypeh&lt;1&gt;" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="dtypeh&lt;0&gt;" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" settings="1">
          <c>1</c>
        </box>
        <box hibit="14" name="dtypel&lt;1&gt;" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="13" name="dtypel&lt;0&gt;" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="12" width="3" name="Pg" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Zt" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="ld1rw_z_p_bi_u32" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="instr-class" value="sve" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="LD1RW" />
          <docvar key="sve-elem-type" value="32-elem" />
        </docvars>
        <asmtemplate><text>LD1RW   </text><text>{</text><text> </text><a link="sa_zt" hover="Scalable vector register to be transferred (field &quot;Zt&quot;)">&lt;Zt&gt;</a><text>.S </text><text>}</text><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field &quot;Pg&quot;)">&lt;Pg&gt;</a><text>/Z, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>{</text><text>, #</text><a link="sa_imm" hover="Optional unsigned immediate byte offset, multiple of 4 [0-252], default 0 (field &quot;imm6&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="LD1RW-Z.P.BI-U32" mylink="LD1RW-Z.P.BI-U32" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() &amp;&amp; !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zt);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
constant integer esize = 32;
constant integer msize = 32;
boolean unsigned = TRUE;
integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="64-bit element" oneof="2" id="iclass_64_elem" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="sve" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="LD1RW" />
        <docvar key="sve-elem-type" value="64-elem" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="LD1RW-Z.P.BI-U64" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="dtypeh&lt;1&gt;" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="dtypeh&lt;0&gt;" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" settings="1">
          <c>1</c>
        </box>
        <box hibit="14" name="dtypel&lt;1&gt;" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="13" name="dtypel&lt;0&gt;" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="12" width="3" name="Pg" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Zt" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="ld1rw_z_p_bi_u64" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="instr-class" value="sve" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="LD1RW" />
          <docvar key="sve-elem-type" value="64-elem" />
        </docvars>
        <asmtemplate><text>LD1RW   </text><text>{</text><text> </text><a link="sa_zt" hover="Scalable vector register to be transferred (field &quot;Zt&quot;)">&lt;Zt&gt;</a><text>.D </text><text>}</text><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field &quot;Pg&quot;)">&lt;Pg&gt;</a><text>/Z, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>{</text><text>, #</text><a link="sa_imm" hover="Optional unsigned immediate byte offset, multiple of 4 [0-252], default 0 (field &quot;imm6&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="LD1RW-Z.P.BI-U64" mylink="LD1RW-Z.P.BI-U64" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() &amp;&amp; !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zt);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
constant integer esize = 64;
constant integer msize = 32;
boolean unsigned = TRUE;
integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ld1rw_z_p_bi_u32, ld1rw_z_p_bi_u64" symboldefcount="1">
      <symbol link="sa_zt">&lt;Zt&gt;</symbol>
      <account encodedin="Zt">
        <intro>
          <para>Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ld1rw_z_p_bi_u32, ld1rw_z_p_bi_u64" symboldefcount="1">
      <symbol link="sa_pg">&lt;Pg&gt;</symbol>
      <account encodedin="Pg">
        <intro>
          <para>Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ld1rw_z_p_bi_u32, ld1rw_z_p_bi_u64" symboldefcount="1">
      <symbol link="sa_xn_sp">&lt;Xn|SP&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ld1rw_z_p_bi_u32, ld1rw_z_p_bi_u64" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm6">
        <intro>
          <para>Is the optional unsigned immediate byte offset, a multiple of 4 in the range 0 to 252, defaulting to 0, encoded in the "imm6" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="LD1RW-Z.P.BI-U32" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(64) base;
bits(PL) mask = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
bits(VL) result;
bits(msize) data;
constant integer mbytes = msize DIV 8;
boolean contiguous = TRUE;
boolean nontemporal = FALSE;
boolean tagchecked = n != 31;
<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescSVE.4" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescSVE(MemOp memop, boolean nontemporal, boolean contiguous, boolean tagchecked)">CreateAccDescSVE</a>(<a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>, nontemporal, contiguous, tagchecked);

if !<a link="impl-aarch64.AnyActiveElement.2" file="shared_pseudocode.xml" hover="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then
    if n == 31 &amp;&amp; <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_CHECKSPNONEACTIVE" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_CHECKSPNONEACTIVE</a>) then
        <a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
else
    if n == 31 then <a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
    base = if n == 31 then <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[] else <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
    bits(64) addr = base + offset * mbytes;
    data = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[addr, mbytes, accdesc];

for e = 0 to elements-1
    if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.Extend.3" file="shared_pseudocode.xml" hover="function: bits(N) Extend(bits(M) x, integer N, boolean unsigned)">Extend</a>(data, esize, unsigned);
    else
        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(esize);

<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[t, VL] = result;</pstext>
    </ps>
  </ps_section>
</instructionsection>
