<?xml version="1.0" encoding="utf-8"?>
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="str_p_bi" title="STR (predicate)" type="instruction">
  <docvars>
    <docvar key="instr-class" value="sve" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="STR" />
  </docvars>
  <heading>STR (predicate)</heading>
  <desc>
    <brief>Store predicate register</brief>
    <description>
      <para>Store a predicate register to a memory address generated by a 64-bit scalar base, plus an immediate offset in the range -256 to 255 which is multiplied by the current predicate register size in bytes. This instruction is unpredicated.</para>
      <para>The store is performed as contiguous byte accesses, each containing 8 consecutive predicate bits in ascending element order, with no endian conversion and no guarantee of single-copy atomicity larger than a byte. However, if alignment is checked, then a general-purpose base register must be aligned to 2 bytes.</para>
    </description>
    <status>Green</status>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="sve" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="STR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="STR-P.BI-_">
        <box hibit="31" width="10" settings="10">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="21" width="6" name="imm9h" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="12" width="3" name="imm9l" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Pt" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="str_p_bi_" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="instr-class" value="sve" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="STR" />
        </docvars>
        <asmtemplate><text>STR     </text><a link="sa_pt" hover="Scalable predicate transfer register (field &quot;Pt&quot;)">&lt;Pt&gt;</a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>{</text><text>, #</text><a link="sa_imm" hover="Optional signed immediate vector offset [-256-255], default 0 (field &quot;imm9h:imm9l&quot;)">&lt;imm&gt;</a><text>, MUL VL</text><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="STR-P.BI-_" mylink="STR-P.BI-_" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() &amp;&amp; !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pt);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer imm = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(imm9h:imm9l);</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="str_p_bi_" symboldefcount="1">
      <symbol link="sa_pt">&lt;Pt&gt;</symbol>
      <account encodedin="Pt">
        <intro>
          <para>Is the name of the scalable predicate transfer register, encoded in the "Pt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="str_p_bi_" symboldefcount="1">
      <symbol link="sa_xn_sp">&lt;Xn|SP&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="str_p_bi_" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm9h:imm9l">
        <intro>
          <para>Is the optional signed immediate vector offset, in the range -256 to 255, defaulting to 0, encoded in the "imm9h:imm9l" fields.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="STR-P.BI-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
constant integer PL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a> DIV 8;
constant integer elements = PL DIV 8;
bits(PL) src;
bits(64) base;
integer offset = imm * elements;
boolean contiguous = TRUE;
boolean nontemporal = FALSE;
boolean tagchecked = n != 31;
<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescSVE.4" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescSVE(MemOp memop, boolean nontemporal, boolean contiguous, boolean tagchecked)">CreateAccDescSVE</a>(<a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>, nontemporal, contiguous, tagchecked);

if n == 31 then
    <a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
    base = <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[];
else
    base = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];

src = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[t, PL];

boolean aligned = <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(base + offset, 2);

if !aligned &amp;&amp; <a link="impl-shared.AlignmentEnforced.0" file="shared_pseudocode.xml" hover="function: boolean AlignmentEnforced()">AlignmentEnforced</a>() then
    <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(base + offset, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));

for e = 0 to elements-1
    <a link="AArch64.MemSingle.write.4" file="shared_pseudocode.xml" hover="accessor: AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc, boolean aligned] = bits(size*8) value">AArch64.MemSingle</a>[base + offset, 1, accdesc, aligned] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[src, e, 8];
    offset = offset + 1;</pstext>
    </ps>
  </ps_section>
</instructionsection>
