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<instructionsection id="LDNP_gen" title="LDNP -- A64" type="instruction">
  <docvars>
    <docvar key="address-form" value="signed-scaled-offset" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="LDNP" />
    <docvar key="offset-type" value="off7s_s" />
  </docvars>
  <heading>LDNP</heading>
  <desc>
    <brief>
      <para>Load Pair of Registers, with non-temporal hint</para>
    </brief>
    <authored>
      <para>Load Pair of Registers, with non-temporal hint, calculates an address from a base register value and an immediate offset, loads two 32-bit words or two 64-bit doublewords from memory, and writes them to two registers.</para>
      <para>For information about memory accesses, see <xref linkend="CHDIIIBB">Load/Store addressing modes</xref>. For information about Non-temporal pair instructions, see <xref linkend="CEGJCGDF">Load/Store Non-temporal pair</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CJAGHAGE">LDNP</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="Signed offset" oneof="1" id="iclass_signed_scaled_offset" no_encodings="2" isa="A64">
      <docvars>
        <docvar key="address-form" value="signed-scaled-offset" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="LDNP" />
        <docvar key="offset-type" value="off7s_s" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch64/instrs/memory/pair/general/no-alloc" tworows="1">
        <box hibit="31" width="2" name="opc" usename="1" settings="1" psbits="xx">
          <c>x</c>
          <c>0</c>
        </box>
        <box hibit="29" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="26" name="V" settings="1">
          <c>0</c>
        </box>
        <box hibit="25" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="L" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="21" width="7" name="imm7" usename="1">
          <c colspan="7"></c>
        </box>
        <box hibit="14" width="5" name="Rt2" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rt" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="LDNP_32_ldstnapair_offs" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="opc == 00">
        <docvars>
          <docvar key="address-form" value="signed-scaled-offset" />
          <docvar key="address-form-reg-type" value="signed-scaled-offset-pair-32" />
          <docvar key="atomic-ops" value="LDNP-pair-32" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="LDNP" />
          <docvar key="offset-type" value="off7s_s" />
          <docvar key="reg-type" value="pair-32" />
        </docvars>
        <box hibit="31" width="2" name="opc">
          <c>0</c>
          <c></c>
        </box>
        <asmtemplate><text>LDNP  </text><a link="sa_wt1" hover="First 32-bit general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Wt1&gt;</a><text>, </text><a link="sa_wt2" hover="Second 32-bit general-purpose register to be transferred (field &quot;Rt2&quot;)">&lt;Wt2&gt;</a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>{</text><text>, #</text><a link="sa_imm" hover="Optional signed immediate byte offset, multiple of 4 [-256-252], default 0 (field &quot;imm7&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="LDNP_64_ldstnapair_offs" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="opc == 10">
        <docvars>
          <docvar key="address-form" value="signed-scaled-offset" />
          <docvar key="address-form-reg-type" value="signed-scaled-offset-pair-64" />
          <docvar key="atomic-ops" value="LDNP-pair-64" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="LDNP" />
          <docvar key="offset-type" value="off7s_s" />
          <docvar key="reg-type" value="pair-64" />
        </docvars>
        <box hibit="31" width="2" name="opc">
          <c>1</c>
          <c></c>
        </box>
        <asmtemplate><text>LDNP  </text><a link="sa_xt1" hover="First 64-bit general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Xt1&gt;</a><text>, </text><a link="sa_xt2" hover="Second 64-bit general-purpose register to be transferred (field &quot;Rt2&quot;)">&lt;Xt2&gt;</a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>{</text><text>, #</text><a link="sa_imm_1" hover="Optional signed immediate byte offset, multiple of 8 [-512-504], default 0 (field &quot;imm7&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/memory/pair/general/no-alloc" mylink="aarch64.instrs.memory.pair.general.no-alloc" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">boolean wback  = FALSE;
boolean postindex = FALSE;</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDNP_32_ldstnapair_offs" symboldefcount="1">
      <symbol link="sa_wt1">&lt;Wt1&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the 32-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDNP_32_ldstnapair_offs" symboldefcount="1">
      <symbol link="sa_wt2">&lt;Wt2&gt;</symbol>
      <account encodedin="Rt2">
        <intro>
          <para>Is the 32-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDNP_64_ldstnapair_offs" symboldefcount="1">
      <symbol link="sa_xt1">&lt;Xt1&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDNP_64_ldstnapair_offs" symboldefcount="1">
      <symbol link="sa_xt2">&lt;Xt2&gt;</symbol>
      <account encodedin="Rt2">
        <intro>
          <para>Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDNP_32_ldstnapair_offs, LDNP_64_ldstnapair_offs" symboldefcount="1">
      <symbol link="sa_xn_sp">&lt;Xn|SP&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDNP_32_ldstnapair_offs" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm7">
        <docvars>
          <docvar key="address-form-reg-type" value="signed-scaled-offset-pair-32" />
          <docvar key="atomic-ops" value="LDNP-pair-32" />
          <docvar key="reg-type" value="pair-32" />
        </docvars>
        <intro>
          <para>For the 32-bit variant: is the optional signed immediate byte offset, a multiple of 4 in the range -256 to 252, defaulting to 0 and encoded in the "imm7" field as &lt;imm&gt;/4.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDNP_64_ldstnapair_offs" symboldefcount="2">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm7">
        <docvars>
          <docvar key="address-form-reg-type" value="signed-scaled-offset-pair-64" />
          <docvar key="atomic-ops" value="LDNP-pair-64" />
          <docvar key="reg-type" value="pair-64" />
        </docvars>
        <intro>
          <para>For the 64-bit variant: is the optional signed immediate byte offset, a multiple of 8 in the range -512 to 504, defaulting to 0 and encoded in the "imm7" field as &lt;imm&gt;/8.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/memory/pair/general/no-alloc" mylink="postdecode" enclabels="" sections="1" secttype="Shared Decode">
      <pstext mayhavelinks="1" section="Postdecode" rep_section="postdecode">integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);
integer t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt2);
boolean nontemporal = TRUE;
<a link="MemOp" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop = if L == '1' then <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> else <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;
if opc&lt;0&gt; == '1' then UNDEFINED;
integer scale = 2 + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opc&lt;1&gt;);
integer datasize = 8 &lt;&lt; scale;
bits(64) offset = <a link="impl-shared.LSL.2" file="shared_pseudocode.xml" hover="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm7, 64), scale);
boolean tagchecked = wback || n != 31;

boolean rt_unknown = FALSE;

if memop == <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> &amp;&amp; t == t2 then
    <a link="Constraint" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint</a> c = <a link="impl-shared.ConstrainUnpredictable.1" file="shared_pseudocode.xml" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</a>(<a link="Unpredictable_LDPOVERLAP" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_LDPOVERLAP</a>);
    assert c IN {<a link="Constraint_UNKNOWN" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNKNOWN</a>, <a link="Constraint_UNDEF" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNDEF</a>, <a link="Constraint_NOP" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NOP</a>};
    case c of
        when <a link="Constraint_UNKNOWN" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNKNOWN</a>    rt_unknown = TRUE;    // result is UNKNOWN
        when <a link="Constraint_UNDEF" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNDEF</a>      UNDEFINED;
        when <a link="Constraint_NOP" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NOP</a>        <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</pstext>
    </ps>
  </ps_section>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/memory/pair/general/no-alloc" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(64) address;
bits(datasize) data1;
bits(datasize) data2;
constant integer dbytes = datasize DIV 8;
boolean privileged = PSTATE.EL != <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>;

<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescGPR.4" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescGPR(MemOp memop, boolean nontemporal, boolean privileged, boolean tagchecked)">CreateAccDescGPR</a>(memop, nontemporal, privileged, tagchecked);

if n == 31 then
    <a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
    address = <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[];
else
    address = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];

if ! postindex then
    address = address + offset;

case memop of
    when <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>
        if rt_unknown &amp;&amp; t == n then
            data1 = bits(datasize) UNKNOWN;
        else
            data1 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[t, datasize];
        if rt_unknown &amp;&amp; t2 == n then
            data2 = bits(datasize) UNKNOWN;
        else
            data2 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[t2, datasize];
        Mem[address + 0     , dbytes, accdesc] = data1;
        Mem[address + dbytes, dbytes, accdesc] = data2;

    when <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>
        if <a link="impl-shared.HaveLSE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveLSE2Ext()">HaveLSE2Ext</a>() then
            bits(2*datasize) full_data;
            boolean ispair = TRUE;
            full_data = <a link="impl-aarch64.Mem.read.4" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc, boolean ispair]">Mem</a>[address, 2 * dbytes, accdesc, ispair];
            if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(accdesc.acctype) then
                data2 = full_data&lt;(datasize-1) : 0&gt;;
                data1 = full_data&lt;(2*datasize-1) : datasize&gt;;
            else
                data1 = full_data&lt;(datasize-1) : 0&gt;;
                data2 = full_data&lt;(2*datasize-1) : datasize&gt;;
        else
            data1 = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[address + 0     , dbytes, accdesc];
            data2 = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[address + dbytes, dbytes, accdesc];
        if rt_unknown then
            data1 = bits(datasize) UNKNOWN;
            data2 = bits(datasize) UNKNOWN;
        <a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[t, datasize]  = data1;
        <a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[t2, datasize] = data2;

if wback then
    if postindex then
        address = address + offset;
    if n == 31 then
        <a link="impl-aarch64.SP.write.0" file="shared_pseudocode.xml" hover="accessor: SP[] = bits(64) value">SP</a>[] = address;
    else
        <a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[n, 64] = address;</pstext>
    </ps>
  </ps_section>
</instructionsection>
