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<instructionsection id="STZ2G" title="STZ2G -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="STZ2G" />
  </docvars>
  <heading>STZ2G</heading>
  <desc>
    <brief>
      <para>Store Allocation Tags, Zeroing</para>
    </brief>
    <authored>
      <para>Store Allocation Tags, Zeroing stores an Allocation Tag to two Tag granules of memory, zeroing the associated data locations. The address used for the store is calculated from the base register and an immediate signed offset scaled by the Tag granule. The Allocation Tag is calculated from the Logical Address Tag in the source register.</para>
      <para>This instruction generates an Unchecked access.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from 3 classes:</txt>
      <a href="#iclass_post_indexed">Post-index</a>
      <txt>, </txt>
      <a href="#iclass_pre_indexed">Pre-index</a>
      <txt> and </txt>
      <a href="#iclass_signed_scaled_offset">Signed offset</a>
    </classesintro>
    <iclass name="Post-index" oneof="3" id="iclass_post_indexed" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="address-form" value="post-indexed" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="STZ2G" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.5" feature="FEAT_MTE" />
      </arch_variants>
      <regdiagram form="32" psname="aarch64/instrs/integer/tags/mcsettagpairandzerodatapost">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="23" name="opc&lt;1&gt;" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="opc&lt;0&gt;" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="9" name="imm9" usename="1">
          <c colspan="9"></c>
        </box>
        <box hibit="11" name="op2&lt;1&gt;" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="op2&lt;0&gt;" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="5" name="Xn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Xt" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="STZ2G_64Spost_ldsttags" oneofinclass="1" oneof="3" label="">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="STZ2G" />
        </docvars>
        <asmtemplate><text>STZ2G  </text><a link="sa_xt_sp" hover="64-bit general-purpose source register or SP (field &quot;Xt&quot;)">&lt;Xt|SP&gt;</a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Xn&quot;)">&lt;Xn|SP&gt;</a><text>], #</text><a link="sa_simm" hover="Optional signed immediate offset, multiple of 16 [-4096-4080], default 0 (field &quot;imm9&quot;)">&lt;simm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/integer/tags/mcsettagpairandzerodatapost" mylink="aarch64.instrs.integer.tags.mcsettagpairandzerodatapost" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveMTEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEExt()">HaveMTEExt</a>() then UNDEFINED;
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xn);
integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xt);
bits(64) offset = <a link="impl-shared.LSL.2" file="shared_pseudocode.xml" hover="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm9, 64), <a link="LOG2_TAG_GRANULE" file="shared_pseudocode.xml" hover="constant integer LOG2_TAG_GRANULE = 4">LOG2_TAG_GRANULE</a>);
boolean writeback = TRUE;
boolean postindex = TRUE;
boolean zero_data = TRUE;</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="Pre-index" oneof="3" id="iclass_pre_indexed" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="address-form" value="pre-indexed" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="STZ2G" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.5" feature="FEAT_MTE" />
      </arch_variants>
      <regdiagram form="32" psname="aarch64/instrs/integer/tags/mcsettagpairandzerodatapre">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="23" name="opc&lt;1&gt;" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="opc&lt;0&gt;" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="9" name="imm9" usename="1">
          <c colspan="9"></c>
        </box>
        <box hibit="11" name="op2&lt;1&gt;" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op2&lt;0&gt;" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="5" name="Xn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Xt" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="STZ2G_64Spre_ldsttags" oneofinclass="1" oneof="3" label="">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="STZ2G" />
        </docvars>
        <asmtemplate><text>STZ2G  </text><a link="sa_xt_sp" hover="64-bit general-purpose source register or SP (field &quot;Xt&quot;)">&lt;Xt|SP&gt;</a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Xn&quot;)">&lt;Xn|SP&gt;</a><text>, #</text><a link="sa_simm" hover="Optional signed immediate offset, multiple of 16 [-4096-4080], default 0 (field &quot;imm9&quot;)">&lt;simm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/integer/tags/mcsettagpairandzerodatapre" mylink="aarch64.instrs.integer.tags.mcsettagpairandzerodatapre" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveMTEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEExt()">HaveMTEExt</a>() then UNDEFINED;
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xn);
integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xt);
bits(64) offset = <a link="impl-shared.LSL.2" file="shared_pseudocode.xml" hover="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm9, 64), <a link="LOG2_TAG_GRANULE" file="shared_pseudocode.xml" hover="constant integer LOG2_TAG_GRANULE = 4">LOG2_TAG_GRANULE</a>);
boolean writeback = TRUE;
boolean postindex = FALSE;
boolean zero_data = TRUE;</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="Signed offset" oneof="3" id="iclass_signed_scaled_offset" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="address-form" value="signed-scaled-offset" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="STZ2G" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.5" feature="FEAT_MTE" />
      </arch_variants>
      <regdiagram form="32" psname="aarch64/instrs/integer/tags/mcsettagpairandzerodata">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="23" name="opc&lt;1&gt;" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="opc&lt;0&gt;" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="9" name="imm9" usename="1">
          <c colspan="9"></c>
        </box>
        <box hibit="11" name="op2&lt;1&gt;" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op2&lt;0&gt;" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Xn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Xt" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="STZ2G_64Soffset_ldsttags" oneofinclass="1" oneof="3" label="">
        <docvars>
          <docvar key="address-form" value="signed-scaled-offset" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="STZ2G" />
        </docvars>
        <asmtemplate><text>STZ2G  </text><a link="sa_xt_sp" hover="64-bit general-purpose source register or SP (field &quot;Xt&quot;)">&lt;Xt|SP&gt;</a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Xn&quot;)">&lt;Xn|SP&gt;</a><text>{</text><text>, #</text><a link="sa_simm" hover="Optional signed immediate offset, multiple of 16 [-4096-4080], default 0 (field &quot;imm9&quot;)">&lt;simm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/integer/tags/mcsettagpairandzerodata" mylink="aarch64.instrs.integer.tags.mcsettagpairandzerodata" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveMTEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEExt()">HaveMTEExt</a>() then UNDEFINED;
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xn);
integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xt);
bits(64) offset = <a link="impl-shared.LSL.2" file="shared_pseudocode.xml" hover="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm9, 64), <a link="LOG2_TAG_GRANULE" file="shared_pseudocode.xml" hover="constant integer LOG2_TAG_GRANULE = 4">LOG2_TAG_GRANULE</a>);
boolean writeback = FALSE;
boolean postindex = FALSE;
boolean zero_data = TRUE;</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STZ2G_64Spost_ldsttags, STZ2G_64Soffset_ldsttags, STZ2G_64Spre_ldsttags" symboldefcount="1">
      <symbol link="sa_xt_sp">&lt;Xt|SP&gt;</symbol>
      <account encodedin="Xt">
        <intro>
          <para>Is the 64-bit name of the general-purpose source register or stack pointer, encoded in the "Xt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STZ2G_64Spost_ldsttags, STZ2G_64Soffset_ldsttags, STZ2G_64Spre_ldsttags" symboldefcount="1">
      <symbol link="sa_xn_sp">&lt;Xn|SP&gt;</symbol>
      <account encodedin="Xn">
        <intro>
          <para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Xn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STZ2G_64Spost_ldsttags, STZ2G_64Soffset_ldsttags, STZ2G_64Spre_ldsttags" symboldefcount="1">
      <symbol link="sa_simm">&lt;simm&gt;</symbol>
      <account encodedin="imm9">
        <intro>
          <para>Is the optional signed immediate offset, a multiple of 16 in the range -4096 to 4080, defaulting to 0 and encoded in the "imm9" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/integer/tags/mcsettagpairandzerodatapost" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(64) address;
bits(64) data = if t == 31 then <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[] else <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[t, 64];
bits(4) tag = <a link="AArch64.AllocationTagFromAddress.1" file="shared_pseudocode.xml" hover="function: bits(4) AArch64.AllocationTagFromAddress(bits(64) tagged_address)">AArch64.AllocationTagFromAddress</a>(data);

if n == 31 then
    <a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
    address = <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[];
else
    address = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];

if !postindex then
    address = address + offset;

<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescLDGSTG.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescLDGSTG(MemOp memop)">CreateAccDescLDGSTG</a>(<a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>);

if zero_data then
    if !<a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, <a link="TAG_GRANULE" file="shared_pseudocode.xml" hover="constant integer TAG_GRANULE = 1 &lt;&lt; LOG2_TAG_GRANULE">TAG_GRANULE</a>) then
        <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));

    Mem[address, TAG_GRANULE, accdesc] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(<a link="TAG_GRANULE" file="shared_pseudocode.xml" hover="constant integer TAG_GRANULE = 1 &lt;&lt; LOG2_TAG_GRANULE">TAG_GRANULE</a> * 8);
    Mem[address+TAG_GRANULE, TAG_GRANULE, accdesc] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(<a link="TAG_GRANULE" file="shared_pseudocode.xml" hover="constant integer TAG_GRANULE = 1 &lt;&lt; LOG2_TAG_GRANULE">TAG_GRANULE</a> * 8);

<a link="AArch64.MemTag.write.2" file="shared_pseudocode.xml" hover="accessor: AArch64.MemTag[bits(64) address, AccessDescriptor accdesc_in] = bits(4) value">AArch64.MemTag</a>[address, accdesc] = tag;
<a link="AArch64.MemTag.write.2" file="shared_pseudocode.xml" hover="accessor: AArch64.MemTag[bits(64) address, AccessDescriptor accdesc_in] = bits(4) value">AArch64.MemTag</a>[address+<a link="TAG_GRANULE" file="shared_pseudocode.xml" hover="constant integer TAG_GRANULE = 1 &lt;&lt; LOG2_TAG_GRANULE">TAG_GRANULE</a>, accdesc] = tag;

if writeback then
    if postindex then
        address = address + offset;

    if n == 31 then
        <a link="impl-aarch64.SP.write.0" file="shared_pseudocode.xml" hover="accessor: SP[] = bits(64) value">SP</a>[] = address;
    else
        <a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[n, 64] = address;</pstext>
    </ps>
  </ps_section>
</instructionsection>
