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<instructionsection id="uqdecw_r_rs" title="UQDECW (scalar)" type="instruction">
  <docvars>
    <docvar key="instr-class" value="sve" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="UQDECW" />
    <docvar key="sve-esize" value="esize-word" />
  </docvars>
  <heading>UQDECW (scalar)</heading>
  <desc>
    <brief>Unsigned saturating decrement scalar by multiple of 32-bit predicate constraint element count</brief>
    <description>
      <para>Determines the number of active 32-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement the scalar destination. The result is saturated to the general-purpose register's unsigned integer range.</para>
      <para>The named predicate constraint limits the number of active elements in a single predicate to:</para>
      <list type="unordered">
        <listitem>
          <content>A fixed number (<value>VL1</value> to <value>VL256</value>)</content>
        </listitem>
        <listitem>
          <content>The largest power of two (<value>POW2</value>)</content>
        </listitem>
        <listitem>
          <content>The largest multiple of three or four (<value>MUL3</value> or <value>MUL4</value>)</content>
        </listitem>
        <listitem>
          <content>All available, implicitly a multiple of two (<value>ALL</value>).</content>
        </listitem>
      </list>
      <para>Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.</para>
    </description>
    <status>Green</status>
    <predicated>False</predicated>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from 2 classes:</txt>
      <a href="#iclass_32_fsreg">32-bit</a>
      <txt> and </txt>
      <a href="#iclass_64_fsreg">64-bit</a>
    </classesintro>
    <iclass name="32-bit" oneof="2" id="iclass_32_fsreg" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="atomic-ops" value="UQDECW-32-fsreg" />
        <docvar key="instr-class" value="sve" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="UQDECW" />
        <docvar key="reg-type" value="32-fsreg" />
        <docvar key="sve-esize" value="esize-word" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="UQDECW-R.RS-UW" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" name="size&lt;1&gt;" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="size&lt;0&gt;" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="sf" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" name="D" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="U" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="5" name="pattern" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rdn" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="uqdecw_r_rs_uw" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="atomic-ops" value="UQDECW-32-fsreg" />
          <docvar key="instr-class" value="sve" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="UQDECW" />
          <docvar key="reg-type" value="32-fsreg" />
          <docvar key="sve-esize" value="esize-word" />
        </docvars>
        <asmtemplate><text>UQDECW  </text><a link="sa_wdn" hover="32-bit source and destination general-purpose register (field &quot;Rdn&quot;)">&lt;Wdn&gt;</a><text>{</text><text>, </text><a link="sa_pattern" hover="Optional pattern specifier, default ALL (field &quot;pattern&quot;) [#uimm5,ALL,MUL3,MUL4,POW2,VL1,VL2,VL3,VL4,VL5,VL6,VL7,VL8,VL16,VL32,VL64,VL128,VL256]">&lt;pattern&gt;</a><text>{</text><text>, MUL #</text><a link="sa_imm" hover="Immediate multiplier [1-16], default 1 (field &quot;imm4&quot;)">&lt;imm&gt;</a><text>}</text><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="UQDECW-R.RS-UW" mylink="UQDECW-R.RS-UW" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() &amp;&amp; !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
constant integer esize = 32;
integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdn);
bits(5) pat = pattern;
integer imm = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm4) + 1;
boolean unsigned = TRUE;
integer ssize = 32;</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="64-bit" oneof="2" id="iclass_64_fsreg" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="atomic-ops" value="UQDECW-64-fsreg" />
        <docvar key="instr-class" value="sve" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="UQDECW" />
        <docvar key="reg-type" value="64-fsreg" />
        <docvar key="sve-esize" value="esize-word" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="UQDECW-R.RS-X" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" name="size&lt;1&gt;" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="size&lt;0&gt;" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="sf" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" name="D" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="U" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="5" name="pattern" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rdn" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="uqdecw_r_rs_x" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="atomic-ops" value="UQDECW-64-fsreg" />
          <docvar key="instr-class" value="sve" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="UQDECW" />
          <docvar key="reg-type" value="64-fsreg" />
          <docvar key="sve-esize" value="esize-word" />
        </docvars>
        <asmtemplate><text>UQDECW  </text><a link="sa_xdn" hover="64-bit source and destination general-purpose register (field &quot;Rdn&quot;)">&lt;Xdn&gt;</a><text>{</text><text>, </text><a link="sa_pattern" hover="Optional pattern specifier, default ALL (field &quot;pattern&quot;) [#uimm5,ALL,MUL3,MUL4,POW2,VL1,VL2,VL3,VL4,VL5,VL6,VL7,VL8,VL16,VL32,VL64,VL128,VL256]">&lt;pattern&gt;</a><text>{</text><text>, MUL #</text><a link="sa_imm" hover="Immediate multiplier [1-16], default 1 (field &quot;imm4&quot;)">&lt;imm&gt;</a><text>}</text><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="UQDECW-R.RS-X" mylink="UQDECW-R.RS-X" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() &amp;&amp; !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
constant integer esize = 32;
integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdn);
bits(5) pat = pattern;
integer imm = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm4) + 1;
boolean unsigned = TRUE;
integer ssize = 64;</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="uqdecw_r_rs_uw" symboldefcount="1">
      <symbol link="sa_wdn">&lt;Wdn&gt;</symbol>
      <account encodedin="Rdn">
        <intro>
          <para>Is the 32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="uqdecw_r_rs_x" symboldefcount="1">
      <symbol link="sa_xdn">&lt;Xdn&gt;</symbol>
      <account encodedin="Rdn">
        <intro>
          <para>Is the 64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="uqdecw_r_rs_uw, uqdecw_r_rs_x" symboldefcount="1">
      <symbol link="sa_pattern">&lt;pattern&gt;</symbol>
      <definition encodedin="pattern">
        <intro>Is the optional pattern specifier, defaulting to ALL, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">pattern</entry>
                <entry class="symbol">&lt;pattern&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00000</entry>
                <entry class="symbol">POW2</entry>
              </row>
              <row>
                <entry class="bitfield">00001</entry>
                <entry class="symbol">VL1</entry>
              </row>
              <row>
                <entry class="bitfield">00010</entry>
                <entry class="symbol">VL2</entry>
              </row>
              <row>
                <entry class="bitfield">00011</entry>
                <entry class="symbol">VL3</entry>
              </row>
              <row>
                <entry class="bitfield">00100</entry>
                <entry class="symbol">VL4</entry>
              </row>
              <row>
                <entry class="bitfield">00101</entry>
                <entry class="symbol">VL5</entry>
              </row>
              <row>
                <entry class="bitfield">00110</entry>
                <entry class="symbol">VL6</entry>
              </row>
              <row>
                <entry class="bitfield">00111</entry>
                <entry class="symbol">VL7</entry>
              </row>
              <row>
                <entry class="bitfield">01000</entry>
                <entry class="symbol">VL8</entry>
              </row>
              <row>
                <entry class="bitfield">01001</entry>
                <entry class="symbol">VL16</entry>
              </row>
              <row>
                <entry class="bitfield">01010</entry>
                <entry class="symbol">VL32</entry>
              </row>
              <row>
                <entry class="bitfield">01011</entry>
                <entry class="symbol">VL64</entry>
              </row>
              <row>
                <entry class="bitfield">01100</entry>
                <entry class="symbol">VL128</entry>
              </row>
              <row>
                <entry class="bitfield">01101</entry>
                <entry class="symbol">VL256</entry>
              </row>
              <row>
                <entry class="bitfield">0111x</entry>
                <entry class="symbol">#uimm5</entry>
              </row>
              <row>
                <entry class="bitfield">101x1</entry>
                <entry class="symbol">#uimm5</entry>
              </row>
              <row>
                <entry class="bitfield">10110</entry>
                <entry class="symbol">#uimm5</entry>
              </row>
              <row>
                <entry class="bitfield">1x0x1</entry>
                <entry class="symbol">#uimm5</entry>
              </row>
              <row>
                <entry class="bitfield">1x010</entry>
                <entry class="symbol">#uimm5</entry>
              </row>
              <row>
                <entry class="bitfield">1xx00</entry>
                <entry class="symbol">#uimm5</entry>
              </row>
              <row>
                <entry class="bitfield">11101</entry>
                <entry class="symbol">MUL4</entry>
              </row>
              <row>
                <entry class="bitfield">11110</entry>
                <entry class="symbol">MUL3</entry>
              </row>
              <row>
                <entry class="bitfield">11111</entry>
                <entry class="symbol">ALL</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="uqdecw_r_rs_uw, uqdecw_r_rs_x" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm4">
        <intro>
          <para>Is the immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="UQDECW-R.RS-UW" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
integer count = <a link="impl-aarch64.DecodePredCount.2" file="shared_pseudocode.xml" hover="function: integer DecodePredCount(bits(5) pattern, integer esize)">DecodePredCount</a>(pat, esize);
bits(ssize) operand1 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[dn, ssize];
bits(ssize) result;

integer element1 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(operand1, unsigned);
(result, -) = <a link="impl-shared.SatQ.3" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element1 - (count * imm), ssize, unsigned);
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[dn, 64] = <a link="impl-shared.Extend.3" file="shared_pseudocode.xml" hover="function: bits(N) Extend(bits(M) x, integer N, boolean unsigned)">Extend</a>(result, 64, unsigned);</pstext>
    </ps>
  </ps_section>
</instructionsection>
