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<instructionsection id="luti4_mz4_ztz" title="LUTI4 (four registers)" type="instruction">
  <docvars>
    <docvar key="instr-class" value="mortlach2" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="LUTI4" />
  </docvars>
  <heading>LUTI4 (four registers)</heading>
  <desc>
    <brief>Lookup table read with 4-bit indexes</brief>
    <description>
      <para>Copy 16-bit or 32-bit elements from ZT0 to four destination vectors using packed 4-bit indices from a segment of the source vector register. A segment corresponds to a portion of the source vector that is consumed in order to fill the destination vector. The segment is selected by the vector segment index modulo the total number of segments.</para>
      <para>This instruction is unpredicated.</para>
    </description>
    <status>S1: Green, S2: Amber</status>
    <predicated>False</predicated>
    <sm_policy>SM_1_only</sm_policy>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from 2 classes:</txt>
      <a href="#iclass_consecutive">Consecutive</a>
      <txt> and </txt>
      <a href="#iclass_strided">Strided</a>
    </classesintro>
    <iclass name="Consecutive" oneof="2" id="iclass_consecutive" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="mortlach2" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="LUTI4" />
        <docvar key="stride-type" value="consecutive" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
      </arch_variants>
      <regdiagram form="32" psname="LUTI4-MZ4.ZTZ-1">
        <box hibit="31" width="13" settings="13">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="18" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="16" name="i1" usename="1">
          <c></c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="11" width="2" name="opc2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Zn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="3" name="Zd" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="1" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="luti4_mz4_ztz_1" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="instr-class" value="mortlach2" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="LUTI4" />
          <docvar key="stride-type" value="consecutive" />
        </docvars>
        <asmtemplate><text>LUTI4   </text><text>{</text><text> </text><a link="sa_zd1" hover="First destination scalable vector register of a multi-vector sequence (field Zd)">&lt;Zd1&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;size&quot;) [H,S]">&lt;T&gt;</a><text>-</text><a link="sa_zd4" hover="Fourth destination scalable vector register of a multi-vector sequence (field Zd)">&lt;Zd4&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;size&quot;) [H,S]">&lt;T&gt;</a><text> </text><text>}</text><text>, ZT0, </text><a link="sa_zn" hover="Source scalable vector register (field &quot;Zn&quot;)">&lt;Zn&gt;</a><text>[</text><a link="sa_index" hover="Vector segment index [0-1] (field &quot;i1&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="LUTI4-MZ4.ZTZ-1" mylink="LUTI4-MZ4.ZTZ-1" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
if size == '00' || size == '11' then UNDEFINED;
constant integer esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
integer isize = 4;
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
integer dstride = 1;
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd:'00');
integer imm = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(i1);
constant integer nreg = 4;</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="Strided" oneof="2" id="iclass_strided" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="mortlach2" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="LUTI4" />
        <docvar key="stride-type" value="strided" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="FEAT_SME2p1" feature="FEAT_SME2p1" />
      </arch_variants>
      <regdiagram form="32" psname="LUTI4-MZ4.ZTZ-4">
        <box hibit="31" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="29" width="10" settings="10">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" settings="1">
          <c>1</c>
        </box>
        <box hibit="18" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="16" name="i1" usename="1">
          <c></c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="11" width="2" name="opc2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Zn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="3" settings="1">
          <c>0</c>
        </box>
        <box hibit="2" settings="1">
          <c>0</c>
        </box>
        <box hibit="1" width="2" name="Zd" usename="1">
          <c colspan="2"></c>
        </box>
      </regdiagram>
      <encoding name="luti4_mz4_ztz_4" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="instr-class" value="mortlach2" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="LUTI4" />
          <docvar key="stride-type" value="strided" />
        </docvars>
        <asmtemplate><text>LUTI4   </text><text>{</text><text> </text><a link="sa_zd1_1" hover="First destination scalable vector register Z0-Z3 or Z16-Z19 of a multi-vector sequence (field D:'00':Zd)">&lt;Zd1&gt;</a><text>.H, </text><a link="sa_zd2" hover="Second destination scalable vector register Z4-Z7 or Z20-Z23 of a multi-vector sequence (field D:'01':Zd)">&lt;Zd2&gt;</a><text>.H, </text><a link="sa_zd3" hover="Third destination scalable vector register Z8-Z11 or Z24-Z27 of a multi-vector sequence (field D:'10':Zd)">&lt;Zd3&gt;</a><text>.H, </text><a link="sa_zd4_1" hover="Fourth destination scalable vector register Z12-Z15 or Z28-Z31 of a multi-vector sequence (field D:'11':Zd)">&lt;Zd4&gt;</a><text>.H </text><text>}</text><text>, ZT0, </text><a link="sa_zn" hover="Source scalable vector register (field &quot;Zn&quot;)">&lt;Zn&gt;</a><text>[</text><a link="sa_index" hover="Vector segment index [0-1] (field &quot;i1&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="LUTI4-MZ4.ZTZ-4" mylink="LUTI4-MZ4.ZTZ-4" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2p1.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2p1()">HaveSME2p1</a>() then UNDEFINED;
if size != '01' then UNDEFINED;
constant integer esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
integer isize = 4;
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
integer dstride = 4;
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:'00':Zd);
integer imm = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(i1);
constant integer nreg = 4;</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="luti4_mz4_ztz_1" symboldefcount="1">
      <symbol link="sa_zd1">&lt;Zd1&gt;</symbol>
      <account encodedin="Zd">
        <docvars>
          <docvar key="stride-type" value="consecutive" />
        </docvars>
        <intro>
          <para>For the consecutive variant: is the name of the first destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 4.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="luti4_mz4_ztz_4" symboldefcount="2">
      <symbol link="sa_zd1_1">&lt;Zd1&gt;</symbol>
      <account encodedin="00:D:Zd">
        <docvars>
          <docvar key="stride-type" value="strided" />
        </docvars>
        <intro>
          <para>For the strided variant: is the name of the first destination scalable vector register Z0-Z3 or Z16-Z19 of a multi-vector sequence, encoded as "D:'00':Zd".</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="luti4_mz4_ztz_4" symboldefcount="1">
      <symbol link="sa_zd2">&lt;Zd2&gt;</symbol>
      <account encodedin="01:D:Zd">
        <intro>
          <para>Is the name of the second destination scalable vector register Z4-Z7 or Z20-Z23 of a multi-vector sequence, encoded as "D:'01':Zd".</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="luti4_mz4_ztz_4" symboldefcount="1">
      <symbol link="sa_zd3">&lt;Zd3&gt;</symbol>
      <account encodedin="10:D:Zd">
        <intro>
          <para>Is the name of the third destination scalable vector register Z8-Z11 or Z24-Z27 of a multi-vector sequence, encoded as "D:'10':Zd".</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="luti4_mz4_ztz_1" symboldefcount="1">
      <symbol link="sa_t">&lt;T&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the size specifier, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;T&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">H</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="luti4_mz4_ztz_1" symboldefcount="1">
      <symbol link="sa_zd4">&lt;Zd4&gt;</symbol>
      <account encodedin="Zd">
        <docvars>
          <docvar key="stride-type" value="consecutive" />
        </docvars>
        <intro>
          <para>For the consecutive variant: is the name of the fourth destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 4 plus 3.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="luti4_mz4_ztz_4" symboldefcount="2">
      <symbol link="sa_zd4_1">&lt;Zd4&gt;</symbol>
      <account encodedin="11:D:Zd">
        <docvars>
          <docvar key="stride-type" value="strided" />
        </docvars>
        <intro>
          <para>For the strided variant: is the name of the fourth destination scalable vector register Z12-Z15 or Z28-Z31 of a multi-vector sequence, encoded as "D:'11':Zd".</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="luti4_mz4_ztz_1, luti4_mz4_ztz_4" symboldefcount="1">
      <symbol link="sa_zn">&lt;Zn&gt;</symbol>
      <account encodedin="Zn">
        <intro>
          <para>Is the name of the source scalable vector register, encoded in the "Zn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="luti4_mz4_ztz_1, luti4_mz4_ztz_4" symboldefcount="1">
      <symbol link="sa_index">&lt;index&gt;</symbol>
      <account encodedin="i1">
        <intro>
          <para>Is the vector segment index, in the range 0 to 1, encoded in the "i1" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="LUTI4-MZ4.ZTZ-1" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEEnabled()">CheckStreamingSVEEnabled</a>();
<a link="impl-aarch64.CheckSMEZT0Enabled.0" file="shared_pseudocode.xml" hover="function: CheckSMEZT0Enabled()">CheckSMEZT0Enabled</a>();
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
constant integer elements = VL DIV esize;
integer segments = esize DIV (isize * nreg);
integer segment = imm MOD segments;
bits(VL) indexes = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
bits(512) table = <a link="impl-aarch64.ZT0.read.1" file="shared_pseudocode.xml" hover="accessor: bits(width) ZT0[integer width]">ZT0</a>[512];

for r = 0 to nreg-1
    integer base = (segment * nreg + r) * elements;
    bits(VL) result = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[d, VL];
    for e = 0 to elements-1
        integer index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indexes, base+e, isize]);
        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 32]&lt;esize-1:0&gt;;
    <a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;
    d = d + dstride;</pstext>
    </ps>
  </ps_section>
</instructionsection>
