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<instructionsection id="FMAXNM_float" title="FMAXNM (scalar) -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="float" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="FMAXNM" />
  </docvars>
  <heading>FMAXNM (scalar)</heading>
  <desc>
    <brief>
      <para>Floating-point Maximum Number (scalar)</para>
    </brief>
    <authored>
      <para>Floating-point Maximum Number (scalar). This instruction compares the first and second source SIMD&amp;FP register values, and writes the larger of the two floating-point values to the destination SIMD&amp;FP register.</para>
      <para>NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result that is placed in the vector is the numerical value, otherwise the result is identical to <xref linkend="A64.instructions.FMAX_float">FMAX (scalar)</xref>.</para>
      <para>This instruction can generate a floating-point exception. Depending on the settings in <xref linkend="AArch64.fpcr">FPCR</xref>, the exception results in either a flag being set in <xref linkend="AArch64.fpsr">FPSR</xref>, or a synchronous exception being generated. For more information, see <xref linkend="BEIJDDAG">Floating-point exception traps</xref>.</para>
      <para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="Floating-point" oneof="1" id="iclass_float" no_encodings="3" isa="A64">
      <docvars>
        <docvar key="instr-class" value="float" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="FMAXNM" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch64/instrs/float/arithmetic/max-min" tworows="1">
        <box hibit="31" name="M" settings="1">
          <c>0</c>
        </box>
        <box hibit="30" settings="1">
          <c>0</c>
        </box>
        <box hibit="29" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="28" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="2" name="ftype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="5" name="Rm" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" width="2" name="opcode[3:2]" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="13" width="2" name="op" usename="1" settings="2" psbits="xx">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="FMAXNM_H_floatdp2" oneofinclass="3" oneof="3" label="Half-precision" bitdiffs="ftype == 11">
        <docvars>
          <docvar key="datatype" value="half" />
          <docvar key="instr-class" value="float" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FMAXNM" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="23" width="2" name="ftype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>FMAXNM  </text><a link="sa_hd" hover="16-bit SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Hd&gt;</a><text>, </text><a link="sa_hn" hover="First 16-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Hn&gt;</a><text>, </text><a link="sa_hm" hover="Second 16-bit SIMD&amp;FP source register (field &quot;Rm&quot;)">&lt;Hm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="FMAXNM_S_floatdp2" oneofinclass="3" oneof="3" label="Single-precision" bitdiffs="ftype == 00">
        <docvars>
          <docvar key="datatype" value="single" />
          <docvar key="instr-class" value="float" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FMAXNM" />
        </docvars>
        <box hibit="23" width="2" name="ftype">
          <c>0</c>
          <c>0</c>
        </box>
        <asmtemplate><text>FMAXNM  </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Rm&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="FMAXNM_D_floatdp2" oneofinclass="3" oneof="3" label="Double-precision" bitdiffs="ftype == 01">
        <docvars>
          <docvar key="datatype" value="double" />
          <docvar key="instr-class" value="float" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FMAXNM" />
        </docvars>
        <box hibit="23" width="2" name="ftype">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>FMAXNM  </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Rm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/float/arithmetic/max-min" mylink="aarch64.instrs.float.arithmetic.max-min" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);

integer esize;
case ftype of
    when '00' esize = 32;
    when '01' esize = 64;
    when '10' UNDEFINED;
    when '11'
        if <a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then
            esize = 16;
        else
            UNDEFINED;

<a link="FPMaxMinOp" file="shared_pseudocode.xml" hover="enumeration FPMaxMinOp  {FPMaxMinOp_MAX, FPMaxMinOp_MIN, FPMaxMinOp_MAXNUM, FPMaxMinOp_MINNUM}">FPMaxMinOp</a> operation;
case op of
    when '00' operation = <a link="FPMaxMinOp_MAX" file="shared_pseudocode.xml" hover="enumeration FPMaxMinOp  {FPMaxMinOp_MAX, FPMaxMinOp_MIN, FPMaxMinOp_MAXNUM, FPMaxMinOp_MINNUM}">FPMaxMinOp_MAX</a>;
    when '01' operation = <a link="FPMaxMinOp_MIN" file="shared_pseudocode.xml" hover="enumeration FPMaxMinOp  {FPMaxMinOp_MAX, FPMaxMinOp_MIN, FPMaxMinOp_MAXNUM, FPMaxMinOp_MINNUM}">FPMaxMinOp_MIN</a>;
    when '10' operation = <a link="FPMaxMinOp_MAXNUM" file="shared_pseudocode.xml" hover="enumeration FPMaxMinOp  {FPMaxMinOp_MAX, FPMaxMinOp_MIN, FPMaxMinOp_MAXNUM, FPMaxMinOp_MINNUM}">FPMaxMinOp_MAXNUM</a>;
    when '11' operation = <a link="FPMaxMinOp_MINNUM" file="shared_pseudocode.xml" hover="enumeration FPMaxMinOp  {FPMaxMinOp_MAX, FPMaxMinOp_MIN, FPMaxMinOp_MAXNUM, FPMaxMinOp_MINNUM}">FPMaxMinOp_MINNUM</a>;</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="FMAXNM_D_floatdp2" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMAXNM_D_floatdp2" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMAXNM_D_floatdp2" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMAXNM_H_floatdp2" symboldefcount="1">
      <symbol link="sa_hd">&lt;Hd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 16-bit name of the SIMD&amp;FP destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMAXNM_H_floatdp2" symboldefcount="1">
      <symbol link="sa_hn">&lt;Hn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 16-bit name of the first SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMAXNM_H_floatdp2" symboldefcount="1">
      <symbol link="sa_hm">&lt;Hm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 16-bit name of the second SIMD&amp;FP source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMAXNM_S_floatdp2" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMAXNM_S_floatdp2" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 32-bit name of the first SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMAXNM_S_floatdp2" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/float/arithmetic/max-min" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPEnabled64()">CheckFPEnabled64</a>();
bits(esize) operand1 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, esize];
bits(esize) operand2 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[m, esize];

<a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr    = FPCR[];
boolean merge    = <a link="impl-shared.IsMerging.1" file="shared_pseudocode.xml" hover="function: boolean IsMerging(FPCRType fpcr)">IsMerging</a>(fpcr);
bits(128) result = if merge then <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, 128] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(128);

case operation of
    when <a link="FPMaxMinOp_MAX" file="shared_pseudocode.xml" hover="enumeration FPMaxMinOp  {FPMaxMinOp_MAX, FPMaxMinOp_MIN, FPMaxMinOp_MAXNUM, FPMaxMinOp_MINNUM}">FPMaxMinOp_MAX</a>    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 0, esize] = <a link="impl-shared.FPMax.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(operand1, operand2, fpcr);
    when <a link="FPMaxMinOp_MIN" file="shared_pseudocode.xml" hover="enumeration FPMaxMinOp  {FPMaxMinOp_MAX, FPMaxMinOp_MIN, FPMaxMinOp_MAXNUM, FPMaxMinOp_MINNUM}">FPMaxMinOp_MIN</a>    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 0, esize] = <a link="impl-shared.FPMin.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(operand1, operand2, fpcr);
    when <a link="FPMaxMinOp_MAXNUM" file="shared_pseudocode.xml" hover="enumeration FPMaxMinOp  {FPMaxMinOp_MAX, FPMaxMinOp_MIN, FPMaxMinOp_MAXNUM, FPMaxMinOp_MINNUM}">FPMaxMinOp_MAXNUM</a> <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 0, esize] = <a link="impl-shared.FPMaxNum.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMaxNum(bits(N) op1_in, bits(N) op2_in, FPCRType fpcr)">FPMaxNum</a>(operand1, operand2, fpcr);
    when <a link="FPMaxMinOp_MINNUM" file="shared_pseudocode.xml" hover="enumeration FPMaxMinOp  {FPMaxMinOp_MAX, FPMaxMinOp_MIN, FPMaxMinOp_MAXNUM, FPMaxMinOp_MINNUM}">FPMaxMinOp_MINNUM</a> <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 0, esize] = <a link="impl-shared.FPMinNum.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMinNum(bits(N) op1_in, bits(N) op2_in, FPCRType fpcr)">FPMinNum</a>(operand1, operand2, fpcr);

<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = result;</pstext>
    </ps>
  </ps_section>
</instructionsection>
