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<instructionsection id="bfsub_za_zw" title="BFSUB" type="instruction">
  <docvars>
    <docvar key="instr-class" value="mortlach2" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="BFSUB" />
  </docvars>
  <heading>BFSUB</heading>
  <desc>
    <brief>BFloat16 floating-point subtract multi-vector from ZA array vector accumulators</brief>
    <description>
      <para>The instruction operates on two or four ZA single-vector groups.</para>
      <para>Destructively subtract all elements of the two or four source vectors from the corresponding BFloat16 elements of the two or four ZA single-vector groups. The vector numbers forming the single-vector group within each half or each quarter of the ZA array are selected by the sum of the vector select register and immediate offset, modulo half or quarter the number of ZA array vectors.</para>
      <para>The <arm-defined-word>vector group</arm-defined-word> symbol, <syntax>VGx2</syntax> or <syntax>VGx4</syntax>, indicates that the ZA operand consists of two or four ZA single-vector groups respectively. The <arm-defined-word>vector group</arm-defined-word> symbol is preferred for disassembly, but optional in assembler source code.</para>
      <para>This instruction follows SME2.1 ZA-targeting non-widening BFloat16 numerical behaviors.</para>
      <para>This instruction is unpredicated.</para>
      <para>ID_AA64SMFR0_EL1.B16B16 indicates whether this instruction is implemented.</para>
    </description>
    <status>Green</status>
    <predicated>False</predicated>
    <sm_policy>SM_1_only</sm_policy>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from 2 classes:</txt>
      <a href="#iclass_sme_vgx2_single">Two ZA single-vectors</a>
      <txt> and </txt>
      <a href="#iclass_sme_vgx4_single">Four ZA single-vectors</a>
    </classesintro>
    <iclass name="Two ZA single-vectors" oneof="2" id="iclass_sme_vgx2_single" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="mortlach2" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="BFSUB" />
        <docvar key="sme-multireg" value="sme-vgx2-single" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="FEAT_B16B16" feature="FEAT_B16B16" />
      </arch_variants>
      <regdiagram form="32" psname="BFSUB-ZA.ZW-2x2_16" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="sz" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" width="7" settings="7">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="14" width="2" name="Rv" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="12" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="4" name="Zm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="5" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" name="S" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="2" width="3" name="off3" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="bfsub_za_zw_2x2_16" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="instr-class" value="mortlach2" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="BFSUB" />
          <docvar key="sme-multireg" value="sme-vgx2-single" />
        </docvars>
        <asmtemplate><text>BFSUB   ZA.H[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field &quot;Rv&quot;)">&lt;Wv&gt;</a><text>, </text><a link="sa_offs" hover="Vector select offset [0-7] (field &quot;off3&quot;)">&lt;offs&gt;</a><a>{, VGx2}</a><text>], </text><text>{</text><text> </text><a link="sa_zm1" hover="First scalable vector register of a multi-vector sequence (field Zm)">&lt;Zm1&gt;</a><text>.H-</text><a link="sa_zm2" hover="Second scalable vector register of a multi-vector sequence (field Zm)">&lt;Zm2&gt;</a><text>.H </text><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="BFSUB-ZA.ZW-2x2_16" mylink="BFSUB-ZA.ZW-2x2_16" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSMEB16B16.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEB16B16()">HaveSMEB16B16</a>() then UNDEFINED;
integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm:'0');
integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(off3);
constant integer nreg = 2;</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="Four ZA single-vectors" oneof="2" id="iclass_sme_vgx4_single" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="mortlach2" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="BFSUB" />
        <docvar key="sme-multireg" value="sme-vgx4-single" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="FEAT_B16B16" feature="FEAT_B16B16" />
      </arch_variants>
      <regdiagram form="32" psname="BFSUB-ZA.ZW-4x4_16" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="sz" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" width="7" settings="7">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="14" width="2" name="Rv" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="12" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="3" name="Zm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="6" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" name="S" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="2" width="3" name="off3" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="bfsub_za_zw_4x4_16" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="instr-class" value="mortlach2" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="BFSUB" />
          <docvar key="sme-multireg" value="sme-vgx4-single" />
        </docvars>
        <asmtemplate><text>BFSUB   ZA.H[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field &quot;Rv&quot;)">&lt;Wv&gt;</a><text>, </text><a link="sa_offs" hover="Vector select offset [0-7] (field &quot;off3&quot;)">&lt;offs&gt;</a><a>{, VGx4}</a><text>], </text><text>{</text><text> </text><a link="sa_zm1_1" hover="First scalable vector register of a multi-vector sequence (field Zm)">&lt;Zm1&gt;</a><text>.H-</text><a link="sa_zm4" hover="Fourth scalable vector register of a multi-vector sequence (field Zm)">&lt;Zm4&gt;</a><text>.H </text><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="BFSUB-ZA.ZW-4x4_16" mylink="BFSUB-ZA.ZW-4x4_16" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSMEB16B16.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEB16B16()">HaveSMEB16B16</a>() then UNDEFINED;
integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm:'00');
integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(off3);
constant integer nreg = 4;</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="bfsub_za_zw_2x2_16, bfsub_za_zw_4x4_16" symboldefcount="1">
      <symbol link="sa_wv">&lt;Wv&gt;</symbol>
      <account encodedin="Rv">
        <intro>
          <para>Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="bfsub_za_zw_2x2_16, bfsub_za_zw_4x4_16" symboldefcount="1">
      <symbol link="sa_offs">&lt;offs&gt;</symbol>
      <account encodedin="off3">
        <intro>
          <para>Is the vector select offset, in the range 0 to 7, encoded in the "off3" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="bfsub_za_zw_2x2_16" symboldefcount="1">
      <symbol link="sa_zm1">&lt;Zm1&gt;</symbol>
      <account encodedin="Zm">
        <docvars>
          <docvar key="sme-multireg" value="sme-vgx2-single" />
        </docvars>
        <intro>
          <para>For the two ZA single-vectors variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zm" times 2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="bfsub_za_zw_4x4_16" symboldefcount="2">
      <symbol link="sa_zm1_1">&lt;Zm1&gt;</symbol>
      <account encodedin="Zm">
        <docvars>
          <docvar key="sme-multireg" value="sme-vgx4-single" />
        </docvars>
        <intro>
          <para>For the four ZA single-vectors variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zm" times 4.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="bfsub_za_zw_4x4_16" symboldefcount="1">
      <symbol link="sa_zm4">&lt;Zm4&gt;</symbol>
      <account encodedin="Zm">
        <intro>
          <para>Is the name of the fourth scalable vector register of a multi-vector sequence, encoded as "Zm" times 4 plus 3.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="bfsub_za_zw_2x2_16" symboldefcount="1">
      <symbol link="sa_zm2">&lt;Zm2&gt;</symbol>
      <account encodedin="Zm">
        <intro>
          <para>Is the name of the second scalable vector register of a multi-vector sequence, encoded as "Zm" times 2 plus 1.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="BFSUB-ZA.ZW-2x2_16" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckStreamingSVEAndZAEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEAndZAEnabled()">CheckStreamingSVEAndZAEnabled</a>();
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
constant integer elements = VL DIV 16;
integer vectors = VL DIV 8;
integer vstride = vectors DIV nreg;
bits(32) vbase = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[v, 32];
integer vec = (<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(vbase) + offset) MOD vstride;
bits(VL) result;

for r = 0 to nreg-1
    bits(VL) operand1 = <a link="impl-aarch64.ZAvector.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) ZAvector[integer index, integer width]">ZAvector</a>[vec, VL];
    bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m+r, VL];
    for e = 0 to elements-1
        bits(16) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 16];
        bits(16) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 16];
        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 16] = <a link="impl-shared.BFSub_ZA.3" file="shared_pseudocode.xml" hover="function: bits(16) BFSub_ZA(bits(16) op1, bits(16) op2, FPCRType fpcr_in)">BFSub_ZA</a>(element1, element2, FPCR[]);
    <a link="impl-aarch64.ZAvector.write.2" file="shared_pseudocode.xml" hover="accessor: ZAvector[integer index, integer width] = bits(width) value">ZAvector</a>[vec, VL] = result;
    vec = vec + vstride;</pstext>
    </ps>
  </ps_section>
</instructionsection>
