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<instructionsection id="smlall_za_zzv" title="SMLALL (multiple and single vector)" type="instruction">
  <docvars>
    <docvar key="instr-class" value="mortlach2" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="SMLALL" />
  </docvars>
  <heading>SMLALL (multiple and single vector)</heading>
  <desc>
    <brief>Multi-vector signed integer multiply-add long long by vector</brief>
    <description>
      <para>The instruction operates on one, two, or four ZA quad-vector groups.</para>
      <para>This signed integer multiply-add long long instruction multiplies each signed 8-bit or 16-bit element in the one, two, or four first source vectors with each signed 8-bit or 16-bit element in the second source vector, widens each product to 32-bits or 64-bits and destructively adds these values to the corresponding 32-bit or 64-bit elements of the one, two, or four ZA quad-vector groups. The lowest of the four consecutive vector numbers forming the quad-vector group within all, each half, or each quarter of the ZA array are selected by the sum of the vector select register and immediate offset, modulo all, half, or quarter the number of ZA array vectors.</para>
      <para>The <arm-defined-word>vector group</arm-defined-word> symbol, <syntax>VGx2</syntax> or <syntax>VGx4</syntax>, indicates that the ZA operand consists of two or four ZA quad-vector groups respectively. The <arm-defined-word>vector group</arm-defined-word> symbol is preferred for disassembly, but optional in assembler source code.</para>
      <para>This instruction is unpredicated.</para>
      <para>ID_AA64SMFR0_EL1.I16I64 indicates whether the 16-bit integer variant is implemented.</para>
    </description>
    <status>Green</status>
    <predicated>False</predicated>
    <sm_policy>SM_1_only</sm_policy>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from 3 classes:</txt>
      <a href="#iclass_sme_vgx1_quad">One ZA quad-vector</a>
      <txt>, </txt>
      <a href="#iclass_sme_vgx2_quad">Two ZA quad-vectors</a>
      <txt> and </txt>
      <a href="#iclass_sme_vgx4_quad">Four ZA quad-vectors</a>
    </classesintro>
    <iclass name="One ZA quad-vector" oneof="3" id="iclass_sme_vgx1_quad" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="mortlach2" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="SMLALL" />
        <docvar key="sme-multireg" value="sme-vgx1-quad" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
      </arch_variants>
      <regdiagram form="32" psname="SMLALL-ZA.ZZV-1" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Zm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="2" name="Rv" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="12" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="5" name="Zn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" name="U" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" name="S" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="2" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="1" width="2" name="off2" usename="1">
          <c colspan="2"></c>
        </box>
      </regdiagram>
      <encoding name="smlall_za_zzv_1" oneofinclass="1" oneof="3" label="">
        <docvars>
          <docvar key="instr-class" value="mortlach2" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="SMLALL" />
          <docvar key="sme-multireg" value="sme-vgx1-quad" />
        </docvars>
        <asmtemplate><text>SMLALL  ZA.</text><a link="sa_t" hover="Size specifier (field &quot;sz&quot;) [D,S]">&lt;T&gt;</a><text>[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field &quot;Rv&quot;)">&lt;Wv&gt;</a><text>, </text><a link="sa_offsf" hover="Vector select offset, pointing to first of four consecutive vectors, encoded as &quot;off2&quot; field times 4 (field off2)">&lt;offsf&gt;</a><text>:</text><a link="sa_offsl" hover="Vector select offset, pointing to last of four consecutive vectors, encoded as &quot;off2&quot; field times 4 plus 3 (field off2)">&lt;offsl&gt;</a><text>], </text><a link="sa_zn" hover="First source scalable vector register (field &quot;Zn&quot;)">&lt;Zn&gt;</a><text>.</text><a link="sa_tb" hover="Size specifier (field &quot;sz&quot;) [B,H]">&lt;Tb&gt;</a><text>, </text><a link="sa_zm" hover="Second source scalable vector register Z0-Z15 (field &quot;Zm&quot;)">&lt;Zm&gt;</a><text>.</text><a link="sa_tb" hover="Size specifier (field &quot;sz&quot;) [B,H]">&lt;Tb&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="SMLALL-ZA.ZZV-1" mylink="SMLALL-ZA.ZZV-1" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
if sz == '1' &amp;&amp; !<a link="impl-aarch64.HaveSMEI16I64.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEI16I64()">HaveSMEI16I64</a>() then UNDEFINED;
constant integer esize = 32 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(off2:'00');
constant integer nreg = 1;</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="Two ZA quad-vectors" oneof="3" id="iclass_sme_vgx2_quad" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="mortlach2" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="SMLALL" />
        <docvar key="sme-multireg" value="sme-vgx2-quad" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
      </arch_variants>
      <regdiagram form="32" psname="SMLALL-ZA.ZZV-2x1" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Zm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="2" name="Rv" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="12" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Zn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" name="U" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" name="S" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="2" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="0" name="o1" usename="1">
          <c></c>
        </box>
      </regdiagram>
      <encoding name="smlall_za_zzv_2x1" oneofinclass="1" oneof="3" label="">
        <docvars>
          <docvar key="instr-class" value="mortlach2" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="SMLALL" />
          <docvar key="sme-multireg" value="sme-vgx2-quad" />
        </docvars>
        <asmtemplate><text>SMLALL  ZA.</text><a link="sa_t" hover="Size specifier (field &quot;sz&quot;) [D,S]">&lt;T&gt;</a><text>[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field &quot;Rv&quot;)">&lt;Wv&gt;</a><text>, </text><a link="sa_offsf_1" hover="Vector select offset, pointing to first of four consecutive vectors, encoded as &quot;o1&quot; field times 4 (field o1)">&lt;offsf&gt;</a><text>:</text><a link="sa_offsl_1" hover="Vector select offset, pointing to last of four consecutive vectors, encoded as &quot;o1&quot; field times 4 plus 3 (field o1)">&lt;offsl&gt;</a><a>{, VGx2}</a><text>], </text><text>{</text><text> </text><a link="sa_zn1" hover="First scalable vector register of a multi-vector sequence, encoded as &quot;Zn&quot; (field Zn)">&lt;Zn1&gt;</a><text>.</text><a link="sa_tb" hover="Size specifier (field &quot;sz&quot;) [B,H]">&lt;Tb&gt;</a><text>-</text><a link="sa_zn2" hover="Second scalable vector register of a multi-vector sequence (field Zn)">&lt;Zn2&gt;</a><text>.</text><a link="sa_tb" hover="Size specifier (field &quot;sz&quot;) [B,H]">&lt;Tb&gt;</a><text> </text><text>}</text><text>, </text><a link="sa_zm" hover="Second source scalable vector register Z0-Z15 (field &quot;Zm&quot;)">&lt;Zm&gt;</a><text>.</text><a link="sa_tb" hover="Size specifier (field &quot;sz&quot;) [B,H]">&lt;Tb&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="SMLALL-ZA.ZZV-2x1" mylink="SMLALL-ZA.ZZV-2x1" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
if sz == '1' &amp;&amp; !<a link="impl-aarch64.HaveSMEI16I64.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEI16I64()">HaveSMEI16I64</a>() then UNDEFINED;
constant integer esize = 32 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(o1:'00');
constant integer nreg = 2;</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="Four ZA quad-vectors" oneof="3" id="iclass_sme_vgx4_quad" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="mortlach2" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="SMLALL" />
        <docvar key="sme-multireg" value="sme-vgx4-quad" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
      </arch_variants>
      <regdiagram form="32" psname="SMLALL-ZA.ZZV-4x1" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Zm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="2" name="Rv" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="12" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Zn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" name="U" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" name="S" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="2" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="0" name="o1" usename="1">
          <c></c>
        </box>
      </regdiagram>
      <encoding name="smlall_za_zzv_4x1" oneofinclass="1" oneof="3" label="">
        <docvars>
          <docvar key="instr-class" value="mortlach2" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="SMLALL" />
          <docvar key="sme-multireg" value="sme-vgx4-quad" />
        </docvars>
        <asmtemplate><text>SMLALL  ZA.</text><a link="sa_t" hover="Size specifier (field &quot;sz&quot;) [D,S]">&lt;T&gt;</a><text>[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field &quot;Rv&quot;)">&lt;Wv&gt;</a><text>, </text><a link="sa_offsf_1" hover="Vector select offset, pointing to first of four consecutive vectors, encoded as &quot;o1&quot; field times 4 (field o1)">&lt;offsf&gt;</a><text>:</text><a link="sa_offsl_1" hover="Vector select offset, pointing to last of four consecutive vectors, encoded as &quot;o1&quot; field times 4 plus 3 (field o1)">&lt;offsl&gt;</a><a>{, VGx4}</a><text>], </text><text>{</text><text> </text><a link="sa_zn1" hover="First scalable vector register of a multi-vector sequence, encoded as &quot;Zn&quot; (field Zn)">&lt;Zn1&gt;</a><text>.</text><a link="sa_tb" hover="Size specifier (field &quot;sz&quot;) [B,H]">&lt;Tb&gt;</a><text>-</text><a link="sa_zn4" hover="Fourth scalable vector register of a multi-vector sequence (field Zn)">&lt;Zn4&gt;</a><text>.</text><a link="sa_tb" hover="Size specifier (field &quot;sz&quot;) [B,H]">&lt;Tb&gt;</a><text> </text><text>}</text><text>, </text><a link="sa_zm" hover="Second source scalable vector register Z0-Z15 (field &quot;Zm&quot;)">&lt;Zm&gt;</a><text>.</text><a link="sa_tb" hover="Size specifier (field &quot;sz&quot;) [B,H]">&lt;Tb&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="SMLALL-ZA.ZZV-4x1" mylink="SMLALL-ZA.ZZV-4x1" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
if sz == '1' &amp;&amp; !<a link="impl-aarch64.HaveSMEI16I64.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEI16I64()">HaveSMEI16I64</a>() then UNDEFINED;
constant integer esize = 32 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(o1:'00');
constant integer nreg = 4;</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="smlall_za_zzv_1, smlall_za_zzv_2x1, smlall_za_zzv_4x1" symboldefcount="1">
      <symbol link="sa_t">&lt;T&gt;</symbol>
      <definition encodedin="sz">
        <intro>Is the size specifier, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;T&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">S</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">D</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="smlall_za_zzv_1, smlall_za_zzv_2x1, smlall_za_zzv_4x1" symboldefcount="1">
      <symbol link="sa_wv">&lt;Wv&gt;</symbol>
      <account encodedin="Rv">
        <intro>
          <para>Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="smlall_za_zzv_1" symboldefcount="1">
      <symbol link="sa_offsf">&lt;offsf&gt;</symbol>
      <account encodedin="off2">
        <docvars>
          <docvar key="sme-multireg" value="sme-vgx1-quad" />
        </docvars>
        <intro>
          <para>For the one ZA quad-vector variant: is the vector select offset, pointing to first of four consecutive vectors, encoded as "off2" field times 4.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="smlall_za_zzv_2x1, smlall_za_zzv_4x1" symboldefcount="2">
      <symbol link="sa_offsf_1">&lt;offsf&gt;</symbol>
      <account encodedin="o1">
        <intro>
          <para>For the four ZA quad-vectors and two ZA quad-vectors variant: is the vector select offset, pointing to first of four consecutive vectors, encoded as "o1" field times 4.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="smlall_za_zzv_1" symboldefcount="1">
      <symbol link="sa_offsl">&lt;offsl&gt;</symbol>
      <account encodedin="off2">
        <docvars>
          <docvar key="sme-multireg" value="sme-vgx1-quad" />
        </docvars>
        <intro>
          <para>For the one ZA quad-vector variant: is the vector select offset, pointing to last of four consecutive vectors, encoded as "off2" field times 4 plus 3.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="smlall_za_zzv_2x1, smlall_za_zzv_4x1" symboldefcount="2">
      <symbol link="sa_offsl_1">&lt;offsl&gt;</symbol>
      <account encodedin="o1">
        <intro>
          <para>For the four ZA quad-vectors and two ZA quad-vectors variant: is the vector select offset, pointing to last of four consecutive vectors, encoded as "o1" field times 4 plus 3.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="smlall_za_zzv_1" symboldefcount="1">
      <symbol link="sa_zn">&lt;Zn&gt;</symbol>
      <account encodedin="Zn">
        <intro>
          <para>Is the name of the first source scalable vector register, encoded in the "Zn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="smlall_za_zzv_2x1, smlall_za_zzv_4x1" symboldefcount="1">
      <symbol link="sa_zn1">&lt;Zn1&gt;</symbol>
      <account encodedin="Zn">
        <intro>
          <para>Is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zn".</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="smlall_za_zzv_1, smlall_za_zzv_2x1, smlall_za_zzv_4x1" symboldefcount="1">
      <symbol link="sa_tb">&lt;Tb&gt;</symbol>
      <definition encodedin="sz">
        <intro>Is the size specifier, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;Tb&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">B</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">H</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="smlall_za_zzv_4x1" symboldefcount="1">
      <symbol link="sa_zn4">&lt;Zn4&gt;</symbol>
      <account encodedin="Zn">
        <intro>
          <para>Is the name of the fourth scalable vector register of a multi-vector sequence, encoded as "Zn" plus 3 modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="smlall_za_zzv_2x1" symboldefcount="1">
      <symbol link="sa_zn2">&lt;Zn2&gt;</symbol>
      <account encodedin="Zn">
        <intro>
          <para>Is the name of the second scalable vector register of a multi-vector sequence, encoded as "Zn" plus 1 modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="smlall_za_zzv_1, smlall_za_zzv_2x1, smlall_za_zzv_4x1" symboldefcount="1">
      <symbol link="sa_zm">&lt;Zm&gt;</symbol>
      <account encodedin="Zm">
        <intro>
          <para>Is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="SMLALL-ZA.ZZV-1" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckStreamingSVEAndZAEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEAndZAEnabled()">CheckStreamingSVEAndZAEnabled</a>();
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
constant integer elements = VL DIV esize;
integer vectors = VL DIV 8;
integer vstride = vectors DIV nreg;
bits(32) vbase = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[v, 32];
integer vec = (<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(vbase) + offset) MOD vstride;
bits(VL) result;
vec = vec - (vec MOD 4);

for r = 0 to nreg-1
    bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[(n+r) MOD 32, VL];
    bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
    for i = 0 to 3
        bits(VL) operand3 = <a link="impl-aarch64.ZAvector.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) ZAvector[integer index, integer width]">ZAvector</a>[vec + i, VL];
        for e = 0 to elements-1
            integer element1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 4 * e + i, esize DIV 4]);
            integer element2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 4 * e + i, esize DIV 4]);
            bits(esize) product = (element1 * element2)&lt;esize-1:0&gt;;
            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
        <a link="impl-aarch64.ZAvector.write.2" file="shared_pseudocode.xml" hover="accessor: ZAvector[integer index, integer width] = bits(width) value">ZAvector</a>[vec + i, VL] = result;
    vec = vec + vstride;</pstext>
    </ps>
  </ps_section>
</instructionsection>
