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<instructionsection id="svdot_za_zzi" title="SVDOT (4-way)" type="instruction">
  <docvars>
    <docvar key="instr-class" value="mortlach2" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="SVDOT" />
  </docvars>
  <heading>SVDOT (4-way)</heading>
  <desc>
    <brief>Multi-vector signed integer vertical dot-product by indexed element</brief>
    <description>
      <para>The instruction operates on four ZA single-vector groups.</para>
      <para>The signed integer vertical dot product instruction computes the vertical dot product of the corresponding four signed 8-bit or 16-bit integer values held in the four first source vectors and four signed 8-bit or 16-bit integer values in the corresponding indexed 32-bit or 64-bit element of the second source vector. The widened dot product results are destructively added to the corresponding 32-bit or 64-bit element of the four ZA single-vector groups.</para>
      <para>The groups within the second source vector are specified using an immediate element index which selects the same group position within each 128-bit vector segment. The index range is from 0 to one less than the number of groups per 128-bit segment, encoded in 1 to 2 bits depending on the size of the group.</para>
      <para>The vector numbers forming the single-vector group within each quarter of the ZA array are selected by the sum of the vector select register and immediate offset, modulo quarter the number of ZA array vectors.</para>
      <para>The <arm-defined-word>vector group</arm-defined-word> symbol <syntax>VGx4</syntax> indicates that the ZA operand consists of four ZA single-vector groups. The <arm-defined-word>vector group</arm-defined-word> symbol is preferred for disassembly, but optional in assembler source code.</para>
      <para>This instruction is unpredicated.</para>
      <para>ID_AA64SMFR0_EL1.I16I64 indicates whether the 16-bit integer variant is implemented.</para>
    </description>
    <status>Green</status>
    <predicated>False</predicated>
    <sm_policy>SM_1_only</sm_policy>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from 2 classes:</txt>
      <a href="#iclass_per_word">32-bit</a>
      <txt> and </txt>
      <a href="#iclass_per_doubleword">64-bit</a>
    </classesintro>
    <iclass name="32-bit" oneof="2" id="iclass_per_word" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="asimdimm-datatype" value="per-word" />
        <docvar key="instr-class" value="mortlach2" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="SVDOT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
      </arch_variants>
      <regdiagram form="32" psname="SVDOT-ZA.ZZi-S4xi" tworows="1">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Zm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>1</c>
        </box>
        <box hibit="14" width="2" name="Rv" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="12" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" width="2" name="i2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="9" width="3" name="Zn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" name="U" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" settings="1">
          <c>0</c>
        </box>
        <box hibit="2" width="3" name="off3" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="svdot_za_zzi_s4xi" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="asimdimm-datatype" value="per-word" />
          <docvar key="instr-class" value="mortlach2" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="SVDOT" />
        </docvars>
        <asmtemplate><text>SVDOT   ZA.S[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field &quot;Rv&quot;)">&lt;Wv&gt;</a><text>, </text><a link="sa_offs" hover="Vector select offset [0-7] (field &quot;off3&quot;)">&lt;offs&gt;</a><a>{, VGx4}</a><text>], </text><text>{</text><text> </text><a link="sa_zn1" hover="First scalable vector register of a multi-vector sequence (field Zn)">&lt;Zn1&gt;</a><text>.B-</text><a link="sa_zn4" hover="Fourth scalable vector register of a multi-vector sequence (field Zn)">&lt;Zn4&gt;</a><text>.B </text><text>}</text><text>, </text><a link="sa_zm" hover="Second source scalable vector register Z0-Z15 (field &quot;Zm&quot;)">&lt;Zm&gt;</a><text>.B[</text><a link="sa_index_1" hover="Element index [0-3] (field &quot;i2&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="SVDOT-ZA.ZZi-S4xi" mylink="SVDOT-ZA.ZZi-S4xi" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
constant integer esize = 32;
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn:'00');
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(off3);
integer index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(i2);</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="64-bit" oneof="2" id="iclass_per_doubleword" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="asimdimm-datatype" value="per-doubleword" />
        <docvar key="instr-class" value="mortlach2" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="SVDOT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="FEAT_SME_I16I64" feature="FEAT_SME_I16I64" />
      </arch_variants>
      <regdiagram form="32" psname="SVDOT-ZA.ZZi-D4xi" tworows="1">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Zm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>1</c>
        </box>
        <box hibit="14" width="2" name="Rv" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="i1" usename="1">
          <c></c>
        </box>
        <box hibit="9" width="3" name="Zn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="6" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" name="U" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" settings="1">
          <c>1</c>
        </box>
        <box hibit="2" width="3" name="off3" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="svdot_za_zzi_d4xi" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="asimdimm-datatype" value="per-doubleword" />
          <docvar key="instr-class" value="mortlach2" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="SVDOT" />
        </docvars>
        <asmtemplate><text>SVDOT   ZA.D[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field &quot;Rv&quot;)">&lt;Wv&gt;</a><text>, </text><a link="sa_offs" hover="Vector select offset [0-7] (field &quot;off3&quot;)">&lt;offs&gt;</a><a>{, VGx4}</a><text>], </text><text>{</text><text> </text><a link="sa_zn1" hover="First scalable vector register of a multi-vector sequence (field Zn)">&lt;Zn1&gt;</a><text>.H-</text><a link="sa_zn4" hover="Fourth scalable vector register of a multi-vector sequence (field Zn)">&lt;Zn4&gt;</a><text>.H </text><text>}</text><text>, </text><a link="sa_zm" hover="Second source scalable vector register Z0-Z15 (field &quot;Zm&quot;)">&lt;Zm&gt;</a><text>.H[</text><a link="sa_index" hover="Element index [0-1] (field &quot;i1&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="SVDOT-ZA.ZZi-D4xi" mylink="SVDOT-ZA.ZZi-D4xi" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !(<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() &amp;&amp; <a link="impl-aarch64.HaveSMEI16I64.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEI16I64()">HaveSMEI16I64</a>()) then UNDEFINED;
integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
constant integer esize = 64;
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn:'00');
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(off3);
integer index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(i1);</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="svdot_za_zzi_d4xi, svdot_za_zzi_s4xi" symboldefcount="1">
      <symbol link="sa_wv">&lt;Wv&gt;</symbol>
      <account encodedin="Rv">
        <intro>
          <para>Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="svdot_za_zzi_d4xi, svdot_za_zzi_s4xi" symboldefcount="1">
      <symbol link="sa_offs">&lt;offs&gt;</symbol>
      <account encodedin="off3">
        <intro>
          <para>Is the vector select offset, in the range 0 to 7, encoded in the "off3" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="svdot_za_zzi_d4xi, svdot_za_zzi_s4xi" symboldefcount="1">
      <symbol link="sa_zn1">&lt;Zn1&gt;</symbol>
      <account encodedin="Zn">
        <intro>
          <para>Is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zn" times 4.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="svdot_za_zzi_d4xi, svdot_za_zzi_s4xi" symboldefcount="1">
      <symbol link="sa_zn4">&lt;Zn4&gt;</symbol>
      <account encodedin="Zn">
        <intro>
          <para>Is the name of the fourth scalable vector register of a multi-vector sequence, encoded as "Zn" times 4 plus 3.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="svdot_za_zzi_d4xi, svdot_za_zzi_s4xi" symboldefcount="1">
      <symbol link="sa_zm">&lt;Zm&gt;</symbol>
      <account encodedin="Zm">
        <intro>
          <para>Is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="svdot_za_zzi_s4xi" symboldefcount="1">
      <symbol link="sa_index_1">&lt;index&gt;</symbol>
      <account encodedin="i2">
        <docvars>
          <docvar key="asimdimm-datatype" value="per-word" />
        </docvars>
        <intro>
          <para>For the 32-bit variant: is the element index, in the range 0 to 3, encoded in the "i2" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="svdot_za_zzi_d4xi" symboldefcount="2">
      <symbol link="sa_index">&lt;index&gt;</symbol>
      <account encodedin="i1">
        <docvars>
          <docvar key="asimdimm-datatype" value="per-doubleword" />
        </docvars>
        <intro>
          <para>For the 64-bit variant: is the element index, in the range 0 to 1, encoded in the "i1" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="SVDOT-ZA.ZZi-S4xi" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckStreamingSVEAndZAEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEAndZAEnabled()">CheckStreamingSVEAndZAEnabled</a>();
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
constant integer elements = VL DIV esize;
integer vectors = VL DIV 8;
integer vstride = vectors DIV 4;
integer eltspersegment = 128 DIV esize;
bits(32) vbase = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[v, 32];
integer vec = (<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(vbase) + offset) MOD vstride;
bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
bits(VL) result;

for r = 0 to 3
    bits(VL) operand3 = <a link="impl-aarch64.ZAvector.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) ZAvector[integer index, integer width]">ZAvector</a>[vec, VL];
    for e = 0 to elements-1
        integer segmentbase = e - (e MOD eltspersegment);
        integer s = segmentbase + index;
        bits(esize) sum = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize];
        for i = 0 to 3
            bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n+i, VL];
            integer element1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 4 * e + r, esize DIV 4]);
            integer element2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 4 * s + i, esize DIV 4]);
            sum = sum + element1 * element2;
        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum;
    <a link="impl-aarch64.ZAvector.write.2" file="shared_pseudocode.xml" hover="accessor: ZAvector[integer index, integer width] = bits(width) value">ZAvector</a>[vec, VL] = result;
    vec = vec + vstride;</pstext>
    </ps>
  </ps_section>
</instructionsection>
