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<instructionsection id="FMSUB_float" title="FMSUB -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="float" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="FMSUB" />
  </docvars>
  <heading>FMSUB</heading>
  <desc>
    <brief>
      <para>Floating-point Fused Multiply-Subtract (scalar)</para>
    </brief>
    <authored>
      <para>Floating-point Fused Multiply-Subtract (scalar). This instruction multiplies the values of the first two SIMD&amp;FP source registers, negates the product, adds that to the value of the third SIMD&amp;FP source register, and writes the result to the SIMD&amp;FP destination register.</para>
      <para>A floating-point exception can be generated by this instruction. Depending on the settings in <xref linkend="AArch64.fpcr">FPCR</xref>, the exception results in either a flag being set in <xref linkend="AArch64.fpsr">FPSR</xref>, or a synchronous exception being generated. For more information, see <xref linkend="BEIJDDAG">Floating-point exception traps</xref>.</para>
      <para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="Floating-point" oneof="1" id="iclass_float" no_encodings="3" isa="A64">
      <docvars>
        <docvar key="instr-class" value="float" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="FMSUB" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch64/instrs/float/arithmetic/mul/add-sub" tworows="1">
        <box hibit="31" name="M" settings="1">
          <c>0</c>
        </box>
        <box hibit="30" settings="1">
          <c>0</c>
        </box>
        <box hibit="29" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="28" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="23" width="2" name="ftype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="21" name="o1" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="20" width="5" name="Rm" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" name="o0" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="14" width="5" name="Ra" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="FMSUB_H_floatdp3" oneofinclass="3" oneof="3" label="Half-precision" bitdiffs="ftype == 11">
        <docvars>
          <docvar key="datatype" value="half" />
          <docvar key="instr-class" value="float" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FMSUB" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="23" width="2" name="ftype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>FMSUB  </text><a link="sa_hd" hover="16-bit SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Hd&gt;</a><text>, </text><a link="sa_hn" hover="First 16-bit SIMD&amp;FP source register holding multiplicand (field &quot;Rn&quot;)">&lt;Hn&gt;</a><text>, </text><a link="sa_hm" hover="Second 16-bit SIMD&amp;FP source register holding multiplier (field &quot;Rm&quot;)">&lt;Hm&gt;</a><text>, </text><a link="sa_ha" hover="Third 16-bit SIMD&amp;FP source register holding minuend (field &quot;Ra&quot;)">&lt;Ha&gt;</a></asmtemplate>
      </encoding>
      <encoding name="FMSUB_S_floatdp3" oneofinclass="3" oneof="3" label="Single-precision" bitdiffs="ftype == 00">
        <docvars>
          <docvar key="datatype" value="single" />
          <docvar key="instr-class" value="float" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FMSUB" />
        </docvars>
        <box hibit="23" width="2" name="ftype">
          <c>0</c>
          <c>0</c>
        </box>
        <asmtemplate><text>FMSUB  </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register holding multiplicand (field &quot;Rn&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register holding multiplier (field &quot;Rm&quot;)">&lt;Sm&gt;</a><text>, </text><a link="sa_sa" hover="Third 32-bit SIMD&amp;FP source register holding minuend (field &quot;Ra&quot;)">&lt;Sa&gt;</a></asmtemplate>
      </encoding>
      <encoding name="FMSUB_D_floatdp3" oneofinclass="3" oneof="3" label="Double-precision" bitdiffs="ftype == 01">
        <docvars>
          <docvar key="datatype" value="double" />
          <docvar key="instr-class" value="float" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FMSUB" />
        </docvars>
        <box hibit="23" width="2" name="ftype">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>FMSUB  </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register holding multiplicand (field &quot;Rn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register holding multiplier (field &quot;Rm&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_da" hover="Third 64-bit SIMD&amp;FP source register holding minuend (field &quot;Ra&quot;)">&lt;Da&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/float/arithmetic/mul/add-sub" mylink="aarch64.instrs.float.arithmetic.mul.add-sub" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Ra);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);

integer esize;
case ftype of
    when '00' esize = 32;
    when '01' esize = 64;
    when '10' UNDEFINED;
    when '11'
        if <a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then
            esize = 16;
        else
            UNDEFINED;

boolean opa_neg = (o1 == '1');
boolean op1_neg = (o0 != o1);</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="FMSUB_D_floatdp3" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMSUB_D_floatdp3" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register holding the multiplicand, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMSUB_D_floatdp3" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register holding the multiplier, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMSUB_D_floatdp3" symboldefcount="1">
      <symbol link="sa_da">&lt;Da&gt;</symbol>
      <account encodedin="Ra">
        <intro>
          <para>Is the 64-bit name of the third SIMD&amp;FP source register holding the minuend, encoded in the "Ra" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMSUB_H_floatdp3" symboldefcount="1">
      <symbol link="sa_hd">&lt;Hd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 16-bit name of the SIMD&amp;FP destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMSUB_H_floatdp3" symboldefcount="1">
      <symbol link="sa_hn">&lt;Hn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 16-bit name of the first SIMD&amp;FP source register holding the multiplicand, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMSUB_H_floatdp3" symboldefcount="1">
      <symbol link="sa_hm">&lt;Hm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 16-bit name of the second SIMD&amp;FP source register holding the multiplier, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMSUB_H_floatdp3" symboldefcount="1">
      <symbol link="sa_ha">&lt;Ha&gt;</symbol>
      <account encodedin="Ra">
        <intro>
          <para>Is the 16-bit name of the third SIMD&amp;FP source register holding the minuend, encoded in the "Ra" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMSUB_S_floatdp3" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMSUB_S_floatdp3" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 32-bit name of the first SIMD&amp;FP source register holding the multiplicand, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMSUB_S_floatdp3" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP source register holding the multiplier, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMSUB_S_floatdp3" symboldefcount="1">
      <symbol link="sa_sa">&lt;Sa&gt;</symbol>
      <account encodedin="Ra">
        <intro>
          <para>Is the 32-bit name of the third SIMD&amp;FP source register holding the minuend, encoded in the "Ra" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/float/arithmetic/mul/add-sub" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPEnabled64()">CheckFPEnabled64</a>();

bits(esize) operanda = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[a, esize];
bits(esize) operand1 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, esize];
bits(esize) operand2 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[m, esize];

<a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = FPCR[];
boolean merge    = <a link="impl-shared.IsMerging.1" file="shared_pseudocode.xml" hover="function: boolean IsMerging(FPCRType fpcr)">IsMerging</a>(fpcr);
bits(128) result = if merge then <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[a, 128] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(128);

if opa_neg then operanda = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(operanda);
if op1_neg then operand1 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(operand1);
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 0, esize] = <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(operanda, operand1, operand2, fpcr);

<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = result;</pstext>
    </ps>
  </ps_section>
</instructionsection>
