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<instructionsection id="SLI_advsimd" title="SLI -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="advsimd" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="SLI" />
  </docvars>
  <heading>SLI</heading>
  <desc>
    <brief>
      <para>Shift Left and Insert (immediate)</para>
    </brief>
    <authored>
      <para>Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.</para>
      <para><image file="A64.sli_operation_shift_by_3.svg" label="shift left by 3 for an 8-bit vector element"></image></para>
      <para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If PSTATE.DIT is 1:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from 2 classes:</txt>
      <a href="#iclass_sisd">Scalar</a>
      <txt> and </txt>
      <a href="#iclass_simd">Vector</a>
    </classesintro>
    <iclass name="Scalar" oneof="2" id="iclass_sisd" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="advsimd-type" value="sisd" />
        <docvar key="instr-class" value="advsimd" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="SLI" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch64/instrs/vector/shift/left-insert/sisd" tworows="1">
        <box hibit="31" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="29" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="28" width="6" settings="6">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="4" name="immh" usename="1" settings="4" constraint="!= 0000" psbits="xxxx">
          <c colspan="4">!= 0000</c>
        </box>
        <box hibit="18" width="3" name="immb" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="5" name="opcode" settings="5">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="10" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="SLI_asisdshf_R" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="advsimd-type" value="sisd" />
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="SLI" />
        </docvars>
        <asmtemplate><text>SLI  </text><a link="sa_v" hover="Width specifier (field &quot;immh&quot;) [D]">&lt;V&gt;</a><a link="sa_d" hover="SIMD&amp;FP destination register number (field &quot;Rd&quot;)">&lt;d&gt;</a><text>, </text><a link="sa_v" hover="Width specifier (field &quot;immh&quot;) [D]">&lt;V&gt;</a><a link="sa_n" hover="First SIMD&amp;FP source register number (field &quot;Rn&quot;)">&lt;n&gt;</a><text>, #</text><a link="sa_shift_1" hover="Left shift amount [0-63] (field &quot;immh:immb&quot;) [(UInt(immh:immb)-64)]">&lt;shift&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/vector/shift/left-insert/sisd" mylink="aarch64.instrs.vector.shift.left-insert.sisd" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);

if immh&lt;3&gt; != '1' then UNDEFINED;
integer esize = 8 &lt;&lt; 3;
integer datasize = esize;
integer elements = 1;

integer shift = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(immh:immb) - esize;</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="Vector" oneof="2" id="iclass_simd" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="advsimd-type" value="simd" />
        <docvar key="instr-class" value="advsimd" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="SLI" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch64/instrs/vector/shift/left-insert/simd" tworows="1">
        <box hibit="31" settings="1">
          <c>0</c>
        </box>
        <box hibit="30" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="29" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="28" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="4" name="immh" usename="1" settings="4" constraint="!= 0000">
          <c colspan="4">!= 0000</c>
        </box>
        <box hibit="18" width="3" name="immb" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="5" name="opcode" settings="5">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="10" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="SLI_asimdshf_R" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="advsimd-type" value="simd" />
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="SLI" />
        </docvars>
        <asmtemplate><text>SLI  </text><a link="sa_vd" hover="SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Vd&gt;</a><text>.</text><a link="sa_t" hover="Arrangement specifier (field &quot;immh:Q&quot;) [2D,2S,4H,4S,8B,8H,16B,SEE(asimdimm)]">&lt;T&gt;</a><text>, </text><a link="sa_vn" hover="SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Vn&gt;</a><text>.</text><a link="sa_t" hover="Arrangement specifier (field &quot;immh:Q&quot;) [2D,2S,4H,4S,8B,8H,16B,SEE(asimdimm)]">&lt;T&gt;</a><text>, #</text><a link="sa_shift" hover="Left shift amount [0-the element width in bits minus 1] (field &quot;immh:immb&quot;) [(UInt(immh:immb)-8),(UInt(immh:immb)-16),(UInt(immh:immb)-32),(UInt(immh:immb)-64),SEE(asimdimm)]">&lt;shift&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/vector/shift/left-insert/simd" mylink="aarch64.instrs.vector.shift.left-insert.simd" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);

if immh == '0000' then <a link="asimdimm" file="encodingindex.xml" hover="handled by an instruction in the 'Advanced SIMD modified immediate' class">SEE(asimdimm)</a>;
if immh&lt;3&gt;:Q == '10' then UNDEFINED;
integer esize = 8 &lt;&lt; <a link="impl-shared.HighestSetBit.1" file="shared_pseudocode.xml" hover="function: integer HighestSetBit(bits(N) x)">HighestSetBit</a>(immh);
integer datasize = if Q == '1' then 128 else 64;
integer elements = datasize DIV esize;

integer shift = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(immh:immb) - esize;</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SLI_asisdshf_R" symboldefcount="1">
      <symbol link="sa_v">&lt;V&gt;</symbol>
      <definition encodedin="immh">
        <intro>Is a width specifier, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">immh</entry>
                <entry class="symbol">&lt;V&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0xxx</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">1xxx</entry>
                <entry class="symbol">D</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="SLI_asisdshf_R" symboldefcount="1">
      <symbol link="sa_d">&lt;d&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the number of the SIMD&amp;FP destination register, in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SLI_asisdshf_R" symboldefcount="1">
      <symbol link="sa_n">&lt;n&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the number of the first SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SLI_asimdshf_R" symboldefcount="1">
      <symbol link="sa_vd">&lt;Vd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the name of the SIMD&amp;FP destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SLI_asimdshf_R" symboldefcount="1">
      <symbol link="sa_t">&lt;T&gt;</symbol>
      <definition encodedin="immh:Q">
        <intro>Is an arrangement specifier, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">immh</entry>
                <entry class="bitfield">Q</entry>
                <entry class="symbol">&lt;T&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0000</entry>
                <entry class="bitfield">x</entry>
                <entry class="symbol" iclasslink="asimdimm" iclasslinkfile="encodingindex.xml">SEE Advanced SIMD modified immediate</entry>
              </row>
              <row>
                <entry class="bitfield">0001</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">8B</entry>
              </row>
              <row>
                <entry class="bitfield">0001</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">16B</entry>
              </row>
              <row>
                <entry class="bitfield">001x</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">4H</entry>
              </row>
              <row>
                <entry class="bitfield">001x</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">8H</entry>
              </row>
              <row>
                <entry class="bitfield">01xx</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">2S</entry>
              </row>
              <row>
                <entry class="bitfield">01xx</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">4S</entry>
              </row>
              <row>
                <entry class="bitfield">1xxx</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">1xxx</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">2D</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="SLI_asimdshf_R" symboldefcount="1">
      <symbol link="sa_vn">&lt;Vn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the name of the SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SLI_asisdshf_R" symboldefcount="1">
      <symbol link="sa_shift_1">&lt;shift&gt;</symbol>
      <definition encodedin="immh:immb">
        <intro>For the scalar variant: is the left shift amount, in the range 0 to 63, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">immh</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0xxx</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">1xxx</entry>
                <entry class="symbol">(UInt(immh:immb)-64)</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="SLI_asimdshf_R" symboldefcount="2">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="immh:immb">
        <intro>For the vector variant: is the left shift amount, in the range 0 to the element width in bits minus 1, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">immh</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0000</entry>
                <entry class="symbol" iclasslink="asimdimm" iclasslinkfile="encodingindex.xml">SEE Advanced SIMD modified immediate</entry>
              </row>
              <row>
                <entry class="bitfield">0001</entry>
                <entry class="symbol">(UInt(immh:immb)-8)</entry>
              </row>
              <row>
                <entry class="bitfield">001x</entry>
                <entry class="symbol">(UInt(immh:immb)-16)</entry>
              </row>
              <row>
                <entry class="bitfield">01xx</entry>
                <entry class="symbol">(UInt(immh:immb)-32)</entry>
              </row>
              <row>
                <entry class="bitfield">1xxx</entry>
                <entry class="symbol">(UInt(immh:immb)-64)</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/vector/shift/left-insert/sisd" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
bits(datasize) operand  = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, datasize];
bits(datasize) operand2 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[d, datasize];
bits(datasize) result;
bits(esize) mask = <a link="impl-shared.LSL.2" file="shared_pseudocode.xml" hover="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
bits(esize) shifted;

for e = 0 to elements-1
    shifted = <a link="impl-shared.LSL.2" file="shared_pseudocode.xml" hover="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, datasize] = result;</pstext>
    </ps>
  </ps_section>
</instructionsection>
