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<instructionsection id="FCMP_float" title="FCMP -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="float" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="FCMP" />
  </docvars>
  <heading>FCMP</heading>
  <desc>
    <brief>
      <para>Floating-point quiet Compare (scalar)</para>
    </brief>
    <authored>
      <para>Floating-point quiet Compare (scalar). This instruction compares the two SIMD&amp;FP source register values, or the first SIMD&amp;FP source register value and zero. It writes the result to the <xref linkend="BEIDIGBH">PSTATE</xref>.{N, Z, C, V} flags.</para>
      <para>This instruction raises an Invalid Operation floating-point exception if either or both of the operands is a signaling NaN.</para>
      <para>A floating-point exception can be generated by this instruction. Depending on the settings in <xref linkend="AArch64.fpcr">FPCR</xref>, the exception results in either a flag being set in <xref linkend="AArch64.fpsr">FPSR</xref>, or a synchronous exception being generated. For more information, see <xref linkend="BEIJDDAG">Floating-point exception traps</xref>.</para>
      <para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
    </authored>
    <affected_by_sme output="NZCV condition flags" />
  </desc>
  <operationalnotes>
    <para>The IEEE 754 standard specifies that the result of a comparison is precisely one of &lt;, ==, &gt; or unordered.  If either or both of the operands is a NaN, they are unordered, and all three of (Operand1 &lt; Operand2), (Operand1 == Operand2) and (Operand1 &gt; Operand2) are false. An unordered comparison sets the <xref linkend="BEIDIGBH">PSTATE</xref> condition flags to N=0, Z=0, C=1, and V=1.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="Floating-point" oneof="1" id="iclass_float" no_encodings="6" isa="A64">
      <docvars>
        <docvar key="instr-class" value="float" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="FCMP" />
      </docvars>
      <iclassintro count="6"></iclassintro>
      <regdiagram form="32" psname="aarch64/instrs/float/compare/uncond" tworows="1">
        <box hibit="31" name="M" settings="1">
          <c>0</c>
        </box>
        <box hibit="30" settings="1">
          <c>0</c>
        </box>
        <box hibit="29" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="28" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="2" name="ftype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="5" name="Rm" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" width="2" name="op" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="13" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="2" name="opc" usename="1" settings="1" psbits="xx">
          <c>0</c>
          <c>x</c>
        </box>
        <box hibit="2" width="3" name="opcode2[2:0]" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="FCMP_H_floatcmp" oneofinclass="6" oneof="6" label="Half-precision" bitdiffs="ftype == 11 &amp;&amp; opc == 00">
        <docvars>
          <docvar key="compare-with" value="cmp-reg" />
          <docvar key="datatype" value="half" />
          <docvar key="instr-class" value="float" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FCMP" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="23" width="2" name="ftype">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" width="2" name="opc">
          <c></c>
          <c>0</c>
        </box>
        <asmtemplate><text>FCMP  </text><a link="sa_hn_1" hover="First 16-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Hn&gt;</a><text>, </text><a link="sa_hm" hover="Second 16-bit SIMD&amp;FP source register (field &quot;Rm&quot;)">&lt;Hm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="FCMP_HZ_floatcmp" oneofinclass="6" oneof="6" label="Half-precision, zero" bitdiffs="ftype == 11 &amp;&amp; Rm == (00000) &amp;&amp; opc == 01">
        <docvars>
          <docvar key="compare-with" value="cmp-zero" />
          <docvar key="datatype" value="half" />
          <docvar key="instr-class" value="float" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FCMP" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="23" width="2" name="ftype">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" width="5" name="Rm">
          <c>z</c>
          <c>z</c>
          <c>z</c>
          <c>z</c>
          <c>z</c>
        </box>
        <box hibit="4" width="2" name="opc">
          <c></c>
          <c>1</c>
        </box>
        <asmtemplate><text>FCMP  </text><a link="sa_hn" hover="16-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Hn&gt;</a><text>, #0.0</text></asmtemplate>
      </encoding>
      <encoding name="FCMP_S_floatcmp" oneofinclass="6" oneof="6" label="Single-precision" bitdiffs="ftype == 00 &amp;&amp; opc == 00">
        <docvars>
          <docvar key="compare-with" value="cmp-reg" />
          <docvar key="datatype" value="single" />
          <docvar key="instr-class" value="float" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FCMP" />
        </docvars>
        <box hibit="23" width="2" name="ftype">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" width="2" name="opc">
          <c></c>
          <c>0</c>
        </box>
        <asmtemplate><text>FCMP  </text><a link="sa_sn_1" hover="First 32-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Rm&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="FCMP_SZ_floatcmp" oneofinclass="6" oneof="6" label="Single-precision, zero" bitdiffs="ftype == 00 &amp;&amp; Rm == (00000) &amp;&amp; opc == 01">
        <docvars>
          <docvar key="compare-with" value="cmp-zero" />
          <docvar key="datatype" value="single" />
          <docvar key="instr-class" value="float" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FCMP" />
        </docvars>
        <box hibit="23" width="2" name="ftype">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" width="5" name="Rm">
          <c>z</c>
          <c>z</c>
          <c>z</c>
          <c>z</c>
          <c>z</c>
        </box>
        <box hibit="4" width="2" name="opc">
          <c></c>
          <c>1</c>
        </box>
        <asmtemplate><text>FCMP  </text><a link="sa_sn" hover="32-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Sn&gt;</a><text>, #0.0</text></asmtemplate>
      </encoding>
      <encoding name="FCMP_D_floatcmp" oneofinclass="6" oneof="6" label="Double-precision" bitdiffs="ftype == 01 &amp;&amp; opc == 00">
        <docvars>
          <docvar key="compare-with" value="cmp-reg" />
          <docvar key="datatype" value="double" />
          <docvar key="instr-class" value="float" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FCMP" />
        </docvars>
        <box hibit="23" width="2" name="ftype">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="4" width="2" name="opc">
          <c></c>
          <c>0</c>
        </box>
        <asmtemplate><text>FCMP  </text><a link="sa_dn_1" hover="First 64-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Rm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="FCMP_DZ_floatcmp" oneofinclass="6" oneof="6" label="Double-precision, zero" bitdiffs="ftype == 01 &amp;&amp; Rm == (00000) &amp;&amp; opc == 01">
        <docvars>
          <docvar key="compare-with" value="cmp-zero" />
          <docvar key="datatype" value="double" />
          <docvar key="instr-class" value="float" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FCMP" />
        </docvars>
        <box hibit="23" width="2" name="ftype">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" width="5" name="Rm">
          <c>z</c>
          <c>z</c>
          <c>z</c>
          <c>z</c>
          <c>z</c>
        </box>
        <box hibit="4" width="2" name="opc">
          <c></c>
          <c>1</c>
        </box>
        <asmtemplate><text>FCMP  </text><a link="sa_dn" hover="64-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Dn&gt;</a><text>, #0.0</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/float/compare/uncond" mylink="aarch64.instrs.float.compare.uncond" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);   // ignored when opc&lt;0&gt; == '1'

integer datasize;
case ftype of
    when '00' datasize = 32;
    when '01' datasize = 64;
    when '10' UNDEFINED;
    when '11'
        if <a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then
            datasize = 16;
        else
            UNDEFINED;

boolean signal_all_nans = (opc&lt;1&gt; == '1');
boolean cmp_with_zero = (opc&lt;0&gt; == '1');</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="FCMP_D_floatcmp" symboldefcount="1">
      <symbol link="sa_dn_1">&lt;Dn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="compare-with" value="cmp-reg" />
        </docvars>
        <intro>
          <para>For the double-precision variant: is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FCMP_DZ_floatcmp" symboldefcount="2">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="compare-with" value="cmp-zero" />
        </docvars>
        <intro>
          <para>For the double-precision, zero variant: is the 64-bit name of the SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FCMP_D_floatcmp" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FCMP_H_floatcmp" symboldefcount="1">
      <symbol link="sa_hn_1">&lt;Hn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="compare-with" value="cmp-reg" />
        </docvars>
        <intro>
          <para>For the half-precision variant: is the 16-bit name of the first SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FCMP_HZ_floatcmp" symboldefcount="2">
      <symbol link="sa_hn">&lt;Hn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="compare-with" value="cmp-zero" />
        </docvars>
        <intro>
          <para>For the half-precision, zero variant: is the 16-bit name of the SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FCMP_H_floatcmp" symboldefcount="1">
      <symbol link="sa_hm">&lt;Hm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 16-bit name of the second SIMD&amp;FP source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FCMP_S_floatcmp" symboldefcount="1">
      <symbol link="sa_sn_1">&lt;Sn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="compare-with" value="cmp-reg" />
        </docvars>
        <intro>
          <para>For the single-precision variant: is the 32-bit name of the first SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FCMP_SZ_floatcmp" symboldefcount="2">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="compare-with" value="cmp-zero" />
        </docvars>
        <intro>
          <para>For the single-precision, zero variant: is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FCMP_S_floatcmp" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/float/compare/uncond" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPEnabled64()">CheckFPEnabled64</a>();

bits(datasize) operand1 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, datasize];
bits(datasize) operand2;

operand2 = if cmp_with_zero then <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>('0', datasize) else <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[m, datasize];

PSTATE.&lt;N,Z,C,V&gt; = <a link="impl-shared.FPCompare.4" file="shared_pseudocode.xml" hover="function: bits(4) FPCompare(bits(N) op1, bits(N) op2, boolean signal_nans, FPCRType fpcr)">FPCompare</a>(operand1, operand2, signal_all_nans, FPCR[]);</pstext>
    </ps>
  </ps_section>
</instructionsection>
