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<instructionsection id="STCLR_LDCLR" title="STCLR, STCLRL -- A64" type="alias">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A64" />
  </docvars>
  <heading>STCLR, STCLRL</heading>
  <desc>
    <brief>
      <para>Atomic bit clear on word or doubleword in memory, without return</para>
    </brief>
    <authored>
      <para>Atomic bit clear on word or doubleword in memory, without return, atomically loads a 32-bit word or 64-bit doubleword from memory, performs a bitwise AND with the complement of the value held in a register on it, and stores the result back to memory.</para>
      <list type="unordered">
        <listitem><content><instruction>STCLR</instruction> does not have release semantics.</content></listitem>
        <listitem><content><instruction>STCLRL</instruction> stores to memory with release semantics, as described in <xref linkend="BEIHCHEF">Load-Acquire, Store-Release</xref>.</content></listitem>
      </list>
      <para>For information about memory accesses see <xref linkend="CHDIIIBB">Load/Store addressing modes</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <aliasto refiform="ldclr.xml" iformid="LDCLR">LDCLR, LDCLRA, LDCLRAL, LDCLRL</aliasto>
  <classes>
    <iclass name="Integer" oneof="1" id="iclass_general" no_encodings="4" isa="A64">
      <docvars>
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A64" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.1" feature="FEAT_LSE" />
      </arch_variants>
      <regdiagram form="32" psname="aarch64/instrs/memory/atomicops/ld" tworows="1">
        <box hibit="31" width="2" name="size" usename="1" settings="1" psbits="xx">
          <c>1</c>
          <c>x</c>
        </box>
        <box hibit="29" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="26" name="V" settings="1">
          <c>0</c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" name="A" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="22" name="R" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="5" name="Rs" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" name="o3" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="opc" usename="1" settings="3" psbits="xxx">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rt" usename="1" settings="5" psbits="xxxxx">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
      </regdiagram>
      <encoding name="STCLR_LDCLR_32_memop" oneofinclass="4" oneof="4" label="32-bit LDCLR alias" bitdiffs="size == 10 &amp;&amp; R == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="STCLR" />
          <docvar key="atomic-ops" value="LDCLR-32-reg" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A64" />
          <docvar key="loadstore-order" value="no-order" />
          <docvar key="mnemonic" value="LDCLR" />
          <docvar key="reg-type" value="32-reg" />
        </docvars>
        <box hibit="31" width="2" name="size">
          <c></c>
          <c>0</c>
        </box>
        <box hibit="22" width="1" name="R">
          <c>0</c>
        </box>
        <asmtemplate><text>STCLR  </text><a link="sa_ws" hover="32-bit general-purpose register holding data value to be operated on with the contents of memory location (field &quot;Rs&quot;)">&lt;Ws&gt;</a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="ldclr.xml#LDCLR_32_memop">LDCLR</a><text> </text><a link="sa_ws" hover="32-bit general-purpose register holding data value to be operated on with the contents of memory location (field &quot;Rs&quot;)">&lt;Ws&gt;</a><text>, WZR, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="STCLRL_LDCLRL_32_memop" oneofinclass="4" oneof="4" label="32-bit LDCLRL alias" bitdiffs="size == 10 &amp;&amp; R == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="STCLRL" />
          <docvar key="atomic-ops" value="LDCLRL-32-reg" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A64" />
          <docvar key="loadstore-order" value="release" />
          <docvar key="mnemonic" value="LDCLRL" />
          <docvar key="reg-type" value="32-reg" />
        </docvars>
        <box hibit="31" width="2" name="size">
          <c></c>
          <c>0</c>
        </box>
        <box hibit="22" width="1" name="R">
          <c>1</c>
        </box>
        <asmtemplate><text>STCLRL  </text><a link="sa_ws" hover="32-bit general-purpose register holding data value to be operated on with the contents of memory location (field &quot;Rs&quot;)">&lt;Ws&gt;</a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="ldclr.xml#LDCLRL_32_memop">LDCLRL</a><text> </text><a link="sa_ws" hover="32-bit general-purpose register holding data value to be operated on with the contents of memory location (field &quot;Rs&quot;)">&lt;Ws&gt;</a><text>, WZR, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="STCLR_LDCLR_64_memop" oneofinclass="4" oneof="4" label="64-bit LDCLR alias" bitdiffs="size == 11 &amp;&amp; R == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="STCLR" />
          <docvar key="atomic-ops" value="LDCLR-64-reg" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A64" />
          <docvar key="loadstore-order" value="no-order" />
          <docvar key="mnemonic" value="LDCLR" />
          <docvar key="reg-type" value="64-reg" />
        </docvars>
        <box hibit="31" width="2" name="size">
          <c></c>
          <c>1</c>
        </box>
        <box hibit="22" width="1" name="R">
          <c>0</c>
        </box>
        <asmtemplate><text>STCLR  </text><a link="sa_xs" hover="64-bit general-purpose register holding data value to be operated on with the contents of memory location (field &quot;Rs&quot;)">&lt;Xs&gt;</a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="ldclr.xml#LDCLR_64_memop">LDCLR</a><text> </text><a link="sa_xs" hover="64-bit general-purpose register holding data value to be operated on with the contents of memory location (field &quot;Rs&quot;)">&lt;Xs&gt;</a><text>, XZR, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="STCLRL_LDCLRL_64_memop" oneofinclass="4" oneof="4" label="64-bit LDCLRL alias" bitdiffs="size == 11 &amp;&amp; R == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="STCLRL" />
          <docvar key="atomic-ops" value="LDCLRL-64-reg" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A64" />
          <docvar key="loadstore-order" value="release" />
          <docvar key="mnemonic" value="LDCLRL" />
          <docvar key="reg-type" value="64-reg" />
        </docvars>
        <box hibit="31" width="2" name="size">
          <c></c>
          <c>1</c>
        </box>
        <box hibit="22" width="1" name="R">
          <c>1</c>
        </box>
        <asmtemplate><text>STCLRL  </text><a link="sa_xs" hover="64-bit general-purpose register holding data value to be operated on with the contents of memory location (field &quot;Rs&quot;)">&lt;Xs&gt;</a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="ldclr.xml#LDCLRL_64_memop">LDCLRL</a><text> </text><a link="sa_xs" hover="64-bit general-purpose register holding data value to be operated on with the contents of memory location (field &quot;Rs&quot;)">&lt;Xs&gt;</a><text>, XZR, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STCLR_LDCLR_32_memop" symboldefcount="1">
      <symbol link="sa_ws">&lt;Ws&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STCLR_LDCLR_64_memop" symboldefcount="1">
      <symbol link="sa_xs">&lt;Xs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the 64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STCLR_LDCLR_32_memop, STCLR_LDCLR_64_memop" symboldefcount="1">
      <symbol link="sa_xn_sp">&lt;Xn|SP&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
