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<instructionsection id="movprfx_z_z" title="MOVPRFX (unpredicated)" type="instruction">
  <docvars>
    <docvar key="instr-class" value="sve" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="MOVPRFX" />
  </docvars>
  <heading>MOVPRFX (unpredicated)</heading>
  <desc>
    <brief>Move prefix (unpredicated)</brief>
    <description>
      <para>The unpredicated <instruction>MOVPRFX</instruction> instruction is a hint to hardware that the instruction may be combined with the destructive instruction which follows it in program order to create a single constructive operation. Since it is a hint it is also permitted to be implemented as a discrete vector copy, and the result of executing the pair of instructions with or without combining is identical. The choice of combined versus discrete operation may vary dynamically.</para>
      <para />
      <para>Although the operation of the instruction is defined as a simple unpredicated vector copy, it is required that the prefixed instruction at PC+4 must be an SVE destructive binary or ternary instruction encoding, or a unary operation with merging predication, but excluding other <instruction>MOVPRFX</instruction> instructions. The prefixed instruction must specify the same destination vector as the <instruction>MOVPRFX</instruction> instruction. The prefixed instruction must not use the destination register in any other operand position, even if they have different names but refer to the same architectural register state. Any other use is UNPREDICTABLE.</para>
    </description>
    <status>Green</status>
    <predicated>False</predicated>
    <uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="sve" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="MOVPRFX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="MOVPRFX-Z.Z-_">
        <box hibit="31" width="8" settings="8">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" name="opc&lt;1&gt;" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="opc&lt;0&gt;" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="4" name="opc2&lt;4:1&gt;" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="16" name="opc2&lt;0&gt;" settings="1">
          <c>0</c>
        </box>
        <box hibit="15" width="6" settings="6">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="5" name="Zn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Zd" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="movprfx_z_z_" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="instr-class" value="sve" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="MOVPRFX" />
        </docvars>
        <asmtemplate><text>MOVPRFX </text><a link="sa_zd" hover="Destination scalable vector register (field &quot;Zd&quot;)">&lt;Zd&gt;</a><text>, </text><a link="sa_zn" hover="Source scalable vector register (field &quot;Zn&quot;)">&lt;Zn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="MOVPRFX-Z.Z-_" mylink="MOVPRFX-Z.Z-_" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() &amp;&amp; !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="movprfx_z_z_" symboldefcount="1">
      <symbol link="sa_zd">&lt;Zd&gt;</symbol>
      <account encodedin="Zd">
        <intro>
          <para>Is the name of the destination scalable vector register, encoded in the "Zd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="movprfx_z_z_" symboldefcount="1">
      <symbol link="sa_zn">&lt;Zn&gt;</symbol>
      <account encodedin="Zn">
        <intro>
          <para>Is the name of the source scalable vector register, encoded in the "Zn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="MOVPRFX-Z.Z-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
constant integer PL = VL DIV 8;
bits(VL) result = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</pstext>
    </ps>
  </ps_section>
</instructionsection>
