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<instructionsection id="MOV_cpy_z_o_i" title="MOV (immediate, predicated, zeroing)" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="MOV" />
    <docvar key="instr-class" value="sve" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="CPY" />
  </docvars>
  <heading>MOV (immediate, predicated, zeroing)</heading>
  <desc>
    <brief>Move signed integer immediate to vector elements (zeroing)</brief>
    <description>
      <para>Move a signed integer immediate to each active element in the destination vector. Inactive elements in the destination vector register are set to zero.</para>
      <para>The immediate operand is a signed value in the range -128 to +127, and for element widths of 16 bits or higher it may also be a signed multiple of 256 in the range -32768 to +32512 (excluding 0).</para>
      <para>The immediate is encoded in 8 bits with an optional left shift by 8. The preferred disassembly when the shift option is specified is "<syntax>#&lt;simm8&gt;, LSL #8</syntax>". However an assembler and disassembler may also allow use of the shifted 16-bit value unless the immediate is 0 and the shift amount is 8, which must be unambiguously described as "<syntax>#0, LSL #8</syntax>".</para>
    </description>
    <status>Green</status>
    <predicated>True</predicated>
    <uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
  </desc>
  <aliasto refiform="cpy_z_o_i.xml" iformid="cpy_z_o_i">CPY (immediate, zeroing)</aliasto>
  <classes>
    <iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="sve" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="CPY" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="CPY-Z.O.I-_" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="23" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Pg" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" name="M" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="13" name="sh" usename="1">
          <c></c>
        </box>
        <box hibit="12" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
        <box hibit="4" width="5" name="Zd" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="MOV_cpy_z_o_i_" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="alias_mnemonic" value="MOV" />
          <docvar key="instr-class" value="sve" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="CPY" />
        </docvars>
        <asmtemplate><text>MOV     </text><a link="sa_zd" hover="Destination scalable vector register (field &quot;Zd&quot;)">&lt;Zd&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;size&quot;) [B,D,H,S]">&lt;T&gt;</a><text>, </text><a link="sa_pg" hover="Governing scalable predicate register (field &quot;Pg&quot;)">&lt;Pg&gt;</a><text>/Z, #</text><a link="sa_imm" hover="Signed immediate [-128-127] (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>{</text><text>, </text><a link="sa_shift" hover="Optional left shift to apply to the immediate, default LSL #0 (field &quot;sh&quot;) [LSL #0,LSL #8]">&lt;shift&gt;</a><text>}</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="cpy_z_o_i.xml#cpy_z_o_i_">CPY</a><text>     </text><a link="sa_zd" hover="Destination scalable vector register (field &quot;Zd&quot;)">&lt;Zd&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;size&quot;) [B,D,H,S]">&lt;T&gt;</a><text>, </text><a link="sa_pg" hover="Governing scalable predicate register (field &quot;Pg&quot;)">&lt;Pg&gt;</a><text>/Z, #</text><a link="sa_imm" hover="Signed immediate [-128-127] (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>{</text><text>, </text><a link="sa_shift" hover="Optional left shift to apply to the immediate, default LSL #0 (field &quot;sh&quot;) [LSL #0,LSL #8]">&lt;shift&gt;</a><text>}</text></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="MOV_cpy_z_o_i_" symboldefcount="1">
      <symbol link="sa_zd">&lt;Zd&gt;</symbol>
      <account encodedin="Zd">
        <intro>
          <para>Is the name of the destination scalable vector register, encoded in the "Zd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_cpy_z_o_i_" symboldefcount="1">
      <symbol link="sa_t">&lt;T&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the size specifier, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;T&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">B</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">H</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">D</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="MOV_cpy_z_o_i_" symboldefcount="1">
      <symbol link="sa_pg">&lt;Pg&gt;</symbol>
      <account encodedin="Pg">
        <intro>
          <para>Is the name of the governing scalable predicate register, encoded in the "Pg" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_cpy_z_o_i_" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <intro>
          <para>Is a signed immediate in the range -128 to 127, encoded in the "imm8" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_cpy_z_o_i_" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="sh">
        <intro>Is the optional left shift to apply to the immediate, defaulting to LSL #0 and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sh</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">LSL #0</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">LSL #8</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
  </explanations>
</instructionsection>
