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<instructionsection id="FCCMP_float" title="FCCMP -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="float" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="FCCMP" />
  </docvars>
  <heading>FCCMP</heading>
  <desc>
    <brief>
      <para>Floating-point Conditional quiet Compare (scalar)</para>
    </brief>
    <authored>
      <para>Floating-point Conditional quiet Compare (scalar). This instruction compares the two SIMD&amp;FP source register values and writes the result to the <xref linkend="BEIDIGBH">PSTATE</xref>.{N, Z, C, V} flags. If the condition does not pass then the <xref linkend="BEIDIGBH">PSTATE</xref>.{N, Z, C, V} flags are set to the flag bit specifier.</para>
      <para>This instruction raises an Invalid Operation floating-point exception if either or both of the operands is a signaling NaN.</para>
      <para>A floating-point exception can be generated by this instruction. Depending on the settings in <xref linkend="AArch64.fpcr">FPCR</xref>, the exception results in either a flag being set in <xref linkend="AArch64.fpsr">FPSR</xref>, or a synchronous exception being generated. For more information, see <xref linkend="BEIJDDAG">Floating-point exception traps</xref>.</para>
      <para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
    </authored>
    <affected_by_sme output="NZCV condition flags" />
  </desc>
  <operationalnotes>
    <para>The IEEE 754 standard specifies that the result of a comparison is precisely one of &lt;, ==, &gt; or unordered.  If either or both of the operands is a NaN, they are unordered, and all three of (Operand1 &lt; Operand2), (Operand1 == Operand2) and (Operand1 &gt; Operand2) are false. An unordered comparison sets the <xref linkend="BEIDIGBH">PSTATE</xref> condition flags to N=0, Z=0, C=1, and V=1.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="Floating-point" oneof="1" id="iclass_float" no_encodings="3" isa="A64">
      <docvars>
        <docvar key="instr-class" value="float" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="FCCMP" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch64/instrs/float/compare/cond" tworows="1">
        <box hibit="31" name="M" settings="1">
          <c>0</c>
        </box>
        <box hibit="30" settings="1">
          <c>0</c>
        </box>
        <box hibit="29" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="28" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="2" name="ftype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="5" name="Rm" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" width="4" name="cond" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" name="op" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="nzcv" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="FCCMP_H_floatccmp" oneofinclass="3" oneof="3" label="Half-precision" bitdiffs="ftype == 11">
        <docvars>
          <docvar key="datatype" value="half" />
          <docvar key="instr-class" value="float" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FCCMP" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="23" width="2" name="ftype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>FCCMP  </text><a link="sa_hn" hover="First 16-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Hn&gt;</a><text>, </text><a link="sa_hm" hover="Second 16-bit SIMD&amp;FP source register (field &quot;Rm&quot;)">&lt;Hm&gt;</a><text>, #</text><a link="sa_nzcv" hover="Flag bit specifier, an immediate [0-15], giving the alternative state for 4-bit NZCV condition flags (field &quot;nzcv&quot;)">&lt;nzcv&gt;</a><text>, </text><a link="sa_cond" hover="Standard condition (field &quot;cond&quot;)">&lt;cond&gt;</a></asmtemplate>
      </encoding>
      <encoding name="FCCMP_S_floatccmp" oneofinclass="3" oneof="3" label="Single-precision" bitdiffs="ftype == 00">
        <docvars>
          <docvar key="datatype" value="single" />
          <docvar key="instr-class" value="float" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FCCMP" />
        </docvars>
        <box hibit="23" width="2" name="ftype">
          <c>0</c>
          <c>0</c>
        </box>
        <asmtemplate><text>FCCMP  </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Rm&quot;)">&lt;Sm&gt;</a><text>, #</text><a link="sa_nzcv" hover="Flag bit specifier, an immediate [0-15], giving the alternative state for 4-bit NZCV condition flags (field &quot;nzcv&quot;)">&lt;nzcv&gt;</a><text>, </text><a link="sa_cond" hover="Standard condition (field &quot;cond&quot;)">&lt;cond&gt;</a></asmtemplate>
      </encoding>
      <encoding name="FCCMP_D_floatccmp" oneofinclass="3" oneof="3" label="Double-precision" bitdiffs="ftype == 01">
        <docvars>
          <docvar key="datatype" value="double" />
          <docvar key="instr-class" value="float" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FCCMP" />
        </docvars>
        <box hibit="23" width="2" name="ftype">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>FCCMP  </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Rm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_nzcv" hover="Flag bit specifier, an immediate [0-15], giving the alternative state for 4-bit NZCV condition flags (field &quot;nzcv&quot;)">&lt;nzcv&gt;</a><text>, </text><a link="sa_cond" hover="Standard condition (field &quot;cond&quot;)">&lt;cond&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/float/compare/cond" mylink="aarch64.instrs.float.compare.cond" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);

integer datasize;
case ftype of
    when '00' datasize = 32;
    when '01' datasize = 64;
    when '10' UNDEFINED;
    when '11'
        if <a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then
            datasize = 16;
        else
            UNDEFINED;

boolean signal_all_nans = (op == '1');
bits(4) condition = cond;
bits(4) flags = nzcv;</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="FCCMP_D_floatccmp" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FCCMP_D_floatccmp" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FCCMP_H_floatccmp" symboldefcount="1">
      <symbol link="sa_hn">&lt;Hn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 16-bit name of the first SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FCCMP_H_floatccmp" symboldefcount="1">
      <symbol link="sa_hm">&lt;Hm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 16-bit name of the second SIMD&amp;FP source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FCCMP_S_floatccmp" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 32-bit name of the first SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FCCMP_S_floatccmp" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FCCMP_D_floatccmp, FCCMP_H_floatccmp, FCCMP_S_floatccmp" symboldefcount="1">
      <symbol link="sa_nzcv">&lt;nzcv&gt;</symbol>
      <account encodedin="nzcv">
        <intro>
          <para>Is the flag bit specifier, an immediate in the range 0 to 15, giving the alternative state for the 4-bit NZCV condition flags, encoded in the "nzcv" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FCCMP_D_floatccmp, FCCMP_H_floatccmp, FCCMP_S_floatccmp" symboldefcount="1">
      <symbol link="sa_cond">&lt;cond&gt;</symbol>
      <account encodedin="cond">
        <intro>
          <para>Is one of the standard conditions, encoded in the "cond" field in the standard way.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/float/compare/cond" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPEnabled64()">CheckFPEnabled64</a>();

bits(datasize) operand1 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, datasize];
bits(datasize) operand2;

operand2 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[m, datasize];

if <a link="impl-shared.ConditionHolds.1" file="shared_pseudocode.xml" hover="function: boolean ConditionHolds(bits(4) cond)">ConditionHolds</a>(condition) then
    flags = <a link="impl-shared.FPCompare.4" file="shared_pseudocode.xml" hover="function: bits(4) FPCompare(bits(N) op1, bits(N) op2, boolean signal_nans, FPCRType fpcr)">FPCompare</a>(operand1, operand2, signal_all_nans, FPCR[]);
PSTATE.&lt;N,Z,C,V&gt; = flags;</pstext>
    </ps>
  </ps_section>
</instructionsection>
