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<instructionsection id="FSQRT_float" title="FSQRT (scalar) -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="float" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="FSQRT" />
  </docvars>
  <heading>FSQRT (scalar)</heading>
  <desc>
    <brief>
      <para>Floating-point Square Root (scalar)</para>
    </brief>
    <authored>
      <para>Floating-point Square Root (scalar). This instruction calculates the square root of the value in the SIMD&amp;FP source register and writes the result to the SIMD&amp;FP destination register.</para>
      <para>A floating-point exception can be generated by this instruction. Depending on the settings in <xref linkend="AArch64.fpcr">FPCR</xref>, the exception results in either a flag being set in <xref linkend="AArch64.fpsr">FPSR</xref>, or a synchronous exception being generated. For more information, see <xref linkend="BEIJDDAG">Floating-point exception traps</xref>.</para>
      <para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="Floating-point" oneof="1" id="iclass_float" no_encodings="3" isa="A64">
      <docvars>
        <docvar key="instr-class" value="float" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="FSQRT" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch64/instrs/float/arithmetic/unary" tworows="1">
        <box hibit="31" name="M" settings="1">
          <c>0</c>
        </box>
        <box hibit="30" settings="1">
          <c>0</c>
        </box>
        <box hibit="29" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="28" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="2" name="ftype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="4" name="opcode[5:2]" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="16" width="2" name="opc" usename="1" settings="2" psbits="xx">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="14" width="5" settings="5">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="FSQRT_H_floatdp1" oneofinclass="3" oneof="3" label="Half-precision" bitdiffs="ftype == 11">
        <docvars>
          <docvar key="datatype" value="half" />
          <docvar key="instr-class" value="float" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FSQRT" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="23" width="2" name="ftype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>FSQRT  </text><a link="sa_hd" hover="16-bit SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Hd&gt;</a><text>, </text><a link="sa_hn" hover="16-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Hn&gt;</a></asmtemplate>
      </encoding>
      <encoding name="FSQRT_S_floatdp1" oneofinclass="3" oneof="3" label="Single-precision" bitdiffs="ftype == 00">
        <docvars>
          <docvar key="datatype" value="single" />
          <docvar key="instr-class" value="float" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FSQRT" />
        </docvars>
        <box hibit="23" width="2" name="ftype">
          <c>0</c>
          <c>0</c>
        </box>
        <asmtemplate><text>FSQRT  </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="32-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Sn&gt;</a></asmtemplate>
      </encoding>
      <encoding name="FSQRT_D_floatdp1" oneofinclass="3" oneof="3" label="Double-precision" bitdiffs="ftype == 01">
        <docvars>
          <docvar key="datatype" value="double" />
          <docvar key="instr-class" value="float" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FSQRT" />
        </docvars>
        <box hibit="23" width="2" name="ftype">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>FSQRT  </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="64-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Dn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/float/arithmetic/unary" mylink="aarch64.instrs.float.arithmetic.unary" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);

integer esize;
case ftype of
    when '00' esize = 32;
    when '01' esize = 64;
    when '10' UNDEFINED;
    when '11'
        if <a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then
            esize = 16;
        else
            UNDEFINED;

<a link="FPUnaryOp" file="shared_pseudocode.xml" hover="enumeration FPUnaryOp   {FPUnaryOp_ABS, FPUnaryOp_MOV, FPUnaryOp_NEG, FPUnaryOp_SQRT}">FPUnaryOp</a> fpop;
case opc of
    when '00' fpop = <a link="FPUnaryOp_MOV" file="shared_pseudocode.xml" hover="enumeration FPUnaryOp   {FPUnaryOp_ABS, FPUnaryOp_MOV, FPUnaryOp_NEG, FPUnaryOp_SQRT}">FPUnaryOp_MOV</a>;
    when '01' fpop = <a link="FPUnaryOp_ABS" file="shared_pseudocode.xml" hover="enumeration FPUnaryOp   {FPUnaryOp_ABS, FPUnaryOp_MOV, FPUnaryOp_NEG, FPUnaryOp_SQRT}">FPUnaryOp_ABS</a>;
    when '10' fpop = <a link="FPUnaryOp_NEG" file="shared_pseudocode.xml" hover="enumeration FPUnaryOp   {FPUnaryOp_ABS, FPUnaryOp_MOV, FPUnaryOp_NEG, FPUnaryOp_SQRT}">FPUnaryOp_NEG</a>;
    when '11' fpop = <a link="FPUnaryOp_SQRT" file="shared_pseudocode.xml" hover="enumeration FPUnaryOp   {FPUnaryOp_ABS, FPUnaryOp_MOV, FPUnaryOp_NEG, FPUnaryOp_SQRT}">FPUnaryOp_SQRT</a>;</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="FSQRT_D_floatdp1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FSQRT_D_floatdp1" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FSQRT_H_floatdp1" symboldefcount="1">
      <symbol link="sa_hd">&lt;Hd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 16-bit name of the SIMD&amp;FP destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FSQRT_H_floatdp1" symboldefcount="1">
      <symbol link="sa_hn">&lt;Hn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 16-bit name of the SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FSQRT_S_floatdp1" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FSQRT_S_floatdp1" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/float/arithmetic/unary" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPEnabled64()">CheckFPEnabled64</a>();

<a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr    = FPCR[];
boolean merge    = fpop != <a link="FPUnaryOp_MOV" file="shared_pseudocode.xml" hover="enumeration FPUnaryOp   {FPUnaryOp_ABS, FPUnaryOp_MOV, FPUnaryOp_NEG, FPUnaryOp_SQRT}">FPUnaryOp_MOV</a> &amp;&amp; <a link="impl-shared.IsMerging.1" file="shared_pseudocode.xml" hover="function: boolean IsMerging(FPCRType fpcr)">IsMerging</a>(fpcr);
bits(128) result = if merge then <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[d, 128] else 0&lt;127:0&gt;;

bits(esize) operand = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, esize];

case fpop of
    when <a link="FPUnaryOp_MOV" file="shared_pseudocode.xml" hover="enumeration FPUnaryOp   {FPUnaryOp_ABS, FPUnaryOp_MOV, FPUnaryOp_NEG, FPUnaryOp_SQRT}">FPUnaryOp_MOV</a>  <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 0, esize] = operand;
    when <a link="FPUnaryOp_ABS" file="shared_pseudocode.xml" hover="enumeration FPUnaryOp   {FPUnaryOp_ABS, FPUnaryOp_MOV, FPUnaryOp_NEG, FPUnaryOp_SQRT}">FPUnaryOp_ABS</a>  <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 0, esize] = <a link="impl-shared.FPAbs.1" file="shared_pseudocode.xml" hover="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(operand);
    when <a link="FPUnaryOp_NEG" file="shared_pseudocode.xml" hover="enumeration FPUnaryOp   {FPUnaryOp_ABS, FPUnaryOp_MOV, FPUnaryOp_NEG, FPUnaryOp_SQRT}">FPUnaryOp_NEG</a>  <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 0, esize] = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(operand);
    when <a link="FPUnaryOp_SQRT" file="shared_pseudocode.xml" hover="enumeration FPUnaryOp   {FPUnaryOp_ABS, FPUnaryOp_MOV, FPUnaryOp_NEG, FPUnaryOp_SQRT}">FPUnaryOp_SQRT</a> <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 0, esize] = <a link="impl-shared.FPSqrt.2" file="shared_pseudocode.xml" hover="function: bits(N) FPSqrt(bits(N) op, FPCRType fpcr)">FPSqrt</a>(operand, fpcr);

<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = result;</pstext>
    </ps>
  </ps_section>
</instructionsection>
