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<instructionsection id="LDEORH" title="LDEORH, LDEORAH, LDEORALH, LDEORLH -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A64" />
  </docvars>
  <heading>LDEORH, LDEORAH, LDEORALH, LDEORLH</heading>
  <desc>
    <brief>
      <para>Atomic Exclusive-OR on halfword in memory</para>
    </brief>
    <authored>
      <para>Atomic Exclusive-OR on halfword in memory atomically loads a 16-bit halfword from memory, performs an exclusive-OR with the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register.</para>
      <list type="unordered">
        <listitem><content>If the destination register is not <value>WZR</value>, <instruction>LDEORAH</instruction> and <instruction>LDEORALH</instruction> load from memory with acquire semantics.</content></listitem>
        <listitem><content><instruction>LDEORLH</instruction> and <instruction>LDEORALH</instruction> store to memory with release semantics.</content></listitem>
        <listitem><content><instruction>LDEORH</instruction> has neither acquire nor release semantics.</content></listitem>
      </list>
      <para>For more information about memory ordering semantics see <xref linkend="BEIHCHEF">Load-Acquire, Store-Release</xref>.</para>
      <para>For information about memory accesses see <xref linkend="CHDIIIBB">Load/Store addressing modes</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="1">
    <alias_list_intro>This instruction is used by the alias </alias_list_intro>
    <aliasref aliaspageid="STEORH_LDEORH" aliasfile="steorh_ldeorh.xml" hover="Atomic exclusive OR on halfword in memory" punct=".">
      <text>STEORH, STEORLH</text>
      <aliaspref>A == '0' &amp;&amp; Rt == '11111'</aliaspref>
    </aliasref>
    <alias_list_outro>
      <text>  See </text>
      <aliastablelink />
      <text> below for details of when the alias is preferred.</text>
    </alias_list_outro>
  </alias_list>
  <classes>
    <iclass name="Integer" oneof="1" id="iclass_general" no_encodings="4" isa="A64">
      <docvars>
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A64" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.1" feature="FEAT_LSE" />
      </arch_variants>
      <regdiagram form="32" psname="aarch64/instrs/memory/atomicops/ld" tworows="1">
        <box hibit="31" width="2" name="size" usename="1" settings="2" psbits="xx">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="29" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="26" name="V" settings="1">
          <c>0</c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" name="A" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="R" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="5" name="Rs" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" name="o3" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="opc" usename="1" settings="3" psbits="xxx">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rt" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="LDEORAH_32_memop" oneofinclass="4" oneof="4" label="LDEORAH" bitdiffs="A == 1 &amp;&amp; R == 0">
        <docvars>
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="LDEORAH" />
        </docvars>
        <box hibit="23" width="1" name="A">
          <c>1</c>
        </box>
        <box hibit="22" width="1" name="R">
          <c>0</c>
        </box>
        <asmtemplate><text>LDEORAH  </text><a link="sa_ws" hover="32-bit general-purpose register holding data value to be operated on with the contents of memory location (field &quot;Rs&quot;)">&lt;Ws&gt;</a><text>, </text><a link="sa_wt" hover="32-bit general-purpose register to be loaded (field &quot;Rt&quot;)">&lt;Wt&gt;</a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="LDEORALH_32_memop" oneofinclass="4" oneof="4" label="LDEORALH" bitdiffs="A == 1 &amp;&amp; R == 1">
        <docvars>
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="LDEORALH" />
        </docvars>
        <box hibit="23" width="1" name="A">
          <c>1</c>
        </box>
        <box hibit="22" width="1" name="R">
          <c>1</c>
        </box>
        <asmtemplate><text>LDEORALH  </text><a link="sa_ws" hover="32-bit general-purpose register holding data value to be operated on with the contents of memory location (field &quot;Rs&quot;)">&lt;Ws&gt;</a><text>, </text><a link="sa_wt" hover="32-bit general-purpose register to be loaded (field &quot;Rt&quot;)">&lt;Wt&gt;</a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="LDEORH_32_memop" oneofinclass="4" oneof="4" label="LDEORH" bitdiffs="A == 0 &amp;&amp; R == 0">
        <docvars>
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="LDEORH" />
        </docvars>
        <box hibit="23" width="1" name="A">
          <c>0</c>
        </box>
        <box hibit="22" width="1" name="R">
          <c>0</c>
        </box>
        <asmtemplate><text>LDEORH  </text><a link="sa_ws" hover="32-bit general-purpose register holding data value to be operated on with the contents of memory location (field &quot;Rs&quot;)">&lt;Ws&gt;</a><text>, </text><a link="sa_wt" hover="32-bit general-purpose register to be loaded (field &quot;Rt&quot;)">&lt;Wt&gt;</a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="LDEORLH_32_memop" oneofinclass="4" oneof="4" label="LDEORLH" bitdiffs="A == 0 &amp;&amp; R == 1">
        <docvars>
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="LDEORLH" />
        </docvars>
        <box hibit="23" width="1" name="A">
          <c>0</c>
        </box>
        <box hibit="22" width="1" name="R">
          <c>1</c>
        </box>
        <asmtemplate><text>LDEORLH  </text><a link="sa_ws" hover="32-bit general-purpose register holding data value to be operated on with the contents of memory location (field &quot;Rs&quot;)">&lt;Ws&gt;</a><text>, </text><a link="sa_wt" hover="32-bit general-purpose register to be loaded (field &quot;Rt&quot;)">&lt;Wt&gt;</a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/memory/atomicops/ld" mylink="aarch64.instrs.memory.atomicops.ld" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveAtomicExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAtomicExt()">HaveAtomicExt</a>() then UNDEFINED;

integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);

integer datasize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
integer regsize = if datasize == 64 then 64 else 32;
boolean acquire = A == '1' &amp;&amp; Rt != '11111';
boolean release = R == '1';
<a link="MemAtomicOp" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp</a> op;
case opc of
    when '000' op = <a link="MemAtomicOp_ADD" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_ADD</a>;
    when '001' op = <a link="MemAtomicOp_BIC" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_BIC</a>;
    when '010' op = <a link="MemAtomicOp_EOR" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_EOR</a>;
    when '011' op = <a link="MemAtomicOp_ORR" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_ORR</a>;
    when '100' op = <a link="MemAtomicOp_SMAX" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_SMAX</a>;
    when '101' op = <a link="MemAtomicOp_SMIN" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_SMIN</a>;
    when '110' op = <a link="MemAtomicOp_UMAX" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_UMAX</a>;
    when '111' op = <a link="MemAtomicOp_UMIN" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_UMIN</a>;
boolean tagchecked = n != 31;</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDEORH_32_memop, LDEORAH_32_memop, LDEORALH_32_memop, LDEORLH_32_memop" symboldefcount="1">
      <symbol link="sa_ws">&lt;Ws&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDEORH_32_memop, LDEORAH_32_memop, LDEORALH_32_memop, LDEORLH_32_memop" symboldefcount="1">
      <symbol link="sa_wt">&lt;Wt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDEORH_32_memop, LDEORAH_32_memop, LDEORALH_32_memop, LDEORLH_32_memop" symboldefcount="1">
      <symbol link="sa_xn_sp">&lt;Xn|SP&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/memory/atomicops/ld" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(64) address;
bits(datasize) value;
bits(datasize) data;

<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescAtomicOp.4" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescAtomicOp(MemAtomicOp modop, boolean acquire, boolean release, boolean tagchecked)">CreateAccDescAtomicOp</a>(op, acquire, release, tagchecked);

value = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[s, datasize];
if n == 31 then
    <a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
    address = <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[];
else
    address = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];

bits(datasize) comparevalue = bits(datasize) UNKNOWN; // Irrelevant when not executing CAS
data = <a link="impl-aarch64.MemAtomic.4" file="shared_pseudocode.xml" hover="function: bits(size) MemAtomic(bits(64) address, bits(size) cmpoperand, bits(size) operand, AccessDescriptor accdesc_in)">MemAtomic</a>(address, comparevalue, value, accdesc);

if t != 31 then
    <a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[t, regsize] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(data, regsize);</pstext>
    </ps>
  </ps_section>
</instructionsection>
