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<instructionsection id="UMMLA_advsimd_vec" title="UMMLA (vector) -- A64" type="instruction">
  <docvars>
    <docvar key="advsimd-type" value="simd" />
    <docvar key="instr-class" value="advsimd" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="UMMLA" />
  </docvars>
  <heading>UMMLA (vector)</heading>
  <desc>
    <brief>
      <para>Unsigned 8-bit integer matrix multiply-accumulate (vector)</para>
    </brief>
    <authored>
      <para>Unsigned 8-bit integer matrix multiply-accumulate. This instruction multiplies the 2x8 matrix of unsigned 8-bit integer values in the first source vector by the 8x2 matrix of unsigned 8-bit integer values in the second source vector. The resulting 2x2 32-bit integer matrix product is destructively added to the 32-bit integer matrix accumulator in the destination vector. This is equivalent to performing an 8-way dot product per destination element.</para>
      <para>From Armv8.2 to Armv8.5, this is an <arm-defined-word>optional</arm-defined-word> instruction. From Armv8.6 it is mandatory for implementations that include Advanced SIMD to support it. <xref linkend="AArch64.id_aa64isar1_el1">ID_AA64ISAR1_EL1</xref>.I8MM indicates whether this instruction is supported.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="Vector" oneof="1" id="iclass_simd" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="advsimd-type" value="simd" />
        <docvar key="instr-class" value="advsimd" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="UMMLA" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.6" feature="FEAT_I8MM" />
      </arch_variants>
      <regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/binary/uniform/mat-mul/int/mla" tworows="1">
        <box hibit="31" settings="1">
          <c>0</c>
        </box>
        <box hibit="30" name="Q" settings="1">
          <c>1</c>
        </box>
        <box hibit="29" name="U" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="28" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" width="5" name="Rm" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" settings="1">
          <c>1</c>
        </box>
        <box hibit="14" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="11" name="B" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="10" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="UMMLA_asimdsame2_G" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="advsimd-type" value="simd" />
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="UMMLA" />
        </docvars>
        <asmtemplate><text>UMMLA  </text><a link="sa_vd" hover="SIMD&amp;FP third source and destination register (field &quot;Rd&quot;)">&lt;Vd&gt;</a><text>.4S, </text><a link="sa_vn" hover="First SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Vn&gt;</a><text>.16B, </text><a link="sa_vm" hover="Second SIMD&amp;FP source register (field &quot;Rm&quot;)">&lt;Vm&gt;</a><text>.16B</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/vector/arithmetic/binary/uniform/mat-mul/int/mla" mylink="aarch64.instrs.vector.arithmetic.binary.uniform.mat-mul.int.mla" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveInt8MatMulExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveInt8MatMulExt()">HaveInt8MatMulExt</a>() then UNDEFINED;
boolean op1_unsigned;
boolean op2_unsigned;
case B:U of
    when '00' op1_unsigned = FALSE; op2_unsigned = FALSE;
    when '01' op1_unsigned = TRUE;  op2_unsigned = TRUE;
    when '10' op1_unsigned = TRUE;  op2_unsigned = FALSE;
    when '11' UNDEFINED;
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UMMLA_asimdsame2_G" symboldefcount="1">
      <symbol link="sa_vd">&lt;Vd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the name of the SIMD&amp;FP third source and destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UMMLA_asimdsame2_G" symboldefcount="1">
      <symbol link="sa_vn">&lt;Vn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the name of the first SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UMMLA_asimdsame2_G" symboldefcount="1">
      <symbol link="sa_vm">&lt;Vm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the name of the second SIMD&amp;FP source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/vector/arithmetic/binary/uniform/mat-mul/int/mla" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
bits(128) operand1 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, 128];
bits(128) operand2 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[m, 128];
bits(128) addend   = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[d, 128];

<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = <a link="impl-shared.MatMulAdd.5" file="shared_pseudocode.xml" hover="function: bits(N) MatMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, boolean op1_unsigned, boolean op2_unsigned)">MatMulAdd</a>(addend, operand1, operand2, op1_unsigned, op2_unsigned);</pstext>
    </ps>
  </ps_section>
</instructionsection>
