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<instructionsection id="sel_mz_p_zz" title="SEL" type="instruction">
  <docvars>
    <docvar key="instr-class" value="mortlach2" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="SEL" />
  </docvars>
  <heading>SEL</heading>
  <desc>
    <brief>Multi-vector conditionally select elements from two vectors</brief>
    <description>
      <para>Read active elements from the two or four first source vectors and inactive elements from the two or four second source vectors and place in the corresponding elements of the two or four destination vectors.</para>
    </description>
    <status>Green</status>
    <predicated>True</predicated>
    <sm_policy>SM_1_only</sm_policy>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from 2 classes:</txt>
      <a href="#iclass_to_2reg">Two registers</a>
      <txt> and </txt>
      <a href="#iclass_to_4reg">Four registers</a>
    </classesintro>
    <iclass name="Two registers" oneof="2" id="iclass_to_2reg" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="mortlach2" />
        <docvar key="isa" value="A64" />
        <docvar key="ldstruct-regcount" value="to-2reg" />
        <docvar key="mnemonic" value="SEL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
      </arch_variants>
      <regdiagram form="32" psname="SEL-MZ.P.ZZ-2">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="23" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="4" name="Zm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="16" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="12" width="3" name="PNg" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="9" width="4" name="Zn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="5" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" width="4" name="Zd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="0" settings="1">
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="sel_mz_p_zz_2" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="instr-class" value="mortlach2" />
          <docvar key="isa" value="A64" />
          <docvar key="ldstruct-regcount" value="to-2reg" />
          <docvar key="mnemonic" value="SEL" />
        </docvars>
        <asmtemplate><text>SEL     </text><text>{</text><text> </text><a link="sa_zd1" hover="First destination scalable vector register of a multi-vector sequence (field Zd)">&lt;Zd1&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;size&quot;) [B,D,H,S]">&lt;T&gt;</a><text>-</text><a link="sa_zd2" hover="Second destination scalable vector register of a multi-vector sequence (field Zd)">&lt;Zd2&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;size&quot;) [B,D,H,S]">&lt;T&gt;</a><text> </text><text>}</text><text>, </text><a link="sa_png" hover="Governing scalable predicate register PN8-PN15 (field &quot;PNg&quot;)">&lt;PNg&gt;</a><text>, </text><text>{</text><text> </text><a link="sa_zn1" hover="First scalable vector register of a multi-vector sequence (field Zn)">&lt;Zn1&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;size&quot;) [B,D,H,S]">&lt;T&gt;</a><text>-</text><a link="sa_zn2" hover="Second scalable vector register of a multi-vector sequence (field Zn)">&lt;Zn2&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;size&quot;) [B,D,H,S]">&lt;T&gt;</a><text> </text><text>}</text><text>, </text><text>{</text><text> </text><a link="sa_zm1" hover="First scalable vector register of a multi-vector sequence (field Zm)">&lt;Zm1&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;size&quot;) [B,D,H,S]">&lt;T&gt;</a><text>-</text><a link="sa_zm2" hover="Second scalable vector register of a multi-vector sequence (field Zm)">&lt;Zm2&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;size&quot;) [B,D,H,S]">&lt;T&gt;</a><text> </text><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="SEL-MZ.P.ZZ-2" mylink="SEL-MZ.P.ZZ-2" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
constant integer esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn:'0');
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm:'0');
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd:'0');
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('1':PNg);
constant integer nreg = 2;</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="Four registers" oneof="2" id="iclass_to_4reg" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="mortlach2" />
        <docvar key="isa" value="A64" />
        <docvar key="ldstruct-regcount" value="to-4reg" />
        <docvar key="mnemonic" value="SEL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
      </arch_variants>
      <regdiagram form="32" psname="SEL-MZ.P.ZZ-4">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="23" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="3" name="Zm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="17" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="12" width="3" name="PNg" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="9" width="3" name="Zn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="6" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" width="3" name="Zd" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="1" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="sel_mz_p_zz_4" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="instr-class" value="mortlach2" />
          <docvar key="isa" value="A64" />
          <docvar key="ldstruct-regcount" value="to-4reg" />
          <docvar key="mnemonic" value="SEL" />
        </docvars>
        <asmtemplate><text>SEL     </text><text>{</text><text> </text><a link="sa_zd1_1" hover="First destination scalable vector register of a multi-vector sequence (field Zd)">&lt;Zd1&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;size&quot;) [B,D,H,S]">&lt;T&gt;</a><text>-</text><a link="sa_zd4" hover="Fourth destination scalable vector register of a multi-vector sequence (field Zd)">&lt;Zd4&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;size&quot;) [B,D,H,S]">&lt;T&gt;</a><text> </text><text>}</text><text>, </text><a link="sa_png" hover="Governing scalable predicate register PN8-PN15 (field &quot;PNg&quot;)">&lt;PNg&gt;</a><text>, </text><text>{</text><text> </text><a link="sa_zn1_1" hover="First scalable vector register of a multi-vector sequence (field Zn)">&lt;Zn1&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;size&quot;) [B,D,H,S]">&lt;T&gt;</a><text>-</text><a link="sa_zn4" hover="Fourth scalable vector register of a multi-vector sequence (field Zn)">&lt;Zn4&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;size&quot;) [B,D,H,S]">&lt;T&gt;</a><text> </text><text>}</text><text>, </text><text>{</text><text> </text><a link="sa_zm1_1" hover="First scalable vector register of a multi-vector sequence (field Zm)">&lt;Zm1&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;size&quot;) [B,D,H,S]">&lt;T&gt;</a><text>-</text><a link="sa_zm4" hover="Fourth scalable vector register of a multi-vector sequence (field Zm)">&lt;Zm4&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;size&quot;) [B,D,H,S]">&lt;T&gt;</a><text> </text><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="SEL-MZ.P.ZZ-4" mylink="SEL-MZ.P.ZZ-4" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
constant integer esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn:'00');
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm:'00');
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd:'00');
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('1':PNg);
constant integer nreg = 4;</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="sel_mz_p_zz_2" symboldefcount="1">
      <symbol link="sa_zd1">&lt;Zd1&gt;</symbol>
      <account encodedin="Zd">
        <docvars>
          <docvar key="ldstruct-regcount" value="to-2reg" />
        </docvars>
        <intro>
          <para>For the two registers variant: is the name of the first destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="sel_mz_p_zz_4" symboldefcount="2">
      <symbol link="sa_zd1_1">&lt;Zd1&gt;</symbol>
      <account encodedin="Zd">
        <docvars>
          <docvar key="ldstruct-regcount" value="to-4reg" />
        </docvars>
        <intro>
          <para>For the four registers variant: is the name of the first destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 4.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="sel_mz_p_zz_2, sel_mz_p_zz_4" symboldefcount="1">
      <symbol link="sa_t">&lt;T&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the size specifier, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;T&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">B</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">H</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">D</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="sel_mz_p_zz_4" symboldefcount="1">
      <symbol link="sa_zd4">&lt;Zd4&gt;</symbol>
      <account encodedin="Zd">
        <intro>
          <para>Is the name of the fourth destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 4 plus 3.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="sel_mz_p_zz_2" symboldefcount="1">
      <symbol link="sa_zd2">&lt;Zd2&gt;</symbol>
      <account encodedin="Zd">
        <intro>
          <para>Is the name of the second destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 2 plus 1.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="sel_mz_p_zz_2, sel_mz_p_zz_4" symboldefcount="1">
      <symbol link="sa_png">&lt;PNg&gt;</symbol>
      <account encodedin="PNg">
        <intro>
          <para>Is the name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="sel_mz_p_zz_2" symboldefcount="1">
      <symbol link="sa_zn1">&lt;Zn1&gt;</symbol>
      <account encodedin="Zn">
        <docvars>
          <docvar key="ldstruct-regcount" value="to-2reg" />
        </docvars>
        <intro>
          <para>For the two registers variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zn" times 2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="sel_mz_p_zz_4" symboldefcount="2">
      <symbol link="sa_zn1_1">&lt;Zn1&gt;</symbol>
      <account encodedin="Zn">
        <docvars>
          <docvar key="ldstruct-regcount" value="to-4reg" />
        </docvars>
        <intro>
          <para>For the four registers variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zn" times 4.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="sel_mz_p_zz_4" symboldefcount="1">
      <symbol link="sa_zn4">&lt;Zn4&gt;</symbol>
      <account encodedin="Zn">
        <intro>
          <para>Is the name of the fourth scalable vector register of a multi-vector sequence, encoded as "Zn" times 4 plus 3.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="sel_mz_p_zz_2" symboldefcount="1">
      <symbol link="sa_zn2">&lt;Zn2&gt;</symbol>
      <account encodedin="Zn">
        <intro>
          <para>Is the name of the second scalable vector register of a multi-vector sequence, encoded as "Zn" times 2 plus 1.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="sel_mz_p_zz_2" symboldefcount="1">
      <symbol link="sa_zm1">&lt;Zm1&gt;</symbol>
      <account encodedin="Zm">
        <docvars>
          <docvar key="ldstruct-regcount" value="to-2reg" />
        </docvars>
        <intro>
          <para>For the two registers variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zm" times 2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="sel_mz_p_zz_4" symboldefcount="2">
      <symbol link="sa_zm1_1">&lt;Zm1&gt;</symbol>
      <account encodedin="Zm">
        <docvars>
          <docvar key="ldstruct-regcount" value="to-4reg" />
        </docvars>
        <intro>
          <para>For the four registers variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zm" times 4.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="sel_mz_p_zz_4" symboldefcount="1">
      <symbol link="sa_zm4">&lt;Zm4&gt;</symbol>
      <account encodedin="Zm">
        <intro>
          <para>Is the name of the fourth scalable vector register of a multi-vector sequence, encoded as "Zm" times 4 plus 3.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="sel_mz_p_zz_2" symboldefcount="1">
      <symbol link="sa_zm2">&lt;Zm2&gt;</symbol>
      <account encodedin="Zm">
        <intro>
          <para>Is the name of the second scalable vector register of a multi-vector sequence, encoded as "Zm" times 2 plus 1.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="SEL-MZ.P.ZZ-2" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEEnabled()">CheckStreamingSVEEnabled</a>();
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
array [0..3] of bits(VL) results;
bits(PL) pred = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
bits(PL * nreg) mask = <a link="impl-aarch64.CounterToPredicate.2" file="shared_pseudocode.xml" hover="function: bits(width) CounterToPredicate(bits(16) pred, integer width)">CounterToPredicate</a>(pred&lt;15:0&gt;, PL * nreg);

for r = 0 to nreg-1
    bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n+r, VL];
    bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m+r, VL];
    for e = 0 to elements-1
        if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, r * elements + e, esize) then
            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[results[r], e, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
        else
            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[results[r], e, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];

for r = 0 to nreg-1
    <a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d+r, VL] = results[r];</pstext>
    </ps>
  </ps_section>
</instructionsection>
