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<instructionsection id="FCVTZS_float_fix" title="FCVTZS (scalar, fixed-point) -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="float" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="FCVTZS" />
  </docvars>
  <heading>FCVTZS (scalar, fixed-point)</heading>
  <desc>
    <brief>
      <para>Floating-point Convert to Signed fixed-point, rounding toward Zero (scalar)</para>
    </brief>
    <authored>
      <para>Floating-point Convert to Signed fixed-point, rounding toward Zero (scalar). This instruction converts the floating-point value in the SIMD&amp;FP source register to a 32-bit or 64-bit fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.</para>
      <para>A floating-point exception can be generated by this instruction. Depending on the settings in <xref linkend="AArch64.fpcr">FPCR</xref>, the exception results in either a flag being set in <xref linkend="AArch64.fpsr">FPSR</xref>, or a synchronous exception being generated. For more information, see <xref linkend="BEIJDDAG">Floating-point exception traps</xref>.</para>
      <para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.</para>
    </authored>
    <affected_by_sme output="general-purpose register" />
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="Floating-point" oneof="1" id="iclass_float" no_encodings="6" isa="A64">
      <docvars>
        <docvar key="instr-class" value="float" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="FCVTZS" />
      </docvars>
      <iclassintro count="6"></iclassintro>
      <regdiagram form="32" psname="aarch64/instrs/float/convert/fix" tworows="1">
        <box hibit="31" name="sf" usename="1">
          <c></c>
        </box>
        <box hibit="30" settings="1">
          <c>0</c>
        </box>
        <box hibit="29" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="28" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="2" name="ftype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" width="2" name="rmode" usename="1" settings="2" psbits="xx">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="18" width="3" name="opcode" usename="1" settings="3" psbits="xxx">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="6" name="scale" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="FCVTZS_32H_float2fix" oneofinclass="6" oneof="6" label="Half-precision to 32-bit" bitdiffs="sf == 0 &amp;&amp; ftype == 11">
        <docvars>
          <docvar key="convert-type" value="half-to-fix32" />
          <docvar key="instr-class" value="float" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FCVTZS" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="31" width="1" name="sf">
          <c>0</c>
        </box>
        <box hibit="23" width="2" name="ftype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>FCVTZS  </text><a link="sa_wd" hover="32-bit general-purpose destination register (field &quot;Rd&quot;)">&lt;Wd&gt;</a><text>, </text><a link="sa_hn" hover="16-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Hn&gt;</a><text>, #</text><a link="sa_fbits" hover="Number of bits after the binary point in the fixed-point destination [1-32] (field scale)">&lt;fbits&gt;</a></asmtemplate>
      </encoding>
      <encoding name="FCVTZS_64H_float2fix" oneofinclass="6" oneof="6" label="Half-precision to 64-bit" bitdiffs="sf == 1 &amp;&amp; ftype == 11">
        <docvars>
          <docvar key="convert-type" value="half-to-fix64" />
          <docvar key="instr-class" value="float" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FCVTZS" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="31" width="1" name="sf">
          <c>1</c>
        </box>
        <box hibit="23" width="2" name="ftype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>FCVTZS  </text><a link="sa_xd" hover="64-bit general-purpose destination register (field &quot;Rd&quot;)">&lt;Xd&gt;</a><text>, </text><a link="sa_hn" hover="16-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Hn&gt;</a><text>, #</text><a link="sa_fbits_1" hover="Number of bits after the binary point in the fixed-point destination [1-64] (field scale)">&lt;fbits&gt;</a></asmtemplate>
      </encoding>
      <encoding name="FCVTZS_32S_float2fix" oneofinclass="6" oneof="6" label="Single-precision to 32-bit" bitdiffs="sf == 0 &amp;&amp; ftype == 00">
        <docvars>
          <docvar key="convert-type" value="single-to-fix32" />
          <docvar key="instr-class" value="float" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FCVTZS" />
        </docvars>
        <box hibit="31" width="1" name="sf">
          <c>0</c>
        </box>
        <box hibit="23" width="2" name="ftype">
          <c>0</c>
          <c>0</c>
        </box>
        <asmtemplate><text>FCVTZS  </text><a link="sa_wd" hover="32-bit general-purpose destination register (field &quot;Rd&quot;)">&lt;Wd&gt;</a><text>, </text><a link="sa_sn" hover="32-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Sn&gt;</a><text>, #</text><a link="sa_fbits" hover="Number of bits after the binary point in the fixed-point destination [1-32] (field scale)">&lt;fbits&gt;</a></asmtemplate>
      </encoding>
      <encoding name="FCVTZS_64S_float2fix" oneofinclass="6" oneof="6" label="Single-precision to 64-bit" bitdiffs="sf == 1 &amp;&amp; ftype == 00">
        <docvars>
          <docvar key="convert-type" value="single-to-fix64" />
          <docvar key="instr-class" value="float" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FCVTZS" />
        </docvars>
        <box hibit="31" width="1" name="sf">
          <c>1</c>
        </box>
        <box hibit="23" width="2" name="ftype">
          <c>0</c>
          <c>0</c>
        </box>
        <asmtemplate><text>FCVTZS  </text><a link="sa_xd" hover="64-bit general-purpose destination register (field &quot;Rd&quot;)">&lt;Xd&gt;</a><text>, </text><a link="sa_sn" hover="32-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Sn&gt;</a><text>, #</text><a link="sa_fbits_1" hover="Number of bits after the binary point in the fixed-point destination [1-64] (field scale)">&lt;fbits&gt;</a></asmtemplate>
      </encoding>
      <encoding name="FCVTZS_32D_float2fix" oneofinclass="6" oneof="6" label="Double-precision to 32-bit" bitdiffs="sf == 0 &amp;&amp; ftype == 01">
        <docvars>
          <docvar key="convert-type" value="double-to-fix32" />
          <docvar key="instr-class" value="float" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FCVTZS" />
        </docvars>
        <box hibit="31" width="1" name="sf">
          <c>0</c>
        </box>
        <box hibit="23" width="2" name="ftype">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>FCVTZS  </text><a link="sa_wd" hover="32-bit general-purpose destination register (field &quot;Rd&quot;)">&lt;Wd&gt;</a><text>, </text><a link="sa_dn" hover="64-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Dn&gt;</a><text>, #</text><a link="sa_fbits" hover="Number of bits after the binary point in the fixed-point destination [1-32] (field scale)">&lt;fbits&gt;</a></asmtemplate>
      </encoding>
      <encoding name="FCVTZS_64D_float2fix" oneofinclass="6" oneof="6" label="Double-precision to 64-bit" bitdiffs="sf == 1 &amp;&amp; ftype == 01">
        <docvars>
          <docvar key="convert-type" value="double-to-fix64" />
          <docvar key="instr-class" value="float" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FCVTZS" />
        </docvars>
        <box hibit="31" width="1" name="sf">
          <c>1</c>
        </box>
        <box hibit="23" width="2" name="ftype">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>FCVTZS  </text><a link="sa_xd" hover="64-bit general-purpose destination register (field &quot;Rd&quot;)">&lt;Xd&gt;</a><text>, </text><a link="sa_dn" hover="64-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Dn&gt;</a><text>, #</text><a link="sa_fbits_1" hover="Number of bits after the binary point in the fixed-point destination [1-64] (field scale)">&lt;fbits&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/float/convert/fix" mylink="aarch64.instrs.float.convert.fix" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);

integer intsize = if sf == '1' then 64 else 32;
integer fltsize;
<a link="FPConvOp" file="shared_pseudocode.xml" hover="enumeration FPConvOp    {FPConvOp_CVT_FtoI, FPConvOp_CVT_ItoF, FPConvOp_MOV_FtoI, FPConvOp_MOV_ItoF , FPConvOp_CVT_FtoI_JS }">FPConvOp</a> op;
<a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding;
boolean unsigned;

case ftype of
    when '00' fltsize = 32;
    when '01' fltsize = 64;
    when '10' UNDEFINED;
    when '11'
        if <a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then
            fltsize = 16;
        else
            UNDEFINED;

if sf == '0' &amp;&amp; scale&lt;5&gt; == '0' then UNDEFINED;
integer fracbits = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(scale);

case opcode&lt;2:1&gt;:rmode of
    when '00 11'        // FCVTZ
        rounding = <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a>;
        unsigned = (opcode&lt;0&gt; == '1');
        op = <a link="FPConvOp_CVT_FtoI" file="shared_pseudocode.xml" hover="enumeration FPConvOp    {FPConvOp_CVT_FtoI, FPConvOp_CVT_ItoF, FPConvOp_MOV_FtoI, FPConvOp_MOV_ItoF , FPConvOp_CVT_FtoI_JS }">FPConvOp_CVT_FtoI</a>;
    when '01 00'        // [US]CVTF
        rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR[]);
        unsigned = (opcode&lt;0&gt; == '1');
        op = <a link="FPConvOp_CVT_ItoF" file="shared_pseudocode.xml" hover="enumeration FPConvOp    {FPConvOp_CVT_FtoI, FPConvOp_CVT_ItoF, FPConvOp_MOV_FtoI, FPConvOp_MOV_ItoF , FPConvOp_CVT_FtoI_JS }">FPConvOp_CVT_ItoF</a>;
    otherwise
        UNDEFINED;</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="FCVTZS_32D_float2fix, FCVTZS_32H_float2fix, FCVTZS_32S_float2fix" symboldefcount="1">
      <symbol link="sa_wd">&lt;Wd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FCVTZS_64D_float2fix, FCVTZS_64H_float2fix, FCVTZS_64S_float2fix" symboldefcount="1">
      <symbol link="sa_xd">&lt;Xd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FCVTZS_32S_float2fix, FCVTZS_64S_float2fix" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FCVTZS_32H_float2fix, FCVTZS_64H_float2fix" symboldefcount="1">
      <symbol link="sa_hn">&lt;Hn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 16-bit name of the SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FCVTZS_32D_float2fix, FCVTZS_64D_float2fix" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FCVTZS_32D_float2fix, FCVTZS_32H_float2fix, FCVTZS_32S_float2fix" symboldefcount="1">
      <symbol link="sa_fbits">&lt;fbits&gt;</symbol>
      <account encodedin="scale">
        <intro>
          <para>For the double-precision to 32-bit, half-precision to 32-bit and single-precision to 32-bit variant: is the number of bits after the binary point in the fixed-point destination, in the range 1 to 32, encoded as 64 minus "scale".</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FCVTZS_64D_float2fix, FCVTZS_64H_float2fix, FCVTZS_64S_float2fix" symboldefcount="2">
      <symbol link="sa_fbits_1">&lt;fbits&gt;</symbol>
      <account encodedin="scale">
        <intro>
          <para>For the double-precision to 64-bit, half-precision to 64-bit and single-precision to 64-bit variant: is the number of bits after the binary point in the fixed-point destination, in the range 1 to 64, encoded as 64 minus "scale".</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/float/convert/fix" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPEnabled64()">CheckFPEnabled64</a>();

<a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = FPCR[];
boolean merge = <a link="impl-shared.IsMerging.1" file="shared_pseudocode.xml" hover="function: boolean IsMerging(FPCRType fpcr)">IsMerging</a>(fpcr);
integer fsize = if op == <a link="FPConvOp_CVT_ItoF" file="shared_pseudocode.xml" hover="enumeration FPConvOp    {FPConvOp_CVT_FtoI, FPConvOp_CVT_ItoF, FPConvOp_MOV_FtoI, FPConvOp_MOV_ItoF , FPConvOp_CVT_FtoI_JS }">FPConvOp_CVT_ItoF</a> &amp;&amp; merge then 128 else fltsize;
bits(fsize) fltval;
bits(intsize) intval;

case op of
    when <a link="FPConvOp_CVT_FtoI" file="shared_pseudocode.xml" hover="enumeration FPConvOp    {FPConvOp_CVT_FtoI, FPConvOp_CVT_ItoF, FPConvOp_MOV_FtoI, FPConvOp_MOV_ItoF , FPConvOp_CVT_FtoI_JS }">FPConvOp_CVT_FtoI</a>
        fltval = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, fsize];
        intval = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(fltval, fracbits, unsigned, fpcr, rounding, intsize);
        <a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, intsize] = intval;
    when <a link="FPConvOp_CVT_ItoF" file="shared_pseudocode.xml" hover="enumeration FPConvOp    {FPConvOp_CVT_FtoI, FPConvOp_CVT_ItoF, FPConvOp_MOV_FtoI, FPConvOp_MOV_ItoF , FPConvOp_CVT_FtoI_JS }">FPConvOp_CVT_ItoF</a>
        intval = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, intsize];
        fltval = if merge then <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[d, fsize] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(fsize);
        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[fltval, 0, fltsize] = <a link="impl-shared.FixedToFP.6" file="shared_pseudocode.xml" hover="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer N)">FixedToFP</a>(intval, fracbits, unsigned, fpcr, rounding, fltsize);
        <a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, fsize] = fltval;</pstext>
    </ps>
  </ps_section>
</instructionsection>
