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<instructionsection id="SQSHRN_advsimd" title="SQSHRN, SQSHRN2 -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="advsimd" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="SQSHRN" />
  </docvars>
  <heading>SQSHRN, SQSHRN2</heading>
  <desc>
    <brief>
      <para>Signed saturating Shift Right Narrow (immediate)</para>
    </brief>
    <authored>
      <para>Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see <xref linkend="A64.instructions.SQRSHRN_advsimd">SQRSHRN</xref>.</para>
      <para>The <instruction>SQSHRN</instruction> instruction writes the vector to the lower half of the destination register and clears the upper half, while the <instruction>SQSHRN2</instruction> instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.</para>
      <para>If saturation occurs, the cumulative saturation bit <xref linkend="AArch64.fpsr">FPSR</xref>.QC is set.</para>
      <para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from 2 classes:</txt>
      <a href="#iclass_sisd">Scalar</a>
      <txt> and </txt>
      <a href="#iclass_simd">Vector</a>
    </classesintro>
    <iclass name="Scalar" oneof="2" id="iclass_sisd" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="advsimd-type" value="sisd" />
        <docvar key="instr-class" value="advsimd" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="SQSHRN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch64/instrs/vector/shift/right-narrow/uniform/sisd" tworows="1">
        <box hibit="31" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="29" name="U" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="28" width="6" settings="6">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="4" name="immh" usename="1" settings="4" constraint="!= 0000" psbits="xxxx">
          <c colspan="4">!= 0000</c>
        </box>
        <box hibit="18" width="3" name="immb" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="opcode[4:1]" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="11" name="op" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="10" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="SQSHRN_asisdshf_N" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="advsimd-type" value="sisd" />
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="SQSHRN" />
        </docvars>
        <asmtemplate><text>SQSHRN  </text><a link="sa_vb" hover="Destination width specifier (field &quot;immh&quot;) [B,H,S]">&lt;Vb&gt;</a><a link="sa_d" hover="SIMD&amp;FP destination register number (field &quot;Rd&quot;)">&lt;d&gt;</a><text>, </text><a link="sa_va" hover="Source width specifier (field &quot;immh&quot;) [D,H,S]">&lt;Va&gt;</a><a link="sa_n" hover="First SIMD&amp;FP source register number (field &quot;Rn&quot;)">&lt;n&gt;</a><text>, #</text><a link="sa_shift_1" hover="Right shift amount [1-the destination operand width in bits] (field &quot;immh:immb&quot;)">&lt;shift&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/vector/shift/right-narrow/uniform/sisd" mylink="aarch64.instrs.vector.shift.right-narrow.uniform.sisd" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);

if immh == '0000' then UNDEFINED;
if immh&lt;3&gt; == '1' then UNDEFINED;
integer esize = 8 &lt;&lt; <a link="impl-shared.HighestSetBit.1" file="shared_pseudocode.xml" hover="function: integer HighestSetBit(bits(N) x)">HighestSetBit</a>(immh);
integer datasize = esize;
integer elements = 1;
integer part = 0;

integer shift = (2 * esize) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(immh:immb);
boolean round = (op == '1');
boolean unsigned = (U == '1');</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="Vector" oneof="2" id="iclass_simd" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="advsimd-type" value="simd" />
        <docvar key="instr-class" value="advsimd" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="SQSHRN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch64/instrs/vector/shift/right-narrow/uniform/simd" tworows="1">
        <box hibit="31" settings="1">
          <c>0</c>
        </box>
        <box hibit="30" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="29" name="U" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="28" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="4" name="immh" usename="1" settings="4" constraint="!= 0000">
          <c colspan="4">!= 0000</c>
        </box>
        <box hibit="18" width="3" name="immb" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="opcode[4:1]" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="11" name="op" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="10" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="SQSHRN_asimdshf_N" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="advsimd-type" value="simd" />
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="SQSHRN" />
        </docvars>
        <asmtemplate><text>SQSHRN</text><a link="sa_2" hover="Second and upper half specifier (field &quot;Q&quot;)">{2}</a><text>  </text><a link="sa_vd" hover="SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Vd&gt;</a><text>.</text><a link="sa_tb" hover="Arrangement specifier (field &quot;immh:Q&quot;) [2S,4H,4S,8B,8H,16B,SEE(asimdimm)]">&lt;Tb&gt;</a><text>, </text><a link="sa_vn" hover="SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Vn&gt;</a><text>.</text><a link="sa_ta" hover="Arrangement specifier (field &quot;immh&quot;) [2D,4S,8H,SEE(asimdimm)]">&lt;Ta&gt;</a><text>, #</text><a link="sa_shift" hover="Right shift amount [1-the destination element width in bits] (field &quot;immh:immb&quot;)">&lt;shift&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/vector/shift/right-narrow/uniform/simd" mylink="aarch64.instrs.vector.shift.right-narrow.uniform.simd" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);

if immh == '0000' then <a link="asimdimm" file="encodingindex.xml" hover="handled by an instruction in the 'Advanced SIMD modified immediate' class">SEE(asimdimm)</a>;
if immh&lt;3&gt; == '1' then UNDEFINED;
integer esize = 8 &lt;&lt; <a link="impl-shared.HighestSetBit.1" file="shared_pseudocode.xml" hover="function: integer HighestSetBit(bits(N) x)">HighestSetBit</a>(immh);
integer datasize = 64;
integer part = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Q);
integer elements = datasize DIV esize;

integer shift = (2 * esize) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(immh:immb);
boolean round = (op == '1');
boolean unsigned = (U == '1');</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SQSHRN_asimdshf_N" symboldefcount="1">
      <symbol link="sa_2">2</symbol>
      <definition encodedin="Q">
        <intro>Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">Q</entry>
                <entry class="symbol">2</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">[absent]</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">[present]</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="SQSHRN_asimdshf_N" symboldefcount="1">
      <symbol link="sa_vd">&lt;Vd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the name of the SIMD&amp;FP destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SQSHRN_asimdshf_N" symboldefcount="1">
      <symbol link="sa_tb">&lt;Tb&gt;</symbol>
      <definition encodedin="immh:Q">
        <intro>Is an arrangement specifier, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">immh</entry>
                <entry class="bitfield">Q</entry>
                <entry class="symbol">&lt;Tb&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0000</entry>
                <entry class="bitfield">x</entry>
                <entry class="symbol" iclasslink="asimdimm" iclasslinkfile="encodingindex.xml">SEE Advanced SIMD modified immediate</entry>
              </row>
              <row>
                <entry class="bitfield">0001</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">8B</entry>
              </row>
              <row>
                <entry class="bitfield">0001</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">16B</entry>
              </row>
              <row>
                <entry class="bitfield">001x</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">4H</entry>
              </row>
              <row>
                <entry class="bitfield">001x</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">8H</entry>
              </row>
              <row>
                <entry class="bitfield">01xx</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">2S</entry>
              </row>
              <row>
                <entry class="bitfield">01xx</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">4S</entry>
              </row>
              <row>
                <entry class="bitfield">1xxx</entry>
                <entry class="bitfield">x</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="SQSHRN_asimdshf_N" symboldefcount="1">
      <symbol link="sa_vn">&lt;Vn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the name of the SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SQSHRN_asimdshf_N" symboldefcount="1">
      <symbol link="sa_ta">&lt;Ta&gt;</symbol>
      <definition encodedin="immh">
        <intro>Is an arrangement specifier, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">immh</entry>
                <entry class="symbol">&lt;Ta&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0000</entry>
                <entry class="symbol" iclasslink="asimdimm" iclasslinkfile="encodingindex.xml">SEE Advanced SIMD modified immediate</entry>
              </row>
              <row>
                <entry class="bitfield">0001</entry>
                <entry class="symbol">8H</entry>
              </row>
              <row>
                <entry class="bitfield">001x</entry>
                <entry class="symbol">4S</entry>
              </row>
              <row>
                <entry class="bitfield">01xx</entry>
                <entry class="symbol">2D</entry>
              </row>
              <row>
                <entry class="bitfield">1xxx</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="SQSHRN_asisdshf_N" symboldefcount="1">
      <symbol link="sa_vb">&lt;Vb&gt;</symbol>
      <definition encodedin="immh">
        <intro>Is the destination width specifier, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">immh</entry>
                <entry class="symbol">&lt;Vb&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0000</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">0001</entry>
                <entry class="symbol">B</entry>
              </row>
              <row>
                <entry class="bitfield">001x</entry>
                <entry class="symbol">H</entry>
              </row>
              <row>
                <entry class="bitfield">01xx</entry>
                <entry class="symbol">S</entry>
              </row>
              <row>
                <entry class="bitfield">1xxx</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="SQSHRN_asisdshf_N" symboldefcount="1">
      <symbol link="sa_d">&lt;d&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the number of the SIMD&amp;FP destination register, in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SQSHRN_asisdshf_N" symboldefcount="1">
      <symbol link="sa_va">&lt;Va&gt;</symbol>
      <definition encodedin="immh">
        <intro>Is the source width specifier, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">immh</entry>
                <entry class="symbol">&lt;Va&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0000</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">0001</entry>
                <entry class="symbol">H</entry>
              </row>
              <row>
                <entry class="bitfield">001x</entry>
                <entry class="symbol">S</entry>
              </row>
              <row>
                <entry class="bitfield">01xx</entry>
                <entry class="symbol">D</entry>
              </row>
              <row>
                <entry class="bitfield">1xxx</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="SQSHRN_asisdshf_N" symboldefcount="1">
      <symbol link="sa_n">&lt;n&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the number of the first SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SQSHRN_asisdshf_N" symboldefcount="1">
      <symbol link="sa_shift_1">&lt;shift&gt;</symbol>
      <definition encodedin="immh:immb">
        <intro>For the scalar variant: is the right shift amount, in the range 1 to the destination operand width in bits, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">immh</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0000</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">0001</entry>
                <entry class="symbol">(16-UInt(immh:immb))</entry>
              </row>
              <row>
                <entry class="bitfield">001x</entry>
                <entry class="symbol">(32-UInt(immh:immb))</entry>
              </row>
              <row>
                <entry class="bitfield">01xx</entry>
                <entry class="symbol">(64-UInt(immh:immb))</entry>
              </row>
              <row>
                <entry class="bitfield">1xxx</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="SQSHRN_asimdshf_N" symboldefcount="2">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="immh:immb">
        <intro>For the vector variant: is the right shift amount, in the range 1 to the destination element width in bits, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">immh</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0000</entry>
                <entry class="symbol" iclasslink="asimdimm" iclasslinkfile="encodingindex.xml">SEE Advanced SIMD modified immediate</entry>
              </row>
              <row>
                <entry class="bitfield">0001</entry>
                <entry class="symbol">(16-UInt(immh:immb))</entry>
              </row>
              <row>
                <entry class="bitfield">001x</entry>
                <entry class="symbol">(32-UInt(immh:immb))</entry>
              </row>
              <row>
                <entry class="bitfield">01xx</entry>
                <entry class="symbol">(64-UInt(immh:immb))</entry>
              </row>
              <row>
                <entry class="bitfield">1xxx</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/vector/shift/right-narrow/uniform/sisd" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
bits(datasize*2) operand = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, datasize*2];
bits(datasize) result;
integer round_const = if round then (1 &lt;&lt; (shift - 1)) else 0;
integer element;
boolean sat;

for e = 0 to elements-1
    element = (<a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) &gt;&gt; shift;
    (<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a link="impl-shared.SatQ.3" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
    if sat then FPSR.QC = '1';

<a link="impl-aarch64.Vpart.write.3" file="shared_pseudocode.xml" hover="accessor: Vpart[integer n, integer part, integer width] = bits(width) value">Vpart</a>[d, part, datasize] = result;</pstext>
    </ps>
  </ps_section>
</instructionsection>
