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<instructionsection id="insr_z_r" title="INSR (scalar)" type="instruction">
  <docvars>
    <docvar key="instr-class" value="sve" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="INSR" />
  </docvars>
  <heading>INSR (scalar)</heading>
  <desc>
    <brief>Insert general-purpose register in shifted vector</brief>
    <description>
      <para>Shift the destination vector left by one element, and then place a copy of the least-significant bits of the general-purpose register in element 0 of the destination vector. This instruction is unpredicated.</para>
    </description>
    <status>Green</status>
    <predicated>False</predicated>
    <uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
    <takes_movprfx>True</takes_movprfx>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="sve" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="INSR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="INSR-Z.R-_">
        <box hibit="31" width="8" settings="8">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="23" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="21" width="12" settings="12">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Rm" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Zdn" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="insr_z_r_" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="instr-class" value="sve" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="INSR" />
        </docvars>
        <asmtemplate><text>INSR    </text><a link="sa_zdn" hover="Source and destination scalable vector register (field &quot;Zdn&quot;)">&lt;Zdn&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;size&quot;) [B,D,H,S]">&lt;T&gt;</a><text>, </text><a link="sa_r" hover="Width specifier (field &quot;size&quot;) [W,X]">&lt;R&gt;</a><a link="sa_m" hover="Source general-purpose register number [0-30] or ZR (31) (field &quot;Rm&quot;)">&lt;m&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="INSR-Z.R-_" mylink="INSR-Z.R-_" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() &amp;&amp; !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
constant integer esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zdn);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="insr_z_r_" symboldefcount="1">
      <symbol link="sa_zdn">&lt;Zdn&gt;</symbol>
      <account encodedin="Zdn">
        <intro>
          <para>Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="insr_z_r_" symboldefcount="1">
      <symbol link="sa_t">&lt;T&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the size specifier, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;T&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">B</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">H</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">D</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="insr_z_r_" symboldefcount="1">
      <symbol link="sa_r">&lt;R&gt;</symbol>
      <definition encodedin="size">
        <intro>Is a width specifier, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;R&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">W</entry>
              </row>
              <row>
                <entry class="bitfield">x0</entry>
                <entry class="symbol">W</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">X</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="insr_z_r_" symboldefcount="1">
      <symbol link="sa_m">&lt;m&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="INSR-Z.R-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
constant integer PL = VL DIV 8;
bits(VL) dest = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
bits(esize) src = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[m, esize];
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = dest&lt;(VL-esize)-1:0&gt; : src;</pstext>
    </ps>
  </ps_section>
</instructionsection>
