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<instructionsection id="ST1_advsimd_sngl" title="ST1 (single structure) -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="advsimd" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="ST1" />
  </docvars>
  <heading>ST1 (single structure)</heading>
  <desc>
    <brief>
      <para>Store a single-element structure from one lane of one register</para>
    </brief>
    <authored>
      <para>Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&amp;FP register to memory.</para>
      <para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from 2 classes:</txt>
      <a href="#iclass_as_no_post_index">No offset</a>
      <txt> and </txt>
      <a href="#iclass_as_post_index">Post-index</a>
    </classesintro>
    <iclass name="No offset" oneof="2" id="iclass_as_no_post_index" no_encodings="4" isa="A64">
      <docvars>
        <docvar key="as-structure-post-index" value="as-no-post-index" />
        <docvar key="instr-class" value="advsimd" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="ST1" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch64/instrs/memory/vector/single/no-wb" tworows="1">
        <box hibit="31" settings="1">
          <c>0</c>
        </box>
        <box hibit="30" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="29" width="7" settings="7">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="L" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="21" name="R" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="20" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="16" name="o2" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="15" width="3" name="opcode" usename="1" settings="1" psbits="xxx">
          <c>x</c>
          <c>x</c>
          <c>0</c>
        </box>
        <box hibit="12" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rt" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="ST1_asisdlso_B1_1b" oneofinclass="4" oneof="12" label="8-bit" bitdiffs="opcode == 000">
        <docvars>
          <docvar key="as-structure-org" value="of-bytes" />
          <docvar key="as-structure-post-index" value="as-no-post-index" />
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="ST1" />
        </docvars>
        <box hibit="15" width="3" name="opcode">
          <c>0</c>
          <c>0</c>
          <c></c>
        </box>
        <asmtemplate><text>ST1  </text><text>{</text><text> </text><a link="sa_vt" hover="First or only SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Vt&gt;</a><text>.B </text><text>}</text><text>[</text><a link="sa_index" hover="Element index (field &quot;Q:S:size&quot;)">&lt;index&gt;</a><text>], [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="ST1_asisdlso_H1_1h" oneofinclass="4" oneof="12" label="16-bit" bitdiffs="opcode == 010 &amp;&amp; size == x0">
        <docvars>
          <docvar key="as-structure-org" value="of-halfwords" />
          <docvar key="as-structure-post-index" value="as-no-post-index" />
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="ST1" />
        </docvars>
        <box hibit="15" width="3" name="opcode">
          <c>0</c>
          <c>1</c>
          <c></c>
        </box>
        <box hibit="11" width="2" name="size">
          <c></c>
          <c>0</c>
        </box>
        <asmtemplate><text>ST1  </text><text>{</text><text> </text><a link="sa_vt" hover="First or only SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Vt&gt;</a><text>.H </text><text>}</text><text>[</text><a link="sa_index_2" hover="Element index (field &quot;Q:S:size&lt;1&gt;&quot;)">&lt;index&gt;</a><text>], [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="ST1_asisdlso_S1_1s" oneofinclass="4" oneof="12" label="32-bit" bitdiffs="opcode == 100 &amp;&amp; size == 00">
        <docvars>
          <docvar key="as-structure-org" value="of-words" />
          <docvar key="as-structure-post-index" value="as-no-post-index" />
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="ST1" />
        </docvars>
        <box hibit="15" width="3" name="opcode">
          <c>1</c>
          <c>0</c>
          <c></c>
        </box>
        <box hibit="11" width="2" name="size">
          <c>0</c>
          <c>0</c>
        </box>
        <asmtemplate><text>ST1  </text><text>{</text><text> </text><a link="sa_vt" hover="First or only SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Vt&gt;</a><text>.S </text><text>}</text><text>[</text><a link="sa_index_3" hover="Element index (field &quot;Q:S&quot;)">&lt;index&gt;</a><text>], [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="ST1_asisdlso_D1_1d" oneofinclass="4" oneof="12" label="64-bit" bitdiffs="opcode == 100 &amp;&amp; S == 0 &amp;&amp; size == 01">
        <docvars>
          <docvar key="as-structure-org" value="of-doublewords" />
          <docvar key="as-structure-post-index" value="as-no-post-index" />
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="ST1" />
        </docvars>
        <box hibit="15" width="3" name="opcode">
          <c>1</c>
          <c>0</c>
          <c></c>
        </box>
        <box hibit="12" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ST1  </text><text>{</text><text> </text><a link="sa_vt" hover="First or only SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Vt&gt;</a><text>.D </text><text>}</text><text>[</text><a link="sa_index_1" hover="Element index (field &quot;Q&quot;)">&lt;index&gt;</a><text>], [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/memory/vector/single/no-wb" mylink="aarch64.instrs.memory.vector.single.no-wb" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = integer UNKNOWN;
boolean wback = FALSE;
boolean nontemporal = FALSE;
boolean tagchecked = wback || n != 31;</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="Post-index" oneof="2" id="iclass_as_post_index" no_encodings="8" isa="A64">
      <docvars>
        <docvar key="as-structure-post-index" value="as-post-index" />
        <docvar key="instr-class" value="advsimd" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="ST1" />
      </docvars>
      <iclassintro count="8"></iclassintro>
      <regdiagram form="32" psname="aarch64/instrs/memory/vector/single/post-inc" tworows="1">
        <box hibit="31" settings="1">
          <c>0</c>
        </box>
        <box hibit="30" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="29" width="7" settings="7">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="L" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="21" name="R" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="20" width="5" name="Rm" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" width="3" name="opcode" usename="1" settings="1" psbits="xxx">
          <c>x</c>
          <c>x</c>
          <c>0</c>
        </box>
        <box hibit="12" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rt" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="ST1_asisdlsop_B1_i1b" oneofinclass="8" oneof="12" label="8-bit, immediate offset" bitdiffs="Rm == 11111 &amp;&amp; opcode == 000">
        <docvars>
          <docvar key="as-structure-index-source" value="post-index-imm" />
          <docvar key="as-structure-org" value="of-bytes" />
          <docvar key="as-structure-post-index" value="as-post-index" />
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="ld1-single-labels" value="of-bytes-post-index-imm" />
          <docvar key="mnemonic" value="ST1" />
        </docvars>
        <box hibit="20" width="5" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="3" name="opcode">
          <c>0</c>
          <c>0</c>
          <c></c>
        </box>
        <asmtemplate><text>ST1  </text><text>{</text><text> </text><a link="sa_vt" hover="First or only SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Vt&gt;</a><text>.B </text><text>}</text><text>[</text><a link="sa_index" hover="Element index (field &quot;Q:S:size&quot;)">&lt;index&gt;</a><text>], [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>], #1</text></asmtemplate>
      </encoding>
      <encoding name="ST1_asisdlsop_BX1_r1b" oneofinclass="8" oneof="12" label="8-bit, register offset" bitdiffs="Rm != 11111 &amp;&amp; opcode == 000">
        <docvars>
          <docvar key="as-structure-index-source" value="post-index-reg" />
          <docvar key="as-structure-org" value="of-bytes" />
          <docvar key="as-structure-post-index" value="as-post-index" />
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="ld1-single-labels" value="of-bytes-post-index-reg" />
          <docvar key="mnemonic" value="ST1" />
        </docvars>
        <box hibit="20" width="5" name="Rm">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <box hibit="15" width="3" name="opcode">
          <c>0</c>
          <c>0</c>
          <c></c>
        </box>
        <asmtemplate><text>ST1  </text><text>{</text><text> </text><a link="sa_vt" hover="First or only SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Vt&gt;</a><text>.B </text><text>}</text><text>[</text><a link="sa_index" hover="Element index (field &quot;Q:S:size&quot;)">&lt;index&gt;</a><text>], [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>], </text><a link="sa_xm" hover="64-bit general-purpose post-index register, excluding XZR (field &quot;Rm&quot;)">&lt;Xm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="ST1_asisdlsop_H1_i1h" oneofinclass="8" oneof="12" label="16-bit, immediate offset" bitdiffs="Rm == 11111 &amp;&amp; opcode == 010 &amp;&amp; size == x0">
        <docvars>
          <docvar key="as-structure-index-source" value="post-index-imm" />
          <docvar key="as-structure-org" value="of-halfwords" />
          <docvar key="as-structure-post-index" value="as-post-index" />
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="ld1-single-labels" value="of-halfwords-post-index-imm" />
          <docvar key="mnemonic" value="ST1" />
        </docvars>
        <box hibit="20" width="5" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="3" name="opcode">
          <c>0</c>
          <c>1</c>
          <c></c>
        </box>
        <box hibit="11" width="2" name="size">
          <c></c>
          <c>0</c>
        </box>
        <asmtemplate><text>ST1  </text><text>{</text><text> </text><a link="sa_vt" hover="First or only SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Vt&gt;</a><text>.H </text><text>}</text><text>[</text><a link="sa_index_2" hover="Element index (field &quot;Q:S:size&lt;1&gt;&quot;)">&lt;index&gt;</a><text>], [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>], #2</text></asmtemplate>
      </encoding>
      <encoding name="ST1_asisdlsop_HX1_r1h" oneofinclass="8" oneof="12" label="16-bit, register offset" bitdiffs="Rm != 11111 &amp;&amp; opcode == 010 &amp;&amp; size == x0">
        <docvars>
          <docvar key="as-structure-index-source" value="post-index-reg" />
          <docvar key="as-structure-org" value="of-halfwords" />
          <docvar key="as-structure-post-index" value="as-post-index" />
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="ld1-single-labels" value="of-halfwords-post-index-reg" />
          <docvar key="mnemonic" value="ST1" />
        </docvars>
        <box hibit="20" width="5" name="Rm">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <box hibit="15" width="3" name="opcode">
          <c>0</c>
          <c>1</c>
          <c></c>
        </box>
        <box hibit="11" width="2" name="size">
          <c></c>
          <c>0</c>
        </box>
        <asmtemplate><text>ST1  </text><text>{</text><text> </text><a link="sa_vt" hover="First or only SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Vt&gt;</a><text>.H </text><text>}</text><text>[</text><a link="sa_index_2" hover="Element index (field &quot;Q:S:size&lt;1&gt;&quot;)">&lt;index&gt;</a><text>], [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>], </text><a link="sa_xm" hover="64-bit general-purpose post-index register, excluding XZR (field &quot;Rm&quot;)">&lt;Xm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="ST1_asisdlsop_S1_i1s" oneofinclass="8" oneof="12" label="32-bit, immediate offset" bitdiffs="Rm == 11111 &amp;&amp; opcode == 100 &amp;&amp; size == 00">
        <docvars>
          <docvar key="as-structure-index-source" value="post-index-imm" />
          <docvar key="as-structure-org" value="of-words" />
          <docvar key="as-structure-post-index" value="as-post-index" />
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="ld1-single-labels" value="of-words-post-index-imm" />
          <docvar key="mnemonic" value="ST1" />
        </docvars>
        <box hibit="20" width="5" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="3" name="opcode">
          <c>1</c>
          <c>0</c>
          <c></c>
        </box>
        <box hibit="11" width="2" name="size">
          <c>0</c>
          <c>0</c>
        </box>
        <asmtemplate><text>ST1  </text><text>{</text><text> </text><a link="sa_vt" hover="First or only SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Vt&gt;</a><text>.S </text><text>}</text><text>[</text><a link="sa_index_3" hover="Element index (field &quot;Q:S&quot;)">&lt;index&gt;</a><text>], [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>], #4</text></asmtemplate>
      </encoding>
      <encoding name="ST1_asisdlsop_SX1_r1s" oneofinclass="8" oneof="12" label="32-bit, register offset" bitdiffs="Rm != 11111 &amp;&amp; opcode == 100 &amp;&amp; size == 00">
        <docvars>
          <docvar key="as-structure-index-source" value="post-index-reg" />
          <docvar key="as-structure-org" value="of-words" />
          <docvar key="as-structure-post-index" value="as-post-index" />
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="ld1-single-labels" value="of-words-post-index-reg" />
          <docvar key="mnemonic" value="ST1" />
        </docvars>
        <box hibit="20" width="5" name="Rm">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <box hibit="15" width="3" name="opcode">
          <c>1</c>
          <c>0</c>
          <c></c>
        </box>
        <box hibit="11" width="2" name="size">
          <c>0</c>
          <c>0</c>
        </box>
        <asmtemplate><text>ST1  </text><text>{</text><text> </text><a link="sa_vt" hover="First or only SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Vt&gt;</a><text>.S </text><text>}</text><text>[</text><a link="sa_index_3" hover="Element index (field &quot;Q:S&quot;)">&lt;index&gt;</a><text>], [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>], </text><a link="sa_xm" hover="64-bit general-purpose post-index register, excluding XZR (field &quot;Rm&quot;)">&lt;Xm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="ST1_asisdlsop_D1_i1d" oneofinclass="8" oneof="12" label="64-bit, immediate offset" bitdiffs="Rm == 11111 &amp;&amp; opcode == 100 &amp;&amp; S == 0 &amp;&amp; size == 01">
        <docvars>
          <docvar key="as-structure-index-source" value="post-index-imm" />
          <docvar key="as-structure-org" value="of-doublewords" />
          <docvar key="as-structure-post-index" value="as-post-index" />
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="ld1-single-labels" value="of-doublewords-post-index-imm" />
          <docvar key="mnemonic" value="ST1" />
        </docvars>
        <box hibit="20" width="5" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="3" name="opcode">
          <c>1</c>
          <c>0</c>
          <c></c>
        </box>
        <box hibit="12" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ST1  </text><text>{</text><text> </text><a link="sa_vt" hover="First or only SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Vt&gt;</a><text>.D </text><text>}</text><text>[</text><a link="sa_index_1" hover="Element index (field &quot;Q&quot;)">&lt;index&gt;</a><text>], [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>], #8</text></asmtemplate>
      </encoding>
      <encoding name="ST1_asisdlsop_DX1_r1d" oneofinclass="8" oneof="12" label="64-bit, register offset" bitdiffs="Rm != 11111 &amp;&amp; opcode == 100 &amp;&amp; S == 0 &amp;&amp; size == 01">
        <docvars>
          <docvar key="as-structure-index-source" value="post-index-reg" />
          <docvar key="as-structure-org" value="of-doublewords" />
          <docvar key="as-structure-post-index" value="as-post-index" />
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="ld1-single-labels" value="of-doublewords-post-index-reg" />
          <docvar key="mnemonic" value="ST1" />
        </docvars>
        <box hibit="20" width="5" name="Rm">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <box hibit="15" width="3" name="opcode">
          <c>1</c>
          <c>0</c>
          <c></c>
        </box>
        <box hibit="12" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ST1  </text><text>{</text><text> </text><a link="sa_vt" hover="First or only SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Vt&gt;</a><text>.D </text><text>}</text><text>[</text><a link="sa_index_1" hover="Element index (field &quot;Q&quot;)">&lt;index&gt;</a><text>], [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>], </text><a link="sa_xm" hover="64-bit general-purpose post-index register, excluding XZR (field &quot;Rm&quot;)">&lt;Xm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/memory/vector/single/post-inc" mylink="aarch64.instrs.memory.vector.single.post-inc" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
boolean wback = TRUE;
boolean nontemporal = FALSE;
boolean tagchecked = wback || n != 31;</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ST1_asisdlso_B1_1b, ST1_asisdlso_D1_1d, ST1_asisdlso_H1_1h, ST1_asisdlso_S1_1s, ST1_asisdlsop_B1_i1b, ST1_asisdlsop_D1_i1d, ST1_asisdlsop_H1_i1h, ST1_asisdlsop_S1_i1s, ST1_asisdlsop_BX1_r1b, ST1_asisdlsop_DX1_r1d, ST1_asisdlsop_HX1_r1h, ST1_asisdlsop_SX1_r1s" symboldefcount="1">
      <symbol link="sa_vt">&lt;Vt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the name of the first or only SIMD&amp;FP register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ST1_asisdlso_B1_1b, ST1_asisdlsop_B1_i1b, ST1_asisdlsop_BX1_r1b" symboldefcount="1">
      <symbol link="sa_index">&lt;index&gt;</symbol>
      <account encodedin="Q:S:size">
        <docvars>
          <docvar key="as-structure-org" value="of-bytes" />
        </docvars>
        <intro>
          <para>For the 8-bit variant: is the element index, encoded in "Q:S:size".</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ST1_asisdlso_H1_1h, ST1_asisdlsop_H1_i1h, ST1_asisdlsop_HX1_r1h" symboldefcount="2">
      <symbol link="sa_index_2">&lt;index&gt;</symbol>
      <account encodedin="Q:S:size">
        <docvars>
          <docvar key="as-structure-org" value="of-halfwords" />
        </docvars>
        <intro>
          <para>For the 16-bit variant: is the element index, encoded in "Q:S:size&lt;1&gt;".</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ST1_asisdlso_S1_1s, ST1_asisdlsop_S1_i1s, ST1_asisdlsop_SX1_r1s" symboldefcount="3">
      <symbol link="sa_index_3">&lt;index&gt;</symbol>
      <account encodedin="Q:S">
        <docvars>
          <docvar key="as-structure-org" value="of-words" />
        </docvars>
        <intro>
          <para>For the 32-bit variant: is the element index, encoded in "Q:S".</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ST1_asisdlso_D1_1d, ST1_asisdlsop_D1_i1d, ST1_asisdlsop_DX1_r1d" symboldefcount="4">
      <symbol link="sa_index_1">&lt;index&gt;</symbol>
      <account encodedin="Q">
        <docvars>
          <docvar key="as-structure-org" value="of-doublewords" />
        </docvars>
        <intro>
          <para>For the 64-bit variant: is the element index, encoded in "Q".</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ST1_asisdlso_B1_1b, ST1_asisdlso_D1_1d, ST1_asisdlso_H1_1h, ST1_asisdlso_S1_1s, ST1_asisdlsop_B1_i1b, ST1_asisdlsop_D1_i1d, ST1_asisdlsop_H1_i1h, ST1_asisdlsop_S1_i1s, ST1_asisdlsop_BX1_r1b, ST1_asisdlsop_DX1_r1d, ST1_asisdlsop_HX1_r1h, ST1_asisdlsop_SX1_r1s" symboldefcount="1">
      <symbol link="sa_xn_sp">&lt;Xn|SP&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ST1_asisdlsop_BX1_r1b, ST1_asisdlsop_DX1_r1d, ST1_asisdlsop_HX1_r1h, ST1_asisdlsop_SX1_r1s" symboldefcount="1">
      <symbol link="sa_xm">&lt;Xm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/memory/vector/single/no-wb" mylink="postdecode" enclabels="" sections="1" secttype="Shared Decode">
      <pstext mayhavelinks="1" section="Postdecode" rep_section="postdecode">integer init_scale = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opcode&lt;2:1&gt;);
integer scale = init_scale;
integer selem = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opcode&lt;0&gt;:R) + 1;
boolean replicate = FALSE;
integer index;

case scale of
    when 3
        // load and replicate
        if L == '0' || S == '1' then UNDEFINED;
        scale = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
        replicate = TRUE;
    when 0
        index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Q:S:size);       // B[0-15]
    when 1
        if size&lt;0&gt; == '1' then UNDEFINED;
        index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Q:S:size&lt;1&gt;);    // H[0-7]
    when 2
        if size&lt;1&gt; == '1' then UNDEFINED;
        if size&lt;0&gt; == '0' then
            index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Q:S);        // S[0-3]
        else
            if S == '1' then UNDEFINED;
            index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Q);          // D[0-1]
            scale = 3;

<a link="MemOp" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop = if L == '1' then <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> else <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;
integer datasize = if Q == '1' then 128 else 64;
integer esize = 8 &lt;&lt; scale;</pstext>
    </ps>
  </ps_section>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/memory/vector/single/no-wb" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();

bits(64) address;
bits(64) offs;
bits(128) rval;
bits(esize) element;
constant integer ebytes = esize DIV 8;

<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescASIMD.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(memop, nontemporal, tagchecked);

if n == 31 then
    <a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
    address = <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[];
else
    address = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];

offs = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);
if replicate then
    // load and replicate to all elements
    for s = 0 to selem-1
        element = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[address + offs, ebytes, accdesc];
        // replicate to fill 128- or 64-bit register
        <a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[t, datasize] = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
        offs = offs + ebytes;
        t = (t + 1) MOD 32;
else
    // load/store one element per register
    for s = 0 to selem-1
        rval = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[t, 128];
        if memop == <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
            // insert into one lane of 128-bit register
            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[address + offs, ebytes, accdesc];
            <a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[t, 128] = rval;
        else // memop == MemOp_STORE
            // extract from one lane of 128-bit register
            Mem[address + offs, ebytes, accdesc] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
        offs = offs + ebytes;
        t = (t + 1) MOD 32;

if wback then
    if m != 31 then
        offs = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[m, 64];
    if n == 31 then
        <a link="impl-aarch64.SP.write.0" file="shared_pseudocode.xml" hover="accessor: SP[] = bits(64) value">SP</a>[] = address + offs;
    else
        <a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[n, 64] = address + offs;</pstext>
    </ps>
  </ps_section>
</instructionsection>
