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<instructionsection id="RORV" title="RORV -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="RORV" />
  </docvars>
  <heading>RORV</heading>
  <desc>
    <brief>
      <para>Rotate Right Variable</para>
    </brief>
    <authored>
      <para>Rotate Right Variable provides the value of the contents of a register rotated by a variable number of bits. The bits that are rotated off the right end are inserted into the vacated bit positions on the left. The remainder obtained by dividing the second source register by the data size defines the number of bits by which the first source register is right-shifted.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If PSTATE.DIT is 1:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="1">
    <alias_list_intro>This instruction is used by the alias </alias_list_intro>
    <aliasref aliaspageid="ROR_RORV" aliasfile="ror_rorv.xml" hover="Rotate right (register)" punct=".">
      <text>ROR (register)</text>
      <aliaspref>Unconditionally</aliaspref>
    </aliasref>
    <alias_list_outro> The alias is always the preferred disassembly.</alias_list_outro>
  </alias_list>
  <classes>
    <iclass name="Integer" oneof="1" id="iclass_general" no_encodings="2" isa="A64">
      <docvars>
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="RORV" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch64/instrs/integer/shift/variable" tworows="1">
        <box hibit="31" name="sf" usename="1">
          <c></c>
        </box>
        <box hibit="30" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="29" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="28" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" width="5" name="Rm" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" width="4" name="opcode2[5:2]" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="11" width="2" name="op2" usename="1" settings="2" psbits="xx">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="RORV_32_dp_2src" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0">
        <docvars>
          <docvar key="datatype" value="32" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="RORV" />
        </docvars>
        <box hibit="31" width="1" name="sf">
          <c>0</c>
        </box>
        <asmtemplate><text>RORV  </text><a link="sa_wd" hover="32-bit general-purpose destination register (field &quot;Rd&quot;)">&lt;Wd&gt;</a><text>, </text><a link="sa_wn" hover="First 32-bit general-purpose source register (field &quot;Rn&quot;)">&lt;Wn&gt;</a><text>, </text><a link="sa_wm" hover="Second 32-bit general-purpose source register holding a shift amount from 0 to 31 in its bottom 5 bits (field &quot;Rm&quot;)">&lt;Wm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="RORV_64_dp_2src" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
        <docvars>
          <docvar key="datatype" value="64" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="RORV" />
        </docvars>
        <box hibit="31" width="1" name="sf">
          <c>1</c>
        </box>
        <asmtemplate><text>RORV  </text><a link="sa_xd" hover="64-bit general-purpose destination register (field &quot;Rd&quot;)">&lt;Xd&gt;</a><text>, </text><a link="sa_xn" hover="First 64-bit general-purpose source register (field &quot;Rn&quot;)">&lt;Xn&gt;</a><text>, </text><a link="sa_xm" hover="Second 64-bit general-purpose source register holding a shift amount from 0 to 63 in its bottom 6 bits (field &quot;Rm&quot;)">&lt;Xm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/integer/shift/variable" mylink="aarch64.instrs.integer.shift.variable" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
integer datasize = if sf == '1' then 64 else 32;
<a link="ShiftType" file="shared_pseudocode.xml" hover="enumeration ShiftType   {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR}">ShiftType</a> shift_type = <a link="impl-aarch64.DecodeShift.1" file="shared_pseudocode.xml" hover="function: ShiftType DecodeShift(bits(2) op)">DecodeShift</a>(op2);</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="RORV_32_dp_2src" symboldefcount="1">
      <symbol link="sa_wd">&lt;Wd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RORV_32_dp_2src" symboldefcount="1">
      <symbol link="sa_wn">&lt;Wn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RORV_32_dp_2src" symboldefcount="1">
      <symbol link="sa_wm">&lt;Wm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 32-bit name of the second general-purpose source register holding a shift amount from 0 to 31 in its bottom 5 bits, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RORV_64_dp_2src" symboldefcount="1">
      <symbol link="sa_xd">&lt;Xd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RORV_64_dp_2src" symboldefcount="1">
      <symbol link="sa_xn">&lt;Xn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RORV_64_dp_2src" symboldefcount="1">
      <symbol link="sa_xm">&lt;Xm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 64-bit name of the second general-purpose source register holding a shift amount from 0 to 63 in its bottom 6 bits, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/integer/shift/variable" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(datasize) result;
bits(datasize) operand2 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[m, datasize];

result = <a link="impl-aarch64.ShiftReg.4" file="shared_pseudocode.xml" hover="function: bits(N) ShiftReg(integer reg, ShiftType shiftype, integer amount, integer N)">ShiftReg</a>(n, shift_type, <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(operand2) MOD datasize, datasize);
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, datasize] = result;</pstext>
    </ps>
  </ps_section>
</instructionsection>
