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<instructionsection id="STLRB" title="STLRB -- A64" type="instruction">
  <docvars>
    <docvar key="address-form" value="base-register" />
    <docvar key="address-form-reg-type" value="base-register-32-reg" />
    <docvar key="atomic-ops" value="STLRB-32-reg" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="STLRB" />
    <docvar key="reg-type" value="32-reg" />
  </docvars>
  <heading>STLRB</heading>
  <desc>
    <brief>
      <para>Store-Release Register Byte</para>
    </brief>
    <authored>
      <para>Store-Release Register Byte stores a byte from a 32-bit register to a memory location. The instruction also has memory ordering semantics as described in <xref linkend="BEIHCHEF">Load-Acquire, Store-Release</xref>. For information about memory accesses, see <xref linkend="CHDIIIBB">Load/Store addressing modes</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="No offset" oneof="1" id="iclass_base_register" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="address-form" value="base-register" />
        <docvar key="address-form-reg-type" value="base-register-32-reg" />
        <docvar key="atomic-ops" value="STLRB-32-reg" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="STLRB" />
        <docvar key="reg-type" value="32-reg" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch64/instrs/memory/ordered" tworows="1">
        <box hibit="31" width="2" name="size" usename="1" settings="2" psbits="xx">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="29" width="6" settings="6">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o2" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="L" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="21" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" width="5" name="Rs" usename="1" settings="5" psbits="xxxxx">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="15" name="o0" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="14" width="5" name="Rt2" usename="1" settings="5" psbits="xxxxx">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rt" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="STLRB_SL32_ldstord" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="address-form" value="base-register" />
          <docvar key="address-form-reg-type" value="base-register-32-reg" />
          <docvar key="atomic-ops" value="STLRB-32-reg" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="STLRB" />
          <docvar key="reg-type" value="32-reg" />
        </docvars>
        <asmtemplate><text>STLRB  </text><a link="sa_wt" hover="32-bit general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Wt&gt;</a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a><text>{,#0}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/memory/ordered" mylink="aarch64.instrs.memory.ordered" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);
integer t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt2); // ignored by load/store single register
integer s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);   // ignored by all loads and store-release
boolean wback = FALSE;
integer offset   = 0;
boolean rt_unknown = FALSE;

limitedordered = o0 == '0';

<a link="MemOp" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop = if L == '1' then <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> else <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;
integer elsize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
integer regsize = if elsize == 64 then 64 else 32;
integer datasize = elsize;
boolean tagchecked = n != 31;</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STLRB_SL32_ldstord" symboldefcount="1">
      <symbol link="sa_wt">&lt;Wt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLRB_SL32_ldstord" symboldefcount="1">
      <symbol link="sa_xn_sp">&lt;Xn|SP&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/memory/ordered" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(64) address;
bits(datasize) data;
constant integer dbytes = datasize DIV 8;

<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc;
if limitedordered then
    accdesc = <a link="impl-shared.CreateAccDescLOR.2" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescLOR(MemOp memop, boolean tagchecked)">CreateAccDescLOR</a>(memop, tagchecked);
else
    accdesc = <a link="impl-shared.CreateAccDescAcqRel.2" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescAcqRel(MemOp memop, boolean tagchecked)">CreateAccDescAcqRel</a>(memop, tagchecked);

if n == 31 then
    <a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
    address = <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[];
else
    address = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];

case memop of
    when <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>
        address = address + offset;
        if rt_unknown then
            data = bits(datasize) UNKNOWN;
        else
            data = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[t, datasize];
        Mem[address, dbytes, accdesc] = data;

        if wback then
            if n == 31 then
                <a link="impl-aarch64.SP.write.0" file="shared_pseudocode.xml" hover="accessor: SP[] = bits(64) value">SP</a>[] = address;
            else
                <a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[n, 64] = address;
    when <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>
        data = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[address, dbytes, accdesc];
        <a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[t, regsize] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(data, regsize);</pstext>
    </ps>
  </ps_section>
</instructionsection>
