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<instructionsection id="TTEST" title="TTEST -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="system" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="TTEST" />
  </docvars>
  <heading>TTEST</heading>
  <desc>
    <brief>
      <para>Test transaction state</para>
    </brief>
    <authored>
      <para>This instruction writes the depth of the transaction to the destination register, or the value 0 otherwise.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="System" oneof="1" id="iclass_system" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="system" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="TTEST" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="FEAT_TME" feature="FEAT_TME" />
      </arch_variants>
      <regdiagram form="32" psname="aarch64/instrs/system/tme/ttest">
        <box hibit="31" width="10" settings="10">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="2" name="op0" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="CRn" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="CRm" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" width="3" name="op2" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" width="5" name="Rt" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="TTEST_BR_systemresult" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="instr-class" value="system" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="TTEST" />
        </docvars>
        <asmtemplate><text>TTEST  </text><a link="sa_xt" hover="64-bit general-purpose destination register (field &quot;Rt&quot;)">&lt;Xt&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/system/tme/ttest" mylink="aarch64.instrs.system.tme.ttest" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() then UNDEFINED;
integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="TTEST_BR_systemresult" symboldefcount="1">
      <symbol link="sa_xt">&lt;Xt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/system/tme/ttest" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if !<a link="impl-aarch64.IsTMEEnabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTMEEnabled()">IsTMEEnabled</a>() then UNDEFINED;

<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[t, 64] = (TSTATE.depth)&lt;63:0&gt;;</pstext>
    </ps>
  </ps_section>
</instructionsection>
