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<instructionsection id="FMULX_advsimd_vec" title="FMULX -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="advsimd" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="FMULX" />
  </docvars>
  <heading>FMULX</heading>
  <desc>
    <brief>
      <para>Floating-point Multiply extended</para>
    </brief>
    <authored>
      <para>Floating-point Multiply extended. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&amp;FP registers, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&amp;FP register.</para>
      <para>If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.</para>
      <para>This instruction can generate a floating-point exception. Depending on the settings in <xref linkend="AArch64.fpcr">FPCR</xref>, the exception results in either a flag being set in <xref linkend="AArch64.fpsr">FPSR</xref>, or a synchronous exception being generated. For more information, see <xref linkend="BEIJDDAG">Floating-point exception traps</xref>.</para>
      <para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from 4 classes:</txt>
      <a href="#iclass_sisd_half">Scalar half precision</a>
      <txt>, </txt>
      <a href="#iclass_sisd_single_and_double">Scalar single-precision and double-precision</a>
      <txt>, </txt>
      <a href="#iclass_simd_half">Vector half precision</a>
      <txt> and </txt>
      <a href="#iclass_simd_single_and_double">Vector single-precision and double-precision</a>
    </classesintro>
    <iclass name="Scalar half precision" oneof="4" id="iclass_sisd_half" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="advsimd-datatype" value="sisd-half" />
        <docvar key="advsimd-type" value="sisd" />
        <docvar key="datatype" value="half" />
        <docvar key="instr-class" value="advsimd" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="FMULX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
      </arch_variants>
      <regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/binary/uniform/mul/fp16/extended/sisd">
        <box hibit="31" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="29" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="28" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="a" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" width="5" name="Rm" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="13" width="3" name="opcode" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="10" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="FMULX_asisdsamefp16_only" oneofinclass="1" oneof="4" label="">
        <docvars>
          <docvar key="advsimd-datatype" value="sisd-half" />
          <docvar key="advsimd-type" value="sisd" />
          <docvar key="datatype" value="half" />
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FMULX" />
        </docvars>
        <asmtemplate><text>FMULX  </text><a link="sa_hd" hover="16-bit SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Hd&gt;</a><text>, </text><a link="sa_hn" hover="First 16-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Hn&gt;</a><text>, </text><a link="sa_hm" hover="Second 16-bit SIMD&amp;FP source register (field &quot;Rm&quot;)">&lt;Hm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/vector/arithmetic/binary/uniform/mul/fp16/extended/sisd" mylink="aarch64.instrs.vector.arithmetic.binary.uniform.mul.fp16.extended.sisd" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;

integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
integer esize = 16;
integer datasize = esize;
integer elements = 1;</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="Scalar single-precision and double-precision" oneof="4" id="iclass_sisd_single_and_double" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="advsimd-datatype" value="sisd-single-and-double" />
        <docvar key="advsimd-type" value="sisd" />
        <docvar key="datatype" value="single-and-double" />
        <docvar key="instr-class" value="advsimd" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="FMULX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/binary/uniform/mul/fp/extended/sisd">
        <box hibit="31" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="29" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="28" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="size[1]" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="5" name="Rm" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" width="5" name="opcode" settings="5">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="10" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="FMULX_asisdsame_only" oneofinclass="1" oneof="4" label="">
        <docvars>
          <docvar key="advsimd-datatype" value="sisd-single-and-double" />
          <docvar key="advsimd-type" value="sisd" />
          <docvar key="datatype" value="single-and-double" />
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FMULX" />
        </docvars>
        <asmtemplate><text>FMULX  </text><a link="sa_v" hover="Width specifier (field &quot;sz&quot;) [D,S]">&lt;V&gt;</a><a link="sa_d" hover="SIMD&amp;FP destination register number (field &quot;Rd&quot;)">&lt;d&gt;</a><text>, </text><a link="sa_v" hover="Width specifier (field &quot;sz&quot;) [D,S]">&lt;V&gt;</a><a link="sa_n" hover="First SIMD&amp;FP source register number (field &quot;Rn&quot;)">&lt;n&gt;</a><text>, </text><a link="sa_v" hover="Width specifier (field &quot;sz&quot;) [D,S]">&lt;V&gt;</a><a link="sa_m" hover="Second SIMD&amp;FP source register number (field &quot;Rm&quot;)">&lt;m&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/vector/arithmetic/binary/uniform/mul/fp/extended/sisd" mylink="aarch64.instrs.vector.arithmetic.binary.uniform.mul.fp.extended.sisd" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
integer esize = 32 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
integer datasize = esize;
integer elements = 1;</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="Vector half precision" oneof="4" id="iclass_simd_half" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="advsimd-datatype" value="simd-half" />
        <docvar key="advsimd-reguse" value="3reg-same" />
        <docvar key="advsimd-type" value="simd" />
        <docvar key="datatype" value="half" />
        <docvar key="instr-class" value="advsimd" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="FMULX" />
        <docvar key="reguse-datatype" value="3reg-same-half" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
      </arch_variants>
      <regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/binary/uniform/mul/fp16/extended/simd">
        <box hibit="31" settings="1">
          <c>0</c>
        </box>
        <box hibit="30" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="29" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="28" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="a" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" width="5" name="Rm" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="13" width="3" name="opcode" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="10" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="FMULX_asimdsamefp16_only" oneofinclass="1" oneof="4" label="">
        <docvars>
          <docvar key="advsimd-datatype" value="simd-half" />
          <docvar key="advsimd-reguse" value="3reg-same" />
          <docvar key="advsimd-type" value="simd" />
          <docvar key="datatype" value="half" />
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FMULX" />
          <docvar key="reguse-datatype" value="3reg-same-half" />
        </docvars>
        <asmtemplate><text>FMULX  </text><a link="sa_vd" hover="SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Vd&gt;</a><text>.</text><a link="sa_t_1" hover="Arrangement specifier (field &quot;Q&quot;) [4H,8H]">&lt;T&gt;</a><text>, </text><a link="sa_vn" hover="First SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Vn&gt;</a><text>.</text><a link="sa_t_1" hover="Arrangement specifier (field &quot;Q&quot;) [4H,8H]">&lt;T&gt;</a><text>, </text><a link="sa_vm" hover="Second SIMD&amp;FP source register (field &quot;Rm&quot;)">&lt;Vm&gt;</a><text>.</text><a link="sa_t_1" hover="Arrangement specifier (field &quot;Q&quot;) [4H,8H]">&lt;T&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/vector/arithmetic/binary/uniform/mul/fp16/extended/simd" mylink="aarch64.instrs.vector.arithmetic.binary.uniform.mul.fp16.extended.simd" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;

integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
integer esize = 16;
integer datasize = if Q == '1' then 128 else 64;
integer elements = datasize DIV esize;</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="Vector single-precision and double-precision" oneof="4" id="iclass_simd_single_and_double" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="advsimd-datatype" value="simd-single-and-double" />
        <docvar key="advsimd-reguse" value="3reg-same" />
        <docvar key="advsimd-type" value="simd" />
        <docvar key="datatype" value="single-and-double" />
        <docvar key="instr-class" value="advsimd" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="FMULX" />
        <docvar key="reguse-datatype" value="3reg-same-single-and-double" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/binary/uniform/mul/fp/extended/simd">
        <box hibit="31" settings="1">
          <c>0</c>
        </box>
        <box hibit="30" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="29" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="28" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="size[1]" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="5" name="Rm" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" width="5" name="opcode" settings="5">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="10" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="FMULX_asimdsame_only" oneofinclass="1" oneof="4" label="">
        <docvars>
          <docvar key="advsimd-datatype" value="simd-single-and-double" />
          <docvar key="advsimd-reguse" value="3reg-same" />
          <docvar key="advsimd-type" value="simd" />
          <docvar key="datatype" value="single-and-double" />
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="FMULX" />
          <docvar key="reguse-datatype" value="3reg-same-single-and-double" />
        </docvars>
        <asmtemplate><text>FMULX  </text><a link="sa_vd" hover="SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Vd&gt;</a><text>.</text><a link="sa_t" hover="Arrangement specifier (field &quot;sz:Q&quot;) [2D,2S,4S]">&lt;T&gt;</a><text>, </text><a link="sa_vn" hover="First SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Vn&gt;</a><text>.</text><a link="sa_t" hover="Arrangement specifier (field &quot;sz:Q&quot;) [2D,2S,4S]">&lt;T&gt;</a><text>, </text><a link="sa_vm" hover="Second SIMD&amp;FP source register (field &quot;Rm&quot;)">&lt;Vm&gt;</a><text>.</text><a link="sa_t" hover="Arrangement specifier (field &quot;sz:Q&quot;) [2D,2S,4S]">&lt;T&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/vector/arithmetic/binary/uniform/mul/fp/extended/simd" mylink="aarch64.instrs.vector.arithmetic.binary.uniform.mul.fp.extended.simd" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
if sz:Q == '10' then UNDEFINED;
integer esize = 32 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
integer datasize = if Q == '1' then 128 else 64;
integer elements = datasize DIV esize;</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="FMULX_asisdsamefp16_only" symboldefcount="1">
      <symbol link="sa_hd">&lt;Hd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 16-bit name of the SIMD&amp;FP destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMULX_asisdsamefp16_only" symboldefcount="1">
      <symbol link="sa_hn">&lt;Hn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 16-bit name of the first SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMULX_asisdsamefp16_only" symboldefcount="1">
      <symbol link="sa_hm">&lt;Hm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 16-bit name of the second SIMD&amp;FP source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMULX_asisdsame_only" symboldefcount="1">
      <symbol link="sa_v">&lt;V&gt;</symbol>
      <definition encodedin="sz">
        <intro>Is a width specifier, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;V&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">S</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">D</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="FMULX_asisdsame_only" symboldefcount="1">
      <symbol link="sa_d">&lt;d&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the number of the SIMD&amp;FP destination register, in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMULX_asisdsame_only" symboldefcount="1">
      <symbol link="sa_n">&lt;n&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the number of the first SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMULX_asisdsame_only" symboldefcount="1">
      <symbol link="sa_m">&lt;m&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the number of the second SIMD&amp;FP source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMULX_asimdsame_only, FMULX_asimdsamefp16_only" symboldefcount="1">
      <symbol link="sa_vd">&lt;Vd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the name of the SIMD&amp;FP destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMULX_asimdsamefp16_only" symboldefcount="1">
      <symbol link="sa_t_1">&lt;T&gt;</symbol>
      <definition encodedin="Q">
        <intro>For the half-precision variant: is an arrangement specifier, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">Q</entry>
                <entry class="symbol">&lt;T&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">4H</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">8H</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="FMULX_asimdsame_only" symboldefcount="2">
      <symbol link="sa_t">&lt;T&gt;</symbol>
      <definition encodedin="sz:Q">
        <intro>For the single-precision and double-precision variant: is an arrangement specifier, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="bitfield">Q</entry>
                <entry class="symbol">&lt;T&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">2S</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">4S</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">2D</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="FMULX_asimdsame_only, FMULX_asimdsamefp16_only" symboldefcount="1">
      <symbol link="sa_vn">&lt;Vn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the name of the first SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FMULX_asimdsame_only, FMULX_asimdsamefp16_only" symboldefcount="1">
      <symbol link="sa_vm">&lt;Vm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the name of the second SIMD&amp;FP source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/vector/arithmetic/binary/uniform/mul/fp16/extended/sisd" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if elements == 1 then
    <a link="impl-aarch64.CheckFPEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPEnabled64()">CheckFPEnabled64</a>();
else
    <a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
bits(datasize) operand1 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, datasize];
bits(datasize) operand2 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[m, datasize];

bits(esize) element1;
bits(esize) element2;
<a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr    = FPCR[];
boolean merge    = elements == 1 &amp;&amp; <a link="impl-shared.IsMerging.1" file="shared_pseudocode.xml" hover="function: boolean IsMerging(FPCRType fpcr)">IsMerging</a>(fpcr);
bits(128) result = if merge then <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, 128] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(128);

for e = 0 to elements-1
    element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
    element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.FPMulX.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMulX(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulX</a>(element1, element2, fpcr);
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = result;</pstext>
    </ps>
  </ps_section>
</instructionsection>
