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<instructionsection id="MOV_dup_z_zi" title="MOV (SIMD&amp;FP scalar, unpredicated)" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="MOV" />
    <docvar key="instr-class" value="sve" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="DUP" />
  </docvars>
  <heading>MOV (SIMD&amp;FP scalar, unpredicated)</heading>
  <desc>
    <brief>Move indexed element or SIMD&amp;FP scalar to vector (unpredicated)</brief>
    <description>
      <para>Unconditionally broadcast the SIMD&amp;FP scalar into each element of the destination vector. This instruction is unpredicated.</para>
    </description>
    <status>Green</status>
    <predicated>False</predicated>
    <uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
  </desc>
  <aliasto refiform="dup_z_zi.xml" iformid="dup_z_zi">DUP (indexed)</aliasto>
  <classes>
    <iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="2" isa="A64">
      <docvars>
        <docvar key="instr-class" value="sve" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="DUP" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="DUP-Z.Zi-_">
        <box hibit="31" width="8" settings="8">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="23" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="5" name="tsz" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" width="6" settings="6">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Zn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Zd" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="MOV_dup_z_zi_" oneofinclass="4" oneof="2" label="">
        <docvars>
          <docvar key="alias_mnemonic" value="MOV" />
          <docvar key="instr-class" value="sve" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="DUP" />
        </docvars>
        <asmtemplate><text>MOV     </text><a link="sa_zd" hover="Destination scalable vector register (field &quot;Zd&quot;)">&lt;Zd&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;tsz&quot;) [B,D,H,Q,S]">&lt;T&gt;</a><text>, </text><a link="sa_zn" hover="Source scalable vector register (field &quot;Zn&quot;)">&lt;Zn&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;tsz&quot;) [B,D,H,Q,S]">&lt;T&gt;</a><text>[</text><a link="sa_imm" hover="Immediate index [0-one less than the number of elements in 512 bits] (field &quot;imm2:tsz&quot;)">&lt;imm&gt;</a><text>]</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="dup_z_zi.xml#dup_z_zi_">DUP</a><text>     </text><a link="sa_zd" hover="Destination scalable vector register (field &quot;Zd&quot;)">&lt;Zd&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;tsz&quot;) [B,D,H,Q,S]">&lt;T&gt;</a><text>, </text><a link="sa_zn" hover="Source scalable vector register (field &quot;Zn&quot;)">&lt;Zn&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;tsz&quot;) [B,D,H,Q,S]">&lt;T&gt;</a><text>[</text><a link="sa_imm" hover="Immediate index [0-one less than the number of elements in 512 bits] (field &quot;imm2:tsz&quot;)">&lt;imm&gt;</a><text>]</text></asmtemplate>
          <aliascond><a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(imm2:tsz) &gt; 1</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="MOV_dup_z_zi_" oneofinclass="4" oneof="2" label="">
        <docvars>
          <docvar key="alias_mnemonic" value="MOV" />
          <docvar key="instr-class" value="sve" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="DUP" />
        </docvars>
        <asmtemplate><text>MOV     </text><a link="sa_zd" hover="Destination scalable vector register (field &quot;Zd&quot;)">&lt;Zd&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;tsz&quot;) [B,D,H,Q,S]">&lt;T&gt;</a><text>, </text><a link="sa_v" hover="Width specifier (field &quot;tsz&quot;) [B,D,H,Q,S]">&lt;V&gt;</a><a link="sa_n" hover="Source SIMD&amp;FP register number [0-31] (field &quot;Zn&quot;)">&lt;n&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="dup_z_zi.xml#dup_z_zi_">DUP</a><text> </text><a link="sa_zd" hover="Destination scalable vector register (field &quot;Zd&quot;)">&lt;Zd&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;tsz&quot;) [B,D,H,Q,S]">&lt;T&gt;</a><text>, </text><a link="sa_zn" hover="Source scalable vector register (field &quot;Zn&quot;)">&lt;Zn&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;tsz&quot;) [B,D,H,Q,S]">&lt;T&gt;</a><text>[0]</text></asmtemplate>
          <aliascond><a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(imm2:tsz) == 1</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="" oneofinclass="4" oneof="2" label="">
        <asmtemplate></asmtemplate>
      </encoding>
      <encoding name="" oneofinclass="4" oneof="2" label="">
        <asmtemplate></asmtemplate>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="MOV_dup_z_zi_, MOV_dup_z_zi_" symboldefcount="1">
      <symbol link="sa_zd">&lt;Zd&gt;</symbol>
      <account encodedin="Zd">
        <intro>
          <para>Is the name of the destination scalable vector register, encoded in the "Zd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_dup_z_zi_, MOV_dup_z_zi_" symboldefcount="1">
      <symbol link="sa_t">&lt;T&gt;</symbol>
      <definition encodedin="tsz">
        <intro>Is the size specifier, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">tsz</entry>
                <entry class="symbol">&lt;T&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00000</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">xxxx1</entry>
                <entry class="symbol">B</entry>
              </row>
              <row>
                <entry class="bitfield">xxx10</entry>
                <entry class="symbol">H</entry>
              </row>
              <row>
                <entry class="bitfield">xx100</entry>
                <entry class="symbol">S</entry>
              </row>
              <row>
                <entry class="bitfield">x1000</entry>
                <entry class="symbol">D</entry>
              </row>
              <row>
                <entry class="bitfield">10000</entry>
                <entry class="symbol">Q</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="MOV_dup_z_zi_" symboldefcount="1">
      <symbol link="sa_zn">&lt;Zn&gt;</symbol>
      <account encodedin="Zn">
        <intro>
          <para>Is the name of the source scalable vector register, encoded in the "Zn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_dup_z_zi_" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm2:tsz">
        <intro>
          <para>Is the immediate index, in the range 0 to one less than the number of elements in 512 bits, encoded in "imm2:tsz".</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_dup_z_zi_" symboldefcount="1">
      <symbol link="sa_v">&lt;V&gt;</symbol>
      <definition encodedin="tsz">
        <intro>Is a width specifier, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">tsz</entry>
                <entry class="symbol">&lt;V&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00000</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">xxxx1</entry>
                <entry class="symbol">B</entry>
              </row>
              <row>
                <entry class="bitfield">xxx10</entry>
                <entry class="symbol">H</entry>
              </row>
              <row>
                <entry class="bitfield">xx100</entry>
                <entry class="symbol">S</entry>
              </row>
              <row>
                <entry class="bitfield">x1000</entry>
                <entry class="symbol">D</entry>
              </row>
              <row>
                <entry class="bitfield">10000</entry>
                <entry class="symbol">Q</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="MOV_dup_z_zi_" symboldefcount="1">
      <symbol link="sa_n">&lt;n&gt;</symbol>
      <account encodedin="Zn">
        <intro>
          <para>Is the number [0-31] of the source SIMD&amp;FP register, encoded in the "Zn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
