Commit Graph

27 Commits

Author SHA1 Message Date
Ronald Caesar
99f4afb9fc docs: add handling arrays in programming rules
Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-13 20:57:16 -04:00
Ronald Caesar
6e4c1edfda docs: add programming rules
Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-13 20:32:41 -04:00
Ronald Caesar
e9ec38bcfd docs: add template files
These template files come from the Barr C style guide.

Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-09 18:23:35 -04:00
Ronald Caesar
6cf4df24bf docs: add table of contents
Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-09 17:26:45 -04:00
Ronald Caesar
74aa9be671 docs: Update outdated instruction operand width
Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-09 17:17:13 -04:00
Ronald Caesar
bf146b681a docs: Add initial static assumption implementation
Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-08 19:53:52 -04:00
Ronald Caesar
2778c94a15 docs: Split ssa_versions[]
Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-08 19:25:26 -04:00
Ronald Caesar
f97fcf7df9 docs: Add scenario to extension instruction
This accidentally got removed in previous commits

Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-08 18:58:01 -04:00
Ronald Caesar
317c33b557 docs: Fix incorrect block limit statement
Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-08 18:54:05 -04:00
Ronald Caesar
8b642a1e9f docs: Add limitations to extention instruction
Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-08 18:50:52 -04:00
Ronald Caesar
624505af17 docs: Switch instruction and instruction encoding sections
Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-08 18:25:05 -04:00
Ronald Caesar
4115204ab9 docs: Shrink instruction_t operands by one
Having 18-bit opcodes means a block has at most 131,072 instructions
which is simply too big. All of these instructions cannot fit into the
L1 cache, which results in cache thrashing.

Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-08 18:18:32 -04:00
Ronald Caesar
e7a8a873e6 docs: Replace ssa_version_t type attribute
We have enough bits in the opcode bitfield in instruction_t
to encode register classes (ADD_INT, ADD_FLOAT, ADD_VECTOR). However,
encoding the bit width (ADD_INT8, ADD_INT32) will massively increase the
amount of opcodes needed. So we replace `type` in ssa_version_t with
`bit_width`.

Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-08 18:09:07 -04:00
Ronald Caesar
fde3d195bd docs: Replace def extensions with block args
Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-08 17:52:25 -04:00
Ronald Caesar
e002fbcc6a docs: Add block size limit rule
Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-06 18:37:36 -04:00
Ronald Caesar
020aa8dca8 docs: Fix Hot-Cold Splitting contradiction
Rule 4.2 states: "If a basic block is deemed cold, it should move to a
separate buffer." This violates Rule 3.1 Implicit Indexing. If v100 is
located at instructions[100] and we move it to a cold buffer, it id no
longer at index 100. If we keep the index 100 but store the data
elsewhere, you break the linear memory array performance benefits.

Hot-cols splitting will be done during code generation.

Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-06 18:18:53 -04:00
Ronald Caesar
cf805cdd86 docs: Fix incorrect block scope comments
Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-05 21:45:43 -04:00
Ronald Caesar
ee594332c9 docs: Refactor IR to merge-at-bottom SSA model
- Replace value-returning IFs with Void IFs and explicit OPCODE_MERGE.
- Move SSA definitions to block exits to eliminate backpatching.
- Formalize Control Scope Stack for tracking yields and arity.
- Update loop peeling logic to respect new merge semantics.

Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-05 21:26:14 -04:00
Ronald Caesar
f314836808 docs: Add IF-to-SELECT optimization pass
Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-02 20:04:30 -04:00
Ronald Caesar
826cce03bf docs: Add loop construction algorithm
Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-02 02:11:41 -04:00
Ronald Caesar
9c35cfdff1 docs: Add and reorganize ssa construction rules
Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-01 23:31:48 -04:00
Ronald Caesar
31db2bd196 docs: Add SSA construction rule for source variables
Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-01 22:21:34 -04:00
Ronald Caesar
89c20b9584 docs: Add SSA optimization rules
Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-01 22:19:28 -04:00
Ronald Caesar
208592ab3b docs: Add constants to IR design doc
Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-01 22:03:20 -04:00
Ronald Caesar
1f593677b2 docs: Add type attribute to ssa_version_t
This attribute originally got removed because you could determine the
type of the variable based on the instruction opcode.

For example:

x1 = OPCODE_ADD_INT32 y1, 10.

x1 type is an int32.

We cannot apply this to control instructions because that would bloat
the amount of opcodes needed. An opcode has 10 bits, so we can define
1024 opcodes. Adding different variations for an `IF` instruction alone
would fill uo way to much space:

x1 = IF_INT8   (condition)
x1 = IF_INT16  (condition)
x1 = IF_INT32  (condition)
x1 = IF_UINT8  (condition)
x1 = IF_FLOAT  (condition)
x1 = IF_VECTOR (condition)
etc...

So to solve creating unecessary opcodes, ssa_version_t will hold the
variable type instead:

x1 = IF (condition) DEF_TYPE: INT32

ssa_version_t.type = DEF_TYPE

Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-01 21:23:30 -04:00
Ronald Caesar
547bb249db docs: Organize IR design doc
Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-01 20:22:19 -04:00
Ronald Caesar
4679593839 docs: Move IR dedign doc to docs/
Signed-off-by: Ronald Caesar <github43132@proton.me>
2026-01-01 19:08:40 -04:00