EON (shifted register)
Bitwise Exclusive-OR NOT (shifted register)
Bitwise Exclusive-OR NOT (shifted register) performs a bitwise exclusive-OR NOT of a register value and an optionally-shifted register value, and writes the result to the destination register.
If PSTATE.DIT is 1:
The execution time of this instruction is independent of:The values of the data supplied in any of its registers.The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:The values of the data supplied in any of its registers.The values of the NZCV flags.
1
0
0
1
0
1
0
1
0
EON <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
1
EON <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
integer d = UInt(Rd);
integer n = UInt(Rn);
integer m = UInt(Rm);
integer datasize = if sf == '1' then 64 else 32;
boolean setflags;
LogicalOp op;
case opc of
when '00' op = LogicalOp_AND; setflags = FALSE;
when '01' op = LogicalOp_ORR; setflags = FALSE;
when '10' op = LogicalOp_EOR; setflags = FALSE;
when '11' op = LogicalOp_AND; setflags = TRUE;
if sf == '0' && imm6<5> == '1' then UNDEFINED;
ShiftType shift_type = DecodeShift(shift);
integer shift_amount = UInt(imm6);
boolean invert = (N == '1');
<Wd>
Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.
<Wn>
Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field.
<Wm>
Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field.
<Xd>
Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.
<Xn>
Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field.
<Xm>
Is the 64-bit name of the second general-purpose source register, encoded in the "Rm" field.
<shift>
Is the optional shift to be applied to the final source, defaulting to LSL and
shift
<shift>
00
LSL
01
LSR
10
ASR
11
ROR
<amount>
For the 32-bit variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.
<amount>
For the 64-bit variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field,
bits(datasize) operand1 = X[n, datasize];
bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount, datasize);
bits(datasize) result;
if invert then operand2 = NOT(operand2);
case op of
when LogicalOp_AND result = operand1 AND operand2;
when LogicalOp_ORR result = operand1 OR operand2;
when LogicalOp_EOR result = operand1 EOR operand2;
if setflags then
PSTATE.<N,Z,C,V> = result<datasize-1>:IsZeroBit(result):'00';
X[d, datasize] = result;