FCVTAU (scalar) Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (scalar) Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (scalar). This instruction converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit unsigned integer using the Round to Nearest with Ties to Away rounding mode, and writes the result to the general-purpose destination register. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. 0 0 1 1 1 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 1 1 FCVTAU <Wd>, <Hn> 1 1 1 FCVTAU <Xd>, <Hn> 0 0 0 FCVTAU <Wd>, <Sn> 1 0 0 FCVTAU <Xd>, <Sn> 0 0 1 FCVTAU <Wd>, <Dn> 1 0 1 FCVTAU <Xd>, <Dn> integer d = UInt(Rd); integer n = UInt(Rn); integer intsize = if sf == '1' then 64 else 32; integer fltsize; FPConvOp op; FPRounding rounding; boolean unsigned; integer part; case ftype of when '00' fltsize = 32; when '01' fltsize = 64; when '10' if opcode<2:1>:rmode != '11 01' then UNDEFINED; fltsize = 128; when '11' if HaveFP16Ext() then fltsize = 16; else UNDEFINED; case opcode<2:1>:rmode of when '00 xx' // FCVT[NPMZ][US] rounding = FPDecodeRounding(rmode); unsigned = (opcode<0> == '1'); op = FPConvOp_CVT_FtoI; when '01 00' // [US]CVTF rounding = FPRoundingMode(FPCR[]); unsigned = (opcode<0> == '1'); op = FPConvOp_CVT_ItoF; when '10 00' // FCVTA[US] rounding = FPRounding_TIEAWAY; unsigned = (opcode<0> == '1'); op = FPConvOp_CVT_FtoI; when '11 00' // FMOV if fltsize != 16 && fltsize != intsize then UNDEFINED; op = if opcode<0> == '1' then FPConvOp_MOV_ItoF else FPConvOp_MOV_FtoI; part = 0; when '11 01' // FMOV D[1] if intsize != 64 || fltsize != 128 then UNDEFINED; op = if opcode<0> == '1' then FPConvOp_MOV_ItoF else FPConvOp_MOV_FtoI; part = 1; fltsize = 64; // size of D[1] is 64 when '11 11' // FJCVTZS if !HaveFJCVTZSExt() then UNDEFINED; rounding = FPRounding_ZERO; unsigned = (opcode<0> == '1'); op = FPConvOp_CVT_FtoI_JS; otherwise UNDEFINED; <Wd> Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. <Xd> Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. <Sn> Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field. <Hn> Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field. <Dn> Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field. if op == FPConvOp_CVT_FtoI_JS then CheckFPAdvSIMDEnabled64(); else CheckFPEnabled64(); FPCRType fpcr = FPCR[]; boolean merge = IsMerging(fpcr); integer fsize = if op == FPConvOp_CVT_ItoF && merge then 128 else fltsize; bits(fsize) fltval; bits(intsize) intval; case op of when FPConvOp_CVT_FtoI fltval = V[n, fsize]; intval = FPToFixed(fltval, 0, unsigned, fpcr, rounding, intsize); X[d, intsize] = intval; when FPConvOp_CVT_ItoF intval = X[n, intsize]; fltval = if merge then V[d, fsize] else Zeros(fsize); Elem[fltval, 0, fltsize] = FixedToFP(intval, 0, unsigned, fpcr, rounding, fltsize); V[d, fsize] = fltval; when FPConvOp_MOV_FtoI fltval = Vpart[n,part,fsize]; intval = ZeroExtend(fltval, intsize); X[d, intsize] = intval; when FPConvOp_MOV_ItoF intval = X[n, intsize]; fltval = intval<fsize-1:0>; Vpart[d,part,fsize] = fltval; when FPConvOp_CVT_FtoI_JS bit z; fltval = V[n, fsize]; (intval, z) = FPToFixedJS(fltval, fpcr, TRUE, intsize); PSTATE.<N,Z,C,V> = '0':z:'00'; X[d, intsize] = intval;