FCVTZU (scalar, fixed-point)
Floating-point Convert to Unsigned fixed-point, rounding toward Zero (scalar)
Floating-point Convert to Unsigned fixed-point, rounding toward Zero (scalar). This instruction converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.
A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
0
0
1
1
1
1
0
0
1
1
0
0
1
0
1
1
FCVTZU <Wd>, <Hn>, #<fbits>
1
1
1
FCVTZU <Xd>, <Hn>, #<fbits>
0
0
0
FCVTZU <Wd>, <Sn>, #<fbits>
1
0
0
FCVTZU <Xd>, <Sn>, #<fbits>
0
0
1
FCVTZU <Wd>, <Dn>, #<fbits>
1
0
1
FCVTZU <Xd>, <Dn>, #<fbits>
integer d = UInt(Rd);
integer n = UInt(Rn);
integer intsize = if sf == '1' then 64 else 32;
integer fltsize;
FPConvOp op;
FPRounding rounding;
boolean unsigned;
case ftype of
when '00' fltsize = 32;
when '01' fltsize = 64;
when '10' UNDEFINED;
when '11'
if HaveFP16Ext() then
fltsize = 16;
else
UNDEFINED;
if sf == '0' && scale<5> == '0' then UNDEFINED;
integer fracbits = 64 - UInt(scale);
case opcode<2:1>:rmode of
when '00 11' // FCVTZ
rounding = FPRounding_ZERO;
unsigned = (opcode<0> == '1');
op = FPConvOp_CVT_FtoI;
when '01 00' // [US]CVTF
rounding = FPRoundingMode(FPCR[]);
unsigned = (opcode<0> == '1');
op = FPConvOp_CVT_ItoF;
otherwise
UNDEFINED;
<Wd>
Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.
<Xd>
Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.
<Sn>
Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
<Hn>
Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
<Dn>
Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field.
<fbits>
For the double-precision to 32-bit, half-precision to 32-bit and single-precision to 32-bit variant: is the number of bits after the binary point in the fixed-point destination, in the range 1 to 32, encoded as 64 minus "scale".
<fbits>
For the double-precision to 64-bit, half-precision to 64-bit and single-precision to 64-bit variant: is the number of bits after the binary point in the fixed-point destination, in the range 1 to 64, encoded as 64 minus "scale".
CheckFPEnabled64();
FPCRType fpcr = FPCR[];
boolean merge = IsMerging(fpcr);
integer fsize = if op == FPConvOp_CVT_ItoF && merge then 128 else fltsize;
bits(fsize) fltval;
bits(intsize) intval;
case op of
when FPConvOp_CVT_FtoI
fltval = V[n, fsize];
intval = FPToFixed(fltval, fracbits, unsigned, fpcr, rounding, intsize);
X[d, intsize] = intval;
when FPConvOp_CVT_ItoF
intval = X[n, intsize];
fltval = if merge then V[d, fsize] else Zeros(fsize);
Elem[fltval, 0, fltsize] = FixedToFP(intval, fracbits, unsigned, fpcr, rounding, fltsize);
V[d, fsize] = fltval;