FMADD Floating-point fused Multiply-Add (scalar) Floating-point fused Multiply-Add (scalar). This instruction multiplies the values of the first two SIMD&FP source registers, adds the product to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. 0 0 0 1 1 1 1 1 0 0 1 1 FMADD <Hd>, <Hn>, <Hm>, <Ha> 0 0 FMADD <Sd>, <Sn>, <Sm>, <Sa> 0 1 FMADD <Dd>, <Dn>, <Dm>, <Da> integer d = UInt(Rd); integer a = UInt(Ra); integer n = UInt(Rn); integer m = UInt(Rm); integer esize; case ftype of when '00' esize = 32; when '01' esize = 64; when '10' UNDEFINED; when '11' if HaveFP16Ext() then esize = 16; else UNDEFINED; boolean opa_neg = (o1 == '1'); boolean op1_neg = (o0 != o1); <Dd> Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field. <Dn> Is the 64-bit name of the first SIMD&FP source register holding the multiplicand, encoded in the "Rn" field. <Dm> Is the 64-bit name of the second SIMD&FP source register holding the multiplier, encoded in the "Rm" field. <Da> Is the 64-bit name of the third SIMD&FP source register holding the addend, encoded in the "Ra" field. <Hd> Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field. <Hn> Is the 16-bit name of the first SIMD&FP source register holding the multiplicand, encoded in the "Rn" field. <Hm> Is the 16-bit name of the second SIMD&FP source register holding the multiplier, encoded in the "Rm" field. <Ha> Is the 16-bit name of the third SIMD&FP source register holding the addend, encoded in the "Ra" field. <Sd> Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field. <Sn> Is the 32-bit name of the first SIMD&FP source register holding the multiplicand, encoded in the "Rn" field. <Sm> Is the 32-bit name of the second SIMD&FP source register holding the multiplier, encoded in the "Rm" field. <Sa> Is the 32-bit name of the third SIMD&FP source register holding the addend, encoded in the "Ra" field. CheckFPEnabled64(); bits(esize) operanda = V[a, esize]; bits(esize) operand1 = V[n, esize]; bits(esize) operand2 = V[m, esize]; FPCRType fpcr = FPCR[]; boolean merge = IsMerging(fpcr); bits(128) result = if merge then V[a, 128] else Zeros(128); if opa_neg then operanda = FPNeg(operanda); if op1_neg then operand1 = FPNeg(operand1); Elem[result, 0, esize] = FPMulAdd(operanda, operand1, operand2, fpcr); V[d, 128] = result;