FMAX (scalar)
Floating-point Maximum (scalar)
Floating-point Maximum (scalar). This instruction compares the two source SIMD&FP registers, and writes the larger of the two floating-point values to the destination SIMD&FP register.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
0
0
0
1
1
1
1
0
1
0
1
0
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1
FMAX <Hd>, <Hn>, <Hm>
0
0
FMAX <Sd>, <Sn>, <Sm>
0
1
FMAX <Dd>, <Dn>, <Dm>
integer d = UInt(Rd);
integer n = UInt(Rn);
integer m = UInt(Rm);
integer esize;
case ftype of
when '00' esize = 32;
when '01' esize = 64;
when '10' UNDEFINED;
when '11'
if HaveFP16Ext() then
esize = 16;
else
UNDEFINED;
FPMaxMinOp operation;
case op of
when '00' operation = FPMaxMinOp_MAX;
when '01' operation = FPMaxMinOp_MIN;
when '10' operation = FPMaxMinOp_MAXNUM;
when '11' operation = FPMaxMinOp_MINNUM;
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Dn>
Is the 64-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
<Dm>
Is the 64-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
<Hd>
Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Hn>
Is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
<Hm>
Is the 16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
<Sd>
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Sn>
Is the 32-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
<Sm>
Is the 32-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
CheckFPEnabled64();
bits(esize) operand1 = V[n, esize];
bits(esize) operand2 = V[m, esize];
FPCRType fpcr = FPCR[];
boolean merge = IsMerging(fpcr);
bits(128) result = if merge then V[n, 128] else Zeros(128);
case operation of
when FPMaxMinOp_MAX Elem[result, 0, esize] = FPMax(operand1, operand2, fpcr);
when FPMaxMinOp_MIN Elem[result, 0, esize] = FPMin(operand1, operand2, fpcr);
when FPMaxMinOp_MAXNUM Elem[result, 0, esize] = FPMaxNum(operand1, operand2, fpcr);
when FPMaxMinOp_MINNUM Elem[result, 0, esize] = FPMinNum(operand1, operand2, fpcr);
V[d, 128] = result;