FMINP (scalar)
Floating-point Minimum of Pair of elements (scalar)
Floating-point Minimum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 2 classes:
Half-precision
and
Single-precision and double-precision
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FMINP <V><d>, <Vn>.<T>
if !HaveFP16Ext() then UNDEFINED;
integer d = UInt(Rd);
integer n = UInt(Rn);
integer esize = 16;
if sz == '1' then UNDEFINED;
integer datasize = esize * 2;
integer elements = 2;
ReduceOp op = if o1 == '1' then ReduceOp_FMIN else ReduceOp_FMAX;
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FMINP <V><d>, <Vn>.<T>
integer d = UInt(Rd);
integer n = UInt(Rn);
integer esize = 32 << UInt(sz);
integer datasize = esize * 2;
integer elements = 2;
ReduceOp op = if o1 == '1' then ReduceOp_FMIN else ReduceOp_FMAX;
<V>
For the half-precision variant: is the destination width specifier,
<V>
For the single-precision and double-precision variant: is the destination width specifier,
<d>
Is the number of the SIMD&FP destination register, encoded in the "Rd" field.
<Vn>
Is the name of the SIMD&FP source register, encoded in the "Rn" field.
<T>
For the half-precision variant: is the source arrangement specifier,
<T>
For the single-precision and double-precision variant: is the source arrangement specifier,
CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n, datasize];
V[d, esize] = Reduce(op, operand, esize);