FRINTZ (scalar)
Floating-point Round to Integral, toward Zero (scalar)
Floating-point Round to Integral, toward Zero (scalar). This instruction rounds a floating-point value in the SIMD&FP source register to an integral floating-point value of the same size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.
A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.
A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
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FRINTZ <Hd>, <Hn>
0
0
FRINTZ <Sd>, <Sn>
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1
FRINTZ <Dd>, <Dn>
integer d = UInt(Rd);
integer n = UInt(Rn);
integer esize;
case ftype of
when '00' esize = 32;
when '01' esize = 64;
when '10' UNDEFINED;
when '11'
if HaveFP16Ext() then
esize = 16;
else
UNDEFINED;
boolean exact = FALSE;
FPRounding rounding;
case rmode of
when '0xx' rounding = FPDecodeRounding(rmode<1:0>);
when '100' rounding = FPRounding_TIEAWAY;
when '101' UNDEFINED;
when '110' rounding = FPRoundingMode(FPCR[]); exact = TRUE;
when '111' rounding = FPRoundingMode(FPCR[]);
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Dn>
Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field.
<Hd>
Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Hn>
Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
<Sd>
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Sn>
Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
CheckFPEnabled64();
FPCRType fpcr = FPCR[];
boolean merge = IsMerging(fpcr);
bits(128) result = if merge then V[d, 128] else Zeros(128);
bits(esize) operand = V[n, esize];
Elem[result, 0, esize] = FPRoundInt(operand, fpcr, rounding, exact);
V[d, 128] = result;