LDRSW (register)
Load Register Signed Word (register)
Load Register Signed Word (register) calculates an address from a base register value and an offset register value, loads a word from memory, sign-extends it to form a 64-bit value, and writes it to a register. The offset register value can be shifted left by 0 or 2 bits. For information about memory accesses, see Load/Store addressing modes.
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
1
0
1
1
1
0
0
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1
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0
LDRSW <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
boolean wback = FALSE;
boolean postindex = FALSE;
integer scale = UInt(size);
if option<1> == '0' then UNDEFINED; // sub-word index
ExtendType extend_type = DecodeRegExtend(option);
integer shift = if S == '1' then scale else 0;
<Xt>
Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
<Xn|SP>
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<Wm>
When option<0> is set to 0, is the 32-bit name of the general-purpose index register, encoded in the "Rm" field.
<Xm>
When option<0> is set to 1, is the 64-bit name of the general-purpose index register, encoded in the "Rm" field.
<extend>
Is the index extend/shift specifier, defaulting to LSL, and which must be omitted for the LSL option when <amount> is omitted.
option
<extend>
010
UXTW
011
LSL
110
SXTW
111
SXTX
<amount>
Is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is
integer n = UInt(Rn);
integer t = UInt(Rt);
integer m = UInt(Rm);
boolean nontemporal = FALSE;
boolean privileged = PSTATE.EL != EL0;
MemOp memop;
boolean signed;
integer regsize;
if opc<1> == '0' then
// store or zero-extending load
memop = if opc<0> == '1' then MemOp_LOAD else MemOp_STORE;
regsize = if size == '11' then 64 else 32;
signed = FALSE;
else
if size == '11' then
memop = MemOp_PREFETCH;
if opc<0> == '1' then UNDEFINED;
else
// sign-extending load
memop = MemOp_LOAD;
if size == '10' && opc<0> == '1' then UNDEFINED;
regsize = if opc<0> == '1' then 32 else 64;
signed = TRUE;
integer datasize = 8 << scale;
boolean tagchecked = memop != MemOp_PREFETCH;
boolean wb_unknown = FALSE;
boolean rt_unknown = FALSE;
Constraint c;
if memop == MemOp_LOAD && wback && n == t && n != 31 then
c = ConstrainUnpredictable(Unpredictable_WBOVERLAPLD);
assert c IN {Constraint_WBSUPPRESS, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP};
case c of
when Constraint_WBSUPPRESS wback = FALSE; // writeback is suppressed
when Constraint_UNKNOWN wb_unknown = TRUE; // writeback is UNKNOWN
when Constraint_UNDEF UNDEFINED;
when Constraint_NOP EndOfInstruction();
if memop == MemOp_STORE && wback && n == t && n != 31 then
c = ConstrainUnpredictable(Unpredictable_WBOVERLAPST);
assert c IN {Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP};
case c of
when Constraint_NONE rt_unknown = FALSE; // value stored is original value
when Constraint_UNKNOWN rt_unknown = TRUE; // value stored is UNKNOWN
when Constraint_UNDEF UNDEFINED;
when Constraint_NOP EndOfInstruction();
bits(64) offset = ExtendReg(m, extend_type, shift, 64);
bits(64) address;
bits(datasize) data;
AccessDescriptor accdesc = CreateAccDescGPR(memop, nontemporal, privileged, tagchecked);
if n == 31 then
if memop != MemOp_PREFETCH then CheckSPAlignment();
address = SP[];
else
address = X[n, 64];
if ! postindex then
address = address + offset;
case memop of
when MemOp_STORE
if rt_unknown then
data = bits(datasize) UNKNOWN;
else
data = X[t, datasize];
Mem[address, datasize DIV 8, accdesc] = data;
when MemOp_LOAD
data = Mem[address, datasize DIV 8, accdesc];
if signed then
X[t, regsize] = SignExtend(data, regsize);
else
X[t, regsize] = ZeroExtend(data, regsize);
when MemOp_PREFETCH
Prefetch(address, t<4:0>);
if wback then
if wb_unknown then
address = bits(64) UNKNOWN;
elsif postindex then
address = address + offset;
if n == 31 then
SP[] = address;
else
X[n, 64] = address;