SCVTF (vector, fixed-point) Signed fixed-point Convert to Floating-point (vector) Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped. It has encodings from 2 classes: Scalar and Vector 0 1 0 1 1 1 1 1 0 != 0000 1 1 1 0 0 1 SCVTF <V><d>, <V><n>, #<fbits> integer d = UInt(Rd); integer n = UInt(Rn); if immh IN {'000x'} || (immh IN {'001x'} && !HaveFP16Ext()) then UNDEFINED; integer esize = if immh IN {'1xxx'} then 64 else if immh IN {'01xx'} then 32 else 16; integer datasize = esize; integer elements = 1; integer fracbits = (esize * 2) - UInt(immh:immb); boolean unsigned = (U == '1'); FPRounding rounding = FPRoundingMode(FPCR[]); 0 0 0 1 1 1 1 0 != 0000 1 1 1 0 0 1 SCVTF <Vd>.<T>, <Vn>.<T>, #<fbits> integer d = UInt(Rd); integer n = UInt(Rn); if immh == '0000' then SEE(asimdimm); if immh IN {'000x'} || (immh IN {'001x'} && !HaveFP16Ext()) then UNDEFINED; if immh<3>:Q == '10' then UNDEFINED; integer esize = if immh IN {'1xxx'} then 64 else if immh IN {'01xx'} then 32 else 16; integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; integer fracbits = (esize * 2) - UInt(immh:immb); boolean unsigned = (U == '1'); FPRounding rounding = FPRoundingMode(FPCR[]); <V> Is a width specifier, immh <V> 000x RESERVED 001x H 01xx S 1xxx D <d> Is the number of the SIMD&FP destination register, in the "Rd" field. <n> Is the number of the first SIMD&FP source register, encoded in the "Rn" field. <Vd> Is the name of the SIMD&FP destination register, encoded in the "Rd" field. <T> Is an arrangement specifier, immh Q <T> 0000 x SEE Advanced SIMD modified immediate 0001 x RESERVED 001x 0 4H 001x 1 8H 01xx 0 2S 01xx 1 4S 1xxx 0 RESERVED 1xxx 1 2D <Vn> Is the name of the SIMD&FP source register, encoded in the "Rn" field. <fbits> For the scalar variant: is the number of fractional bits, in the range 1 to the operand width, immh <fbits> 000x RESERVED 001x (32-Uint(immh:immb)) 01xx (64-UInt(immh:immb)) 1xxx (128-UInt(immh:immb)) <fbits> For the vector variant: is the number of fractional bits, in the range 1 to the element width, immh <fbits> 0000 SEE Advanced SIMD modified immediate 0001 RESERVED 001x (32-Uint(immh:immb)) 01xx (64-UInt(immh:immb)) 1xxx (128-UInt(immh:immb)) CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n, datasize]; bits(esize) element; FPCRType fpcr = FPCR[]; boolean merge = elements == 1 && IsMerging(fpcr); bits(128) result = if merge then V[d, 128] else Zeros(128); for e = 0 to elements-1 element = Elem[operand, e, esize]; Elem[result, e, esize] = FixedToFP(element, fracbits, unsigned, fpcr, rounding, esize); V[d, 128] = result;