UMLAL (multiple vectors) Multi-vector unsigned integer multiply-add long The instruction operates on two or four ZA double-vector groups. This unsigned integer multiply-add long instruction multiplies each unsigned 16-bit element in the two or four first source vectors with each unsigned 16-bit element in the two or four second source vectors, widens each product to 32-bits and destructively adds these values to the corresponding 32-bit elements of the two or four ZA double-vector groups. The lowest of the two consecutive vector numbers forming the double-vector group within each half or each quarter of the ZA array are selected by the sum of the vector select register and immediate offset, modulo half or quarter the number of ZA array vectors. The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA double-vector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code. This instruction is unpredicated. Green False SM_1_only It has encodings from 2 classes: Two ZA double-vectors and Four ZA double-vectors 1 1 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 0 0 UMLAL ZA.S[<Wv>, <offsf>:<offsl>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } if !HaveSME2() then UNDEFINED; constant integer esize = 32; integer v = UInt('010':Rv); integer n = UInt(Zn:'0'); integer m = UInt(Zm:'0'); integer offset = UInt(off2:'0'); constant integer nreg = 2; 1 1 0 0 0 0 0 1 1 1 1 0 1 0 0 1 0 0 0 1 0 0 UMLAL ZA.S[<Wv>, <offsf>:<offsl>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H } if !HaveSME2() then UNDEFINED; constant integer esize = 32; integer v = UInt('010':Rv); integer n = UInt(Zn:'00'); integer m = UInt(Zm:'00'); integer offset = UInt(off2:'0'); constant integer nreg = 4; <Wv> Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field. <offsf> Is the vector select offset, pointing to first of two consecutive vectors, encoded as "off2" field times 2. <offsl> Is the vector select offset, pointing to last of two consecutive vectors, encoded as "off2" field times 2 plus 1. <Zn1> For the two ZA double-vectors variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zn" times 2. <Zn1> For the four ZA double-vectors variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zn" times 4. <Zn4> Is the name of the fourth scalable vector register of a multi-vector sequence, encoded as "Zn" times 4 plus 3. <Zn2> Is the name of the second scalable vector register of a multi-vector sequence, encoded as "Zn" times 2 plus 1. <Zm1> For the two ZA double-vectors variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zm" times 2. <Zm1> For the four ZA double-vectors variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zm" times 4. <Zm4> Is the name of the fourth scalable vector register of a multi-vector sequence, encoded as "Zm" times 4 plus 3. <Zm2> Is the name of the second scalable vector register of a multi-vector sequence, encoded as "Zm" times 2 plus 1. CheckStreamingSVEAndZAEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; integer vectors = VL DIV 8; integer vstride = vectors DIV nreg; bits(32) vbase = X[v, 32]; integer vec = (UInt(vbase) + offset) MOD vstride; bits(VL) result; vec = vec - (vec MOD 2); for r = 0 to nreg-1 bits(VL) operand1 = Z[n+r, VL]; bits(VL) operand2 = Z[m+r, VL]; for i = 0 to 1 bits(VL) operand3 = ZAvector[vec + i, VL]; for e = 0 to elements-1 integer element1 = UInt(Elem[operand1, 2 * e + i, esize DIV 2]); integer element2 = UInt(Elem[operand2, 2 * e + i, esize DIV 2]); bits(esize) product = (element1 * element2)<esize-1:0>; Elem[result, e, esize] = Elem[operand3, e, esize] + product; ZAvector[vec + i, VL] = result; vec = vec + vstride;