URSHL (multiple vectors)
Multi-vector unsigned rounding shift left
Shift active unsigned elements of the two or four first source vectors by corresponding elements of the two or four second source vectors and destructively place the rounded results in the corresponding elements of the two or four first source vectors. A positive shift amount performs a left shift, otherwise a right shift by the negated shift amount is performed.
This instruction is unpredicated.
Green
False
SM_1_only
It has encodings from 2 classes:
Two registers
and
Four registers
1
1
0
0
0
0
0
1
1
0
1
0
1
1
0
0
1
0
0
0
1
1
URSHL { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }
if !HaveSME2() then UNDEFINED;
constant integer esize = 8 << UInt(size);
integer dn = UInt(Zdn:'0');
integer m = UInt(Zm:'0');
constant integer nreg = 2;
1
1
0
0
0
0
0
1
1
0
0
1
0
1
1
1
0
1
0
0
0
1
0
1
URSHL { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }
if !HaveSME2() then UNDEFINED;
constant integer esize = 8 << UInt(size);
integer dn = UInt(Zdn:'00');
integer m = UInt(Zm:'00');
constant integer nreg = 4;
<Zdn1>
For the two registers variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zdn" times 2.
<Zdn1>
For the four registers variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zdn" times 4.
<T>
Is the size specifier,
size
<T>
00
B
01
H
10
S
11
D
<Zdn4>
Is the name of the fourth scalable vector register of a multi-vector sequence, encoded as "Zdn" times 4 plus 3.
<Zdn2>
Is the name of the second scalable vector register of a multi-vector sequence, encoded as "Zdn" times 2 plus 1.
<Zm1>
For the two registers variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zm" times 2.
<Zm1>
For the four registers variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zm" times 4.
<Zm4>
Is the name of the fourth scalable vector register of a multi-vector sequence, encoded as "Zm" times 4 plus 3.
<Zm2>
Is the name of the second scalable vector register of a multi-vector sequence, encoded as "Zm" times 2 plus 1.
CheckStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV esize;
array [0..3] of bits(VL) results;
for r = 0 to nreg-1
bits(VL) operand1 = Z[dn+r, VL];
bits(VL) operand2 = Z[m+r, VL];
for e = 0 to elements-1
integer element = UInt(Elem[operand1, e, esize]);
integer shift = ShiftSat(SInt(Elem[operand2, e, esize]), esize);
integer res;
if shift >= 0 then
res = element << shift;
else
shift = -shift;
res = (element + (1 << (shift - 1))) >> shift;
Elem[results[r], e, esize] = res<esize-1:0>;
for r = 0 to nreg-1
Z[dn+r, VL] = results[r];