mirror of
https://github.com/pound-emu/ballistic.git
synced 2026-01-31 01:15:21 +01:00
345 lines
17 KiB
XML
345 lines
17 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
|
|
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
|
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
|
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
|
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
|
|
|
<instructionsection id="ADD_addsub_ext" title="ADD (extended register) -- A64" type="instruction">
|
|
<docvars>
|
|
<docvar key="cond-setting" value="no-s" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="ADD" />
|
|
</docvars>
|
|
<heading>ADD (extended register)</heading>
|
|
<desc>
|
|
<brief>
|
|
<para>Add (extended register)</para>
|
|
</brief>
|
|
<authored>
|
|
<para>Add (extended register) adds a register value and a sign or zero-extended register value, followed by an optional left shift amount, and writes the result to the destination register. The argument that is extended from the <syntax><Rm></syntax> register can be a byte, halfword, word, or doubleword.</para>
|
|
</authored>
|
|
</desc>
|
|
<operationalnotes>
|
|
<para>If PSTATE.DIT is 1:</para>
|
|
<list type="unordered">
|
|
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
|
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
|
</list>
|
|
</operationalnotes>
|
|
<alias_list howmany="0"></alias_list>
|
|
<classes>
|
|
<iclass name="Not setting the condition flags" oneof="1" id="iclass_no_s" no_encodings="2" isa="A64">
|
|
<docvars>
|
|
<docvar key="cond-setting" value="no-s" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="ADD" />
|
|
</docvars>
|
|
<iclassintro count="2"></iclassintro>
|
|
<regdiagram form="32" psname="aarch64/instrs/integer/arithmetic/add-sub/extendedreg" tworows="1">
|
|
<box hibit="31" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" name="op" usename="1" settings="1" psbits="x">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="29" name="S" usename="1" settings="1" psbits="x">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opt" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" name="option" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="imm3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="ADD_32_addsub_ext" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0">
|
|
<docvars>
|
|
<docvar key="cond-setting" value="no-s" />
|
|
<docvar key="datatype" value="32" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="ADD" />
|
|
</docvars>
|
|
<box hibit="31" width="1" name="sf">
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate><text>ADD </text><a link="sa_wd_wsp" hover="32-bit destination general-purpose register or WSP (field "Rd")"><Wd|WSP></a><text>, </text><a link="sa_wn_wsp" hover="First 32-bit source general-purpose register or WSP (field "Rn")"><Wn|WSP></a><text>, </text><a link="sa_wm" hover="Second 32-bit general-purpose source register (field "Rm")"><Wm></a><text>{</text><text>, </text><a link="sa_extend" hover="Extension applied to second source operand (field "option") [LSL,SXTB,SXTH,SXTW,SXTX,UXTB,UXTH,UXTW,UXTX]"><extend></a><text> </text><text>{</text><text>#</text><a link="sa_amount" hover="Left shift amount applied after extension [0-4], default 0 (field "imm3")"><amount></a><text>}</text><text>}</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="ADD_64_addsub_ext" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
|
|
<docvars>
|
|
<docvar key="cond-setting" value="no-s" />
|
|
<docvar key="datatype" value="64" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="ADD" />
|
|
</docvars>
|
|
<box hibit="31" width="1" name="sf">
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>ADD </text><a link="sa_xd_sp" hover="64-bit destination general-purpose register or SP (field "Rd")"><Xd|SP></a><text>, </text><a link="sa_xn_sp" hover="First 64-bit source general-purpose register or SP (field "Rn")"><Xn|SP></a><text>, </text><a link="sa_r" hover="Width specifier (field "option") [W,X]"><R></a><a link="sa_m" hover="Second general-purpose source register number [0-30] or ZR (31) (field "Rm")"><m></a><text>{</text><text>, </text><a link="sa_extend_1" hover="Extension applied to second source operand (field "option") [LSL,SXTB,SXTH,SXTW,SXTX,UXTB,UXTH,UXTW,UXTX]"><extend></a><text> </text><text>{</text><text>#</text><a link="sa_amount" hover="Left shift amount applied after extension [0-4], default 0 (field "imm3")"><amount></a><text>}</text><text>}</text></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/integer/arithmetic/add-sub/extendedreg" mylink="aarch64.instrs.integer.arithmetic.add-sub.extendedreg" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
|
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
|
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
|
integer datasize = if sf == '1' then 64 else 32;
|
|
boolean sub_op = (op == '1');
|
|
boolean setflags = (S == '1');
|
|
<a link="ExtendType" file="shared_pseudocode.xml" hover="enumeration ExtendType {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType</a> extend_type = <a link="impl-aarch64.DecodeRegExtend.1" file="shared_pseudocode.xml" hover="function: ExtendType DecodeRegExtend(bits(3) op)">DecodeRegExtend</a>(option);
|
|
integer shift = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm3);
|
|
if shift > 4 then UNDEFINED;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="ADD_32_addsub_ext" symboldefcount="1">
|
|
<symbol link="sa_wd_wsp"><Wd|WSP></symbol>
|
|
<account encodedin="Rd">
|
|
<intro>
|
|
<para>Is the 32-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="ADD_32_addsub_ext" symboldefcount="1">
|
|
<symbol link="sa_wn_wsp"><Wn|WSP></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>Is the 32-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="ADD_32_addsub_ext" symboldefcount="1">
|
|
<symbol link="sa_wm"><Wm></symbol>
|
|
<account encodedin="Rm">
|
|
<intro>
|
|
<para>Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="ADD_64_addsub_ext" symboldefcount="1">
|
|
<symbol link="sa_xd_sp"><Xd|SP></symbol>
|
|
<account encodedin="Rd">
|
|
<intro>
|
|
<para>Is the 64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="ADD_64_addsub_ext" symboldefcount="1">
|
|
<symbol link="sa_xn_sp"><Xn|SP></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>Is the 64-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="ADD_64_addsub_ext" symboldefcount="1">
|
|
<symbol link="sa_r"><R></symbol>
|
|
<definition encodedin="option">
|
|
<intro>Is a width specifier, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">option</entry>
|
|
<entry class="symbol"><R></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00x</entry>
|
|
<entry class="symbol">W</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">010</entry>
|
|
<entry class="symbol">W</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">x11</entry>
|
|
<entry class="symbol">X</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10x</entry>
|
|
<entry class="symbol">W</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">110</entry>
|
|
<entry class="symbol">W</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="ADD_64_addsub_ext" symboldefcount="1">
|
|
<symbol link="sa_m"><m></symbol>
|
|
<account encodedin="Rm">
|
|
<intro>
|
|
<para>Is the number [0-30] of the second general-purpose source register or the name ZR (31), encoded in the "Rm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="ADD_32_addsub_ext" symboldefcount="1">
|
|
<symbol link="sa_extend"><extend></symbol>
|
|
<definition encodedin="option">
|
|
<intro>For the 32-bit variant: is the extension to be applied to the second source operand, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">option</entry>
|
|
<entry class="symbol"><extend></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">000</entry>
|
|
<entry class="symbol">UXTB</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">001</entry>
|
|
<entry class="symbol">UXTH</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">010</entry>
|
|
<entry class="symbol">LSL|UXTW</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">011</entry>
|
|
<entry class="symbol">UXTX</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">100</entry>
|
|
<entry class="symbol">SXTB</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">101</entry>
|
|
<entry class="symbol">SXTH</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">110</entry>
|
|
<entry class="symbol">SXTW</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">111</entry>
|
|
<entry class="symbol">SXTX</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
<after>If "Rd" or "Rn" is '11111' (WSP) and "option" is '010' then LSL is preferred, but may be omitted when "imm3" is '000'. In all other cases <extend> is required and must be UXTW when "option" is '010'.</after>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="ADD_64_addsub_ext" symboldefcount="2">
|
|
<symbol link="sa_extend_1"><extend></symbol>
|
|
<definition encodedin="option">
|
|
<intro>For the 64-bit variant: is the extension to be applied to the second source operand, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">option</entry>
|
|
<entry class="symbol"><extend></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">000</entry>
|
|
<entry class="symbol">UXTB</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">001</entry>
|
|
<entry class="symbol">UXTH</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">010</entry>
|
|
<entry class="symbol">UXTW</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">011</entry>
|
|
<entry class="symbol">LSL|UXTX</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">100</entry>
|
|
<entry class="symbol">SXTB</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">101</entry>
|
|
<entry class="symbol">SXTH</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">110</entry>
|
|
<entry class="symbol">SXTW</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">111</entry>
|
|
<entry class="symbol">SXTX</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
<after>If "Rd" or "Rn" is '11111' (SP) and "option" is '011' then LSL is preferred, but may be omitted when "imm3" is '000'. In all other cases <extend> is required and must be UXTX when "option" is '011'.</after>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="ADD_32_addsub_ext, ADD_64_addsub_ext" symboldefcount="1">
|
|
<symbol link="sa_amount"><amount></symbol>
|
|
<account encodedin="imm3">
|
|
<intro>
|
|
<para>Is the left shift amount to be applied after extension in the range 0 to 4, defaulting to 0, encoded in the "imm3" field. It must be absent when <extend> is absent, is required when <extend> is LSL, and is optional when <extend> is present but not LSL.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/integer/arithmetic/add-sub/extendedreg" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(datasize) result;
|
|
bits(datasize) operand1 = if n == 31 then <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[]<datasize-1:0> else <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, datasize];
|
|
bits(datasize) operand2 = <a link="impl-aarch64.ExtendReg.4" file="shared_pseudocode.xml" hover="function: bits(N) ExtendReg(integer reg, ExtendType exttype, integer shift, integer N)">ExtendReg</a>(m, extend_type, shift, datasize);
|
|
bits(4) nzcv;
|
|
bit carry_in;
|
|
|
|
if sub_op then
|
|
operand2 = NOT(operand2);
|
|
carry_in = '1';
|
|
else
|
|
carry_in = '0';
|
|
|
|
(result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(operand1, operand2, carry_in);
|
|
|
|
if setflags then
|
|
PSTATE.<N,Z,C,V> = nzcv;
|
|
|
|
if d == 31 && !setflags then
|
|
<a link="impl-aarch64.SP.write.0" file="shared_pseudocode.xml" hover="accessor: SP[] = bits(64) value">SP</a>[] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(result, 64);
|
|
else
|
|
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, datasize] = result;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|