mirror of
https://github.com/pound-emu/ballistic.git
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153 lines
8.4 KiB
XML
153 lines
8.4 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="ADDG" title="ADDG -- A64" type="instruction">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ADDG" />
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</docvars>
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<heading>ADDG</heading>
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<desc>
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<brief>
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<para>Add with Tag</para>
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</brief>
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<authored>
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<para>Add with Tag adds an immediate value scaled by the Tag granule to the address in the source register, modifies the Logical Address Tag of the address using an immediate value, and writes the result to the destination register. Tags specified in GCR_EL1.Exclude are excluded from the possible outputs when modifying the Logical Address Tag.</para>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="Integer" oneof="1" id="iclass_general" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ADDG" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.5" feature="FEAT_MTE" />
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</arch_variants>
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<regdiagram form="32" psname="aarch64/instrs/integer/tags/mcaddtag" tworows="1">
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<box hibit="31" name="sf" settings="1">
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<c>1</c>
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</box>
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<box hibit="30" name="op" settings="1">
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<c>0</c>
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</box>
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<box hibit="29" name="S" settings="1">
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<c>0</c>
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</box>
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<box hibit="28" width="6" settings="6">
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="22" name="o2" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" width="6" name="uimm6" usename="1">
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<c colspan="6"></c>
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</box>
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<box hibit="15" width="2" name="op3" usename="1" settings="2" psbits="xx">
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<c>(0)</c>
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<c>(0)</c>
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</box>
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<box hibit="13" width="4" name="uimm4" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="9" width="5" name="Xn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Xd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="ADDG_64_addsub_immtags" oneofinclass="1" oneof="1" label="">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ADDG" />
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</docvars>
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<asmtemplate><text>ADDG </text><a link="sa_xd_sp" hover="64-bit destination general-purpose register or SP (field "Xd")"><Xd|SP></a><text>, </text><a link="sa_xn_sp" hover="64-bit source general-purpose register or SP (field "Xn")"><Xn|SP></a><text>, #</text><a link="sa_uimm6" hover="Unsigned immediate, multiple of 16 [0-1008] (field "uimm6")"><uimm6></a><text>, #</text><a link="sa_uimm4" hover="Unsigned immediate [0-15] (field "uimm4")"><uimm4></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/integer/tags/mcaddtag" mylink="aarch64.instrs.integer.tags.mcaddtag" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveMTEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEExt()">HaveMTEExt</a>() then UNDEFINED;
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xn);
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bits(4) tag_offset = uimm4;
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bits(64) offset = <a link="impl-shared.LSL.2" file="shared_pseudocode.xml" hover="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(uimm6, 64), <a link="LOG2_TAG_GRANULE" file="shared_pseudocode.xml" hover="constant integer LOG2_TAG_GRANULE = 4">LOG2_TAG_GRANULE</a>);
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boolean ADD = TRUE;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="ADDG_64_addsub_immtags" symboldefcount="1">
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<symbol link="sa_xd_sp"><Xd|SP></symbol>
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<account encodedin="Xd">
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<intro>
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<para>Is the 64-bit name of the destination general-purpose register or stack pointer, encoded in the "Xd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ADDG_64_addsub_immtags" symboldefcount="1">
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<symbol link="sa_xn_sp"><Xn|SP></symbol>
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<account encodedin="Xn">
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<intro>
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<para>Is the 64-bit name of the source general-purpose register or stack pointer, encoded in the "Xn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ADDG_64_addsub_immtags" symboldefcount="1">
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<symbol link="sa_uimm6"><uimm6></symbol>
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<account encodedin="uimm6">
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<intro>
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<para>Is an unsigned immediate, a multiple of 16 in the range 0 to 1008, encoded in the "uimm6" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ADDG_64_addsub_immtags" symboldefcount="1">
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<symbol link="sa_uimm4"><uimm4></symbol>
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<account encodedin="uimm4">
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<intro>
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<para>Is an unsigned immediate, in the range 0 to 15, encoded in the "uimm4" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/integer/tags/mcaddtag" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(64) operand1 = if n == 31 then <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[] else <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
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bits(4) start_tag = <a link="AArch64.AllocationTagFromAddress.1" file="shared_pseudocode.xml" hover="function: bits(4) AArch64.AllocationTagFromAddress(bits(64) tagged_address)">AArch64.AllocationTagFromAddress</a>(operand1);
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bits(16) exclude = GCR_EL1.Exclude;
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bits(64) result;
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bits(4) rtag;
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if <a link="AArch64.AllocationTagAccessIsEnabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.AllocationTagAccessIsEnabled(bits(2) el)">AArch64.AllocationTagAccessIsEnabled</a>(PSTATE.EL) then
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rtag = <a link="AArch64.ChooseNonExcludedTag.3" file="shared_pseudocode.xml" hover="function: bits(4) AArch64.ChooseNonExcludedTag(bits(4) tag_in, bits(4) offset_in, bits(16) exclude)">AArch64.ChooseNonExcludedTag</a>(start_tag, tag_offset, exclude);
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else
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rtag = '0000';
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if ADD then
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(result, -) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(operand1, offset, '0');
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else
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(result, -) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(operand1, NOT(offset), '1');
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result = <a link="AArch64.AddressWithAllocationTag.2" file="shared_pseudocode.xml" hover="function: bits(64) AArch64.AddressWithAllocationTag(bits(64) address, bits(4) allocation_tag)">AArch64.AddressWithAllocationTag</a>(result, rtag);
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if d == 31 then
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<a link="impl-aarch64.SP.write.0" file="shared_pseudocode.xml" hover="accessor: SP[] = bits(64) value">SP</a>[] = result;
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else
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<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = result;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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