mirror of
https://github.com/pound-emu/ballistic.git
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377 lines
18 KiB
XML
377 lines
18 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="adr_z_az" title="ADR" type="instruction">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ADR" />
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</docvars>
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<heading>ADR</heading>
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<desc>
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<brief>Compute vector address</brief>
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<description>
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<para>Optionally sign or zero-extend the least significant 32-bits of each element from a vector of offsets or indices in the second source vector, scale each index by 2, 4 or 8, add to a vector of base addresses from the first source vector, and place the resulting addresses in the destination vector. This instruction is unpredicated.</para>
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<para>This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.</para>
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</description>
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<status>Green</status>
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<predicated>False</predicated>
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<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
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<sm_policy>SM_0_only</sm_policy>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="3">
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<txt>It has encodings from 3 classes:</txt>
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<a href="#iclass_off_pkd">Packed offsets</a>
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<txt>, </txt>
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<a href="#iclass_off_s_s32">Unpacked 32-bit signed offsets</a>
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<txt> and </txt>
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<a href="#iclass_off_s_u32">Unpacked 32-bit unsigned offsets</a>
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</classesintro>
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<iclass name="Packed offsets" oneof="3" id="iclass_off_pkd" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ADR" />
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<docvar key="sve-offset-type" value="off_pkd" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="ADR-Z.AZ-SD.same.scaled">
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<box hibit="31" width="8" settings="8">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="23" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" name="sz" usename="1">
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<c></c>
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</box>
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<box hibit="21" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" width="5" name="Zm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" width="4" settings="4">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="11" width="2" name="msz" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="9" width="5" name="Zn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="adr_z_az_sd_same_scaled" oneofinclass="1" oneof="3" label="">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ADR" />
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<docvar key="sve-offset-type" value="off_pkd" />
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</docvars>
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<asmtemplate><text>ADR </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>, [</text><a link="sa_zn" hover="Base scalable vector register (field "Zn")"><Zn></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>, </text><a link="sa_zm" hover="Offset scalable vector register (field "Zm")"><Zm></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>{</text><text>, </text><a link="sa_mod" hover="Index extend and shift specifier (field "msz")"><mod></a><text> </text><a link="sa_amount" hover="Index shift amount (field "msz")"><amount></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="ADR-Z.AZ-SD.same.scaled" mylink="ADR-Z.AZ-SD.same.scaled" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() then UNDEFINED;
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constant integer esize = 32 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);
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constant integer osize = esize;
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boolean unsigned = TRUE;
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integer mbytes = 1 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(msz);</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Unpacked 32-bit signed offsets" oneof="3" id="iclass_off_s_s32" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ADR" />
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<docvar key="sve-offset-type" value="off_s_s32" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="ADR-Z.AZ-D.s32.scaled">
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<box hibit="31" width="8" settings="8">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="23" name="opc<1>" settings="1">
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<c>0</c>
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</box>
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<box hibit="22" name="opc<0>" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" width="5" name="Zm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" width="4" settings="4">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="11" width="2" name="msz" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="9" width="5" name="Zn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="adr_z_az_d_s32_scaled" oneofinclass="1" oneof="3" label="">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ADR" />
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<docvar key="sve-offset-type" value="off_s_s32" />
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</docvars>
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<asmtemplate><text>ADR </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.D, [</text><a link="sa_zn" hover="Base scalable vector register (field "Zn")"><Zn></a><text>.D, </text><a link="sa_zm" hover="Offset scalable vector register (field "Zm")"><Zm></a><text>.D, SXTW</text><text>{</text><text> </text><a link="sa_amount" hover="Index shift amount (field "msz")"><amount></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="ADR-Z.AZ-D.s32.scaled" mylink="ADR-Z.AZ-D.s32.scaled" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() then UNDEFINED;
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constant integer esize = 64;
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);
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constant integer osize = 32;
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boolean unsigned = FALSE;
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integer mbytes = 1 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(msz);</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Unpacked 32-bit unsigned offsets" oneof="3" id="iclass_off_s_u32" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ADR" />
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<docvar key="sve-offset-type" value="off_s_u32" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="ADR-Z.AZ-D.u32.scaled">
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<box hibit="31" width="8" settings="8">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="23" name="opc<1>" settings="1">
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<c>0</c>
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</box>
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<box hibit="22" name="opc<0>" settings="1">
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<c>1</c>
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</box>
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<box hibit="21" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" width="5" name="Zm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" width="4" settings="4">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="11" width="2" name="msz" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="9" width="5" name="Zn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="adr_z_az_d_u32_scaled" oneofinclass="1" oneof="3" label="">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ADR" />
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<docvar key="sve-offset-type" value="off_s_u32" />
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</docvars>
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<asmtemplate><text>ADR </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.D, [</text><a link="sa_zn" hover="Base scalable vector register (field "Zn")"><Zn></a><text>.D, </text><a link="sa_zm" hover="Offset scalable vector register (field "Zm")"><Zm></a><text>.D, UXTW</text><text>{</text><text> </text><a link="sa_amount" hover="Index shift amount (field "msz")"><amount></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="ADR-Z.AZ-D.u32.scaled" mylink="ADR-Z.AZ-D.u32.scaled" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() then UNDEFINED;
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constant integer esize = 64;
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);
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constant integer osize = 32;
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boolean unsigned = TRUE;
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integer mbytes = 1 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(msz);</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="adr_z_az_d_s32_scaled, adr_z_az_d_u32_scaled, adr_z_az_sd_same_scaled" symboldefcount="1">
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<symbol link="sa_zd"><Zd></symbol>
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<account encodedin="Zd">
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<intro>
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<para>Is the name of the destination scalable vector register, encoded in the "Zd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="adr_z_az_sd_same_scaled" symboldefcount="1">
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<symbol link="sa_t"><T></symbol>
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<definition encodedin="sz">
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<intro>Is the size specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">sz</entry>
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<entry class="symbol"><T></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="symbol">S</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="symbol">D</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="adr_z_az_d_s32_scaled, adr_z_az_d_u32_scaled, adr_z_az_sd_same_scaled" symboldefcount="1">
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<symbol link="sa_zn"><Zn></symbol>
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<account encodedin="Zn">
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<intro>
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<para>Is the name of the base scalable vector register, encoded in the "Zn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="adr_z_az_d_s32_scaled, adr_z_az_d_u32_scaled, adr_z_az_sd_same_scaled" symboldefcount="1">
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<symbol link="sa_zm"><Zm></symbol>
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<account encodedin="Zm">
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<intro>
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<para>Is the name of the offset scalable vector register, encoded in the "Zm" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="adr_z_az_sd_same_scaled" symboldefcount="1">
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<symbol link="sa_mod"><mod></symbol>
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<definition encodedin="msz">
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<intro>Is the index extend and shift specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">msz</entry>
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<entry class="symbol"><mod></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">00</entry>
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<entry class="symbol">[absent]</entry>
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</row>
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<row>
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<entry class="bitfield">x1</entry>
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<entry class="symbol">LSL</entry>
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</row>
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<row>
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<entry class="bitfield">10</entry>
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<entry class="symbol">LSL</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="adr_z_az_d_s32_scaled, adr_z_az_d_u32_scaled, adr_z_az_sd_same_scaled" symboldefcount="1">
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<symbol link="sa_amount"><amount></symbol>
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<definition encodedin="msz">
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<intro>Is the index shift amount, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">msz</entry>
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<entry class="symbol"><amount></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">00</entry>
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<entry class="symbol">[absent]</entry>
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</row>
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<row>
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<entry class="bitfield">01</entry>
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<entry class="symbol">#1</entry>
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</row>
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<row>
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<entry class="bitfield">10</entry>
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<entry class="symbol">#2</entry>
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</row>
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<row>
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<entry class="bitfield">11</entry>
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<entry class="symbol">#3</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="ADR-Z.AZ-SD.same.scaled" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckNonStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
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constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
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constant integer elements = VL DIV esize;
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bits(VL) base = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
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bits(VL) offs = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
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bits(VL) result;
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for e = 0 to elements-1
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bits(esize) addr = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[base, e, esize];
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integer offset = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[offs, e, esize]<osize-1:0>, unsigned);
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = addr + (offset * mbytes);
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<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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