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https://github.com/pound-emu/ballistic.git
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234 lines
14 KiB
XML
234 lines
14 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="BFDOT_advsimd_elt" title="BFDOT (by element) -- A64" type="instruction">
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<docvars>
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<docvar key="advsimd-reguse" value="2reg-element" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="BFDOT" />
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</docvars>
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<heading>BFDOT (by element)</heading>
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<desc>
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<brief>
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<para>BFloat16 floating-point dot product (vector, by element)</para>
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</brief>
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<authored>
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<para>BFloat16 floating-point dot product (vector, by element). This instruction delimits the source vectors into pairs of BFloat16 elements. The BFloat16 pair within the second source vector is specified using an immediate index. The index range is from 0 to 3 inclusive.</para>
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<para>If FEAT_EBF16 is not implemented or <xref linkend="AArch64.fpcr">FPCR</xref>.EBF is 0, this instruction:</para>
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<list type="unordered">
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<listitem><content>Performs an unfused sum-of-products of each pair of adjacent BFloat16 elements in the first source vector with the specified pair of elements in the second source vector. The intermediate single-precision products are rounded before they are summed, and the intermediate sum is rounded before accumulation into the single-precision destination element that overlaps with the corresponding pair of BFloat16 elements in the first source vector.</content></listitem>
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<listitem><content>Uses the non-IEEE 754 Round-to-Odd rounding mode, which forces bit 0 of an inexact result to 1, and rounds an overflow to an appropriately signed Infinity.</content></listitem>
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<listitem><content>Flushes denormalized inputs and results to zero, as if <xref linkend="AArch64.fpcr">FPCR</xref>.{FZ, FIZ} is {1, 1}.</content></listitem>
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<listitem><content>Disables alternative floating point behaviors, as if <xref linkend="AArch64.fpcr">FPCR</xref>.AH is 0.</content></listitem>
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</list>
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<para>If FEAT_EBF16 is implemented and <xref linkend="AArch64.fpcr">FPCR</xref>.EBF is 1, then this instruction:</para>
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<list type="unordered">
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<listitem><content>Performs a fused sum-of-products of each pair of adjacent BFloat16 elements in the first source vector with the specified pair of elements in the second source vector. The intermediate single-precision products are not rounded before they are summed, but the intermediate sum is rounded before accumulation into the single-precision destination element that overlaps with the corresponding pair of BFloat16 elements in the first source vector.</content></listitem>
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<listitem><content>Follows all other floating-point behaviors that apply to single-precision arithmetic, as governed by <xref linkend="AArch64.fpcr">FPCR</xref>.RMode, <xref linkend="AArch64.fpcr">FPCR</xref>.FZ, <xref linkend="AArch64.fpcr">FPCR</xref>.AH, and <xref linkend="AArch64.fpcr">FPCR</xref>.FIZ.</content></listitem>
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</list>
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<para>Irrespective of FEAT_EBF16 and <xref linkend="AArch64.fpcr">FPCR</xref>.EBF, this instruction:</para>
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<list type="unordered">
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<listitem><content>Does not modify the cumulative <xref linkend="AArch64.fpsr">FPSR</xref> exception bits (IDC, IXC, UFC, OFC, DZC, and IOC).</content></listitem>
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<listitem><content>Disables trapped floating-point exceptions, as if the <xref linkend="AArch64.fpcr">FPCR</xref> trap enable bits (IDE, IXE, UFE, OFE, DZE, and IOE) are all zero.</content></listitem>
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<listitem><content>Generates only the default NaN, as if <xref linkend="AArch64.fpcr">FPCR</xref>.DN is 1.</content></listitem>
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</list>
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<para><xref linkend="AArch64.id_aa64isar1_el1">ID_AA64ISAR1_EL1</xref>.BF16 indicates whether this instruction is supported.</para>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="Vector" oneof="1" id="iclass_2reg_element" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="advsimd-reguse" value="2reg-element" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="BFDOT" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.6" feature="FEAT_BF16" />
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</arch_variants>
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<regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/binary/element/bfdot">
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<box hibit="31" settings="1">
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<c>0</c>
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</box>
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<box hibit="30" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="29" name="U" settings="1">
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<c>0</c>
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</box>
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<box hibit="28" width="5" settings="5">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="23" width="2" name="size" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="21" name="L" usename="1">
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<c></c>
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</box>
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<box hibit="20" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="19" width="4" name="Rm" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="opcode" settings="4">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="11" name="H" usename="1">
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<c></c>
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</box>
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<box hibit="10" settings="1">
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="BFDOT_asimdelem_E" oneofinclass="1" oneof="1" label="">
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<docvars>
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<docvar key="advsimd-reguse" value="2reg-element" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="BFDOT" />
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</docvars>
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<asmtemplate><text>BFDOT </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_ta" hover="Arrangement specifier (field "Q") [2S,4S]"><Ta></a><text>, </text><a link="sa_vn" hover="First SIMD&FP source register (field "Rn")"><Vn></a><text>.</text><a link="sa_tb" hover="Arrangement specifier (field "Q") [4H,8H]"><Tb></a><text>, </text><a link="sa_vm" hover="Second SIMD&FP source register (field "M:Rm")"><Vm></a><text>.2H[</text><a link="sa_index" hover="Immediate index of a pair of 16-bit elements [0-3] (field "H:L")"><index></a><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/arithmetic/binary/element/bfdot" mylink="aarch64.instrs.vector.arithmetic.binary.element.bfdot" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveBF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveBF16Ext()">HaveBF16Ext</a>() then UNDEFINED;
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Rm);
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer i = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(H:L);
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integer datasize = if Q == '1' then 128 else 64;
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integer elements = datasize DIV 32;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="BFDOT_asimdelem_E" symboldefcount="1">
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<symbol link="sa_vd"><Vd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="BFDOT_asimdelem_E" symboldefcount="1">
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<symbol link="sa_ta"><Ta></symbol>
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<definition encodedin="Q">
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<intro>Is an arrangement specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">Q</entry>
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<entry class="symbol"><Ta></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="symbol">2S</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="symbol">4S</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="BFDOT_asimdelem_E" symboldefcount="1">
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<symbol link="sa_vn"><Vn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the name of the first SIMD&FP source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="BFDOT_asimdelem_E" symboldefcount="1">
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<symbol link="sa_tb"><Tb></symbol>
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<definition encodedin="Q">
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<intro>Is an arrangement specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">Q</entry>
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<entry class="symbol"><Tb></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="symbol">4H</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="symbol">8H</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="BFDOT_asimdelem_E" symboldefcount="1">
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<symbol link="sa_vm"><Vm></symbol>
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<account encodedin="M:Rm">
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<intro>
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<para>Is the name of the second SIMD&FP source register, encoded in the "M:Rm" fields.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="BFDOT_asimdelem_E" symboldefcount="1">
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<symbol link="sa_index"><index></symbol>
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<account encodedin="H:L">
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<intro>
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<para>Is the immediate index of a pair of 16-bit elements in the range 0 to 3, encoded in the "H:L" fields.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/arithmetic/binary/element/bfdot" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
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bits(datasize) operand1 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, datasize];
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bits(128) operand2 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[m, 128];
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bits(datasize) operand3 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[d, datasize];
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bits(datasize) result;
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for e = 0 to elements-1
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bits(16) elt1_a = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2 * e + 0, 16];
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bits(16) elt1_b = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2 * e + 1, 16];
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bits(16) elt2_a = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2 * i + 0, 16];
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bits(16) elt2_b = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2 * i + 1, 16];
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bits(32) sum = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 32];
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sum = <a link="impl-shared.BFDotAdd.6" file="shared_pseudocode.xml" hover="function: bits(32) BFDotAdd(bits(32) addend, bits(16) op1_a, bits(16) op1_b, bits(16) op2_a, bits(16) op2_b, FPCRType fpcr_in)">BFDotAdd</a>(sum, elt1_a, elt1_b, elt2_a, elt2_b, FPCR[]);
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 32] = sum;
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<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, datasize] = result;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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