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https://github.com/pound-emu/ballistic.git
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260 lines
13 KiB
XML
260 lines
13 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="bfminnm_mz_zzv" title="BFMINNM (multiple and single vector)" type="instruction">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="BFMINNM" />
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</docvars>
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<heading>BFMINNM (multiple and single vector)</heading>
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<desc>
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<brief>Multi-vector BFloat16 floating-point minimum number by vector</brief>
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<description>
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<para>Determine the minimum number value of BFloat16 elements of the second source vector and the corresponding BFloat16 elements of the two or four first source vectors and destructively place the results in the corresponding elements of the two or four first source vectors. If one element value is numeric and the other is a quiet NaN, then the result is the numeric value.</para>
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<para>This instruction follows SME2.1 non-widening BFloat16 numerical behaviors corresponding to instructions that place their results in two or four SVE Z vectors.</para>
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<para>This instruction is unpredicated.</para>
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<para>ID_AA64SMFR0_EL1.B16B16 indicates whether this instruction is implemented.</para>
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</description>
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<status>Green</status>
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<predicated>False</predicated>
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<sm_policy>SM_1_only</sm_policy>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from 2 classes:</txt>
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<a href="#iclass_to_2reg">Two registers</a>
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<txt> and </txt>
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<a href="#iclass_to_4reg">Four registers</a>
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</classesintro>
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<iclass name="Two registers" oneof="2" id="iclass_to_2reg" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="ldstruct-regcount" value="to-2reg" />
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<docvar key="mnemonic" value="BFMINNM" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="FEAT_B16B16" feature="FEAT_B16B16" />
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</arch_variants>
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<regdiagram form="32" psname="BFMINNM-MZ.ZZV-2x1" tworows="1">
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<box hibit="31" width="8" settings="8">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="23" name="size<1>" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="22" name="size<0>" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Zm" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="6" settings="6">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="9" width="4" settings="4">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="5" name="op" settings="1">
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<c>1</c>
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</box>
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<box hibit="4" width="4" name="Zdn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="0" name="o2" settings="1">
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<c>1</c>
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</box>
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</regdiagram>
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<encoding name="bfminnm_mz_zzv_2x1" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="ldstruct-regcount" value="to-2reg" />
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<docvar key="mnemonic" value="BFMINNM" />
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</docvars>
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<asmtemplate><text>BFMINNM </text><text>{</text><text> </text><a link="sa_zdn1" hover="First scalable vector register of a multi-vector sequence (field Zdn)"><Zdn1></a><text>.H-</text><a link="sa_zdn2" hover="Second scalable vector register of a multi-vector sequence (field Zdn)"><Zdn2></a><text>.H </text><text>}</text><text>, </text><text>{</text><text> </text><a link="sa_zdn1" hover="First scalable vector register of a multi-vector sequence (field Zdn)"><Zdn1></a><text>.H-</text><a link="sa_zdn2" hover="Second scalable vector register of a multi-vector sequence (field Zdn)"><Zdn2></a><text>.H </text><text>}</text><text>, </text><a link="sa_zm" hover="Second source scalable vector register Z0-Z15 (field "Zm")"><Zm></a><text>.H</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="BFMINNM-MZ.ZZV-2x1" mylink="BFMINNM-MZ.ZZV-2x1" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSMEB16B16.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEB16B16()">HaveSMEB16B16</a>() then UNDEFINED;
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integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zdn:'0');
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
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constant integer nreg = 2;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Four registers" oneof="2" id="iclass_to_4reg" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="ldstruct-regcount" value="to-4reg" />
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<docvar key="mnemonic" value="BFMINNM" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="FEAT_B16B16" feature="FEAT_B16B16" />
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</arch_variants>
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<regdiagram form="32" psname="BFMINNM-MZ.ZZV-4x1" tworows="1">
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<box hibit="31" width="8" settings="8">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="23" name="size<1>" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="22" name="size<0>" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Zm" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="6" settings="6">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="4" settings="4">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="5" name="op" settings="1">
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<c>1</c>
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</box>
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<box hibit="4" width="3" name="Zdn" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="0" name="o2" settings="1">
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<c>1</c>
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</box>
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</regdiagram>
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<encoding name="bfminnm_mz_zzv_4x1" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="ldstruct-regcount" value="to-4reg" />
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<docvar key="mnemonic" value="BFMINNM" />
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</docvars>
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<asmtemplate><text>BFMINNM </text><text>{</text><text> </text><a link="sa_zdn1_1" hover="First scalable vector register of a multi-vector sequence (field Zdn)"><Zdn1></a><text>.H-</text><a link="sa_zdn4" hover="Fourth scalable vector register of a multi-vector sequence (field Zdn)"><Zdn4></a><text>.H </text><text>}</text><text>, </text><text>{</text><text> </text><a link="sa_zdn1_1" hover="First scalable vector register of a multi-vector sequence (field Zdn)"><Zdn1></a><text>.H-</text><a link="sa_zdn4" hover="Fourth scalable vector register of a multi-vector sequence (field Zdn)"><Zdn4></a><text>.H </text><text>}</text><text>, </text><a link="sa_zm" hover="Second source scalable vector register Z0-Z15 (field "Zm")"><Zm></a><text>.H</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="BFMINNM-MZ.ZZV-4x1" mylink="BFMINNM-MZ.ZZV-4x1" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSMEB16B16.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEB16B16()">HaveSMEB16B16</a>() then UNDEFINED;
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integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zdn:'00');
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
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constant integer nreg = 4;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="bfminnm_mz_zzv_2x1" symboldefcount="1">
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<symbol link="sa_zdn1"><Zdn1></symbol>
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<account encodedin="Zdn">
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<docvars>
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<docvar key="ldstruct-regcount" value="to-2reg" />
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</docvars>
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<intro>
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<para>For the two registers variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zdn" times 2.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="bfminnm_mz_zzv_4x1" symboldefcount="2">
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<symbol link="sa_zdn1_1"><Zdn1></symbol>
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<account encodedin="Zdn">
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<docvars>
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<docvar key="ldstruct-regcount" value="to-4reg" />
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</docvars>
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<intro>
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<para>For the four registers variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zdn" times 4.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="bfminnm_mz_zzv_4x1" symboldefcount="1">
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<symbol link="sa_zdn4"><Zdn4></symbol>
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<account encodedin="Zdn">
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<intro>
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<para>Is the name of the fourth scalable vector register of a multi-vector sequence, encoded as "Zdn" times 4 plus 3.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="bfminnm_mz_zzv_2x1" symboldefcount="1">
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<symbol link="sa_zdn2"><Zdn2></symbol>
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<account encodedin="Zdn">
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<intro>
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<para>Is the name of the second scalable vector register of a multi-vector sequence, encoded as "Zdn" times 2 plus 1.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="bfminnm_mz_zzv_2x1, bfminnm_mz_zzv_4x1" symboldefcount="1">
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<symbol link="sa_zm"><Zm></symbol>
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<account encodedin="Zm">
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<intro>
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<para>Is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="BFMINNM-MZ.ZZV-2x1" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEEnabled()">CheckStreamingSVEEnabled</a>();
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constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
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constant integer elements = VL DIV 16;
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array [0..3] of bits(VL) results;
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for r = 0 to nreg-1
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bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn+r, VL];
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bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
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for e = 0 to elements-1
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bits(16) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 16];
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bits(16) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 16];
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[results[r], e, 16] = <a link="impl-shared.BFMinNum.3" file="shared_pseudocode.xml" hover="function: bits(16) BFMinNum(bits(16) op1_in, bits(16) op2_in, FPCRType fpcr)">BFMinNum</a>(element1, element2, FPCR[]);
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for r = 0 to nreg-1
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<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn+r, VL] = results[r];</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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