mirror of
https://github.com/pound-emu/ballistic.git
synced 2026-01-31 01:15:21 +01:00
382 lines
21 KiB
XML
382 lines
21 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
|
|
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
|
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
|
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
|
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
|
|
|
<instructionsection id="bfmlal_za_zzv" title="BFMLAL (multiple and single vector)" type="instruction">
|
|
<docvars>
|
|
<docvar key="instr-class" value="mortlach2" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="BFMLAL" />
|
|
</docvars>
|
|
<heading>BFMLAL (multiple and single vector)</heading>
|
|
<desc>
|
|
<brief>Multi-vector BFloat16 floating-point multiply-add long by vector</brief>
|
|
<description>
|
|
<para>The instruction operates on one, two, or four ZA double-vector groups.</para>
|
|
<para>This BFloat16 floating-point multiply-add long instruction widens all 16-bit BFloat16 elements in the one, two, or four first source vectors and the second source vector to single-precision format, then multiplies the corresponding elements and destructively adds these values without intermediate rounding to the overlapping 32-bit single-precision elements of the one, two, or four ZA double-vector groups. The lowest of the two consecutive vector numbers forming the double-vector group within all, each half, or each quarter of the ZA array are selected by the sum of the vector select register and immediate offset, modulo all, half, or quarter the number of ZA array vectors.</para>
|
|
<para>The <arm-defined-word>vector group</arm-defined-word> symbol, <syntax>VGx2</syntax> or <syntax>VGx4</syntax>, indicates that the ZA operand consists of two or four ZA double-vector groups respectively. The <arm-defined-word>vector group</arm-defined-word> symbol is preferred for disassembly, but optional in assembler source code.</para>
|
|
<para>This instruction follows SME ZA-targeting floating-point behaviors.</para>
|
|
<para>This instruction is unpredicated.</para>
|
|
</description>
|
|
<status>Green</status>
|
|
<predicated>False</predicated>
|
|
<sm_policy>SM_1_only</sm_policy>
|
|
</desc>
|
|
<alias_list howmany="0"></alias_list>
|
|
<classes>
|
|
<classesintro count="3">
|
|
<txt>It has encodings from 3 classes:</txt>
|
|
<a href="#iclass_sme_vgx1_double">One ZA double-vector</a>
|
|
<txt>, </txt>
|
|
<a href="#iclass_sme_vgx2_double">Two ZA double-vectors</a>
|
|
<txt> and </txt>
|
|
<a href="#iclass_sme_vgx4_double">Four ZA double-vectors</a>
|
|
</classesintro>
|
|
<iclass name="One ZA double-vector" oneof="3" id="iclass_sme_vgx1_double" no_encodings="1" isa="A64">
|
|
<docvars>
|
|
<docvar key="instr-class" value="mortlach2" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="BFMLAL" />
|
|
<docvar key="sme-multireg" value="sme-vgx1-double" />
|
|
</docvars>
|
|
<iclassintro count="1"></iclassintro>
|
|
<arch_variants>
|
|
<arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
|
|
</arch_variants>
|
|
<regdiagram form="32" psname="BFMLAL-ZA.ZZV-1" tworows="1">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="op" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="bfmlal_za_zzv_1" oneofinclass="1" oneof="3" label="">
|
|
<docvars>
|
|
<docvar key="instr-class" value="mortlach2" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="BFMLAL" />
|
|
<docvar key="sme-multireg" value="sme-vgx1-double" />
|
|
</docvars>
|
|
<asmtemplate><text>BFMLAL ZA.S[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field "Rv")"><Wv></a><text>, </text><a link="sa_offsf" hover="Vector select offset, pointing to first of two consecutive vectors, encoded as "off3" field times 2 (field off3)"><offsf></a><text>:</text><a link="sa_offsl" hover="Vector select offset, pointing to last of two consecutive vectors, encoded as "off3" field times 2 plus 1 (field off3)"><offsl></a><text>], </text><a link="sa_zn" hover="First source scalable vector register (field "Zn")"><Zn></a><text>.H, </text><a link="sa_zm" hover="Second source scalable vector register Z0-Z15 (field "Zm")"><Zm></a><text>.H</text></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="BFMLAL-ZA.ZZV-1" mylink="BFMLAL-ZA.ZZV-1" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
|
|
integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
|
|
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
|
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
|
|
integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(off3:'0');
|
|
boolean sub_op = FALSE;
|
|
constant integer nreg = 1;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="Two ZA double-vectors" oneof="3" id="iclass_sme_vgx2_double" no_encodings="1" isa="A64">
|
|
<docvars>
|
|
<docvar key="instr-class" value="mortlach2" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="BFMLAL" />
|
|
<docvar key="sme-multireg" value="sme-vgx2-double" />
|
|
</docvars>
|
|
<iclassintro count="1"></iclassintro>
|
|
<arch_variants>
|
|
<arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
|
|
</arch_variants>
|
|
<regdiagram form="32" psname="BFMLAL-ZA.ZZV-2x1" tworows="1">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="op" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="off2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="bfmlal_za_zzv_2x1" oneofinclass="1" oneof="3" label="">
|
|
<docvars>
|
|
<docvar key="instr-class" value="mortlach2" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="BFMLAL" />
|
|
<docvar key="sme-multireg" value="sme-vgx2-double" />
|
|
</docvars>
|
|
<asmtemplate><text>BFMLAL ZA.S[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field "Rv")"><Wv></a><text>, </text><a link="sa_offsf_1" hover="Vector select offset, pointing to first of two consecutive vectors, encoded as "off2" field times 2 (field off2)"><offsf></a><text>:</text><a link="sa_offsl_1" hover="Vector select offset, pointing to last of two consecutive vectors, encoded as "off2" field times 2 plus 1 (field off2)"><offsl></a><a>{, VGx2}</a><text>], </text><text>{</text><text> </text><a link="sa_zn1" hover="First scalable vector register of a multi-vector sequence, encoded as "Zn" (field Zn)"><Zn1></a><text>.H-</text><a link="sa_zn2" hover="Second scalable vector register of a multi-vector sequence (field Zn)"><Zn2></a><text>.H </text><text>}</text><text>, </text><a link="sa_zm" hover="Second source scalable vector register Z0-Z15 (field "Zm")"><Zm></a><text>.H</text></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="BFMLAL-ZA.ZZV-2x1" mylink="BFMLAL-ZA.ZZV-2x1" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
|
|
integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
|
|
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
|
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
|
|
integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(off2:'0');
|
|
boolean sub_op = FALSE;
|
|
constant integer nreg = 2;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="Four ZA double-vectors" oneof="3" id="iclass_sme_vgx4_double" no_encodings="1" isa="A64">
|
|
<docvars>
|
|
<docvar key="instr-class" value="mortlach2" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="BFMLAL" />
|
|
<docvar key="sme-multireg" value="sme-vgx4-double" />
|
|
</docvars>
|
|
<iclassintro count="1"></iclassintro>
|
|
<arch_variants>
|
|
<arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
|
|
</arch_variants>
|
|
<regdiagram form="32" psname="BFMLAL-ZA.ZZV-4x1" tworows="1">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="op" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="off2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="bfmlal_za_zzv_4x1" oneofinclass="1" oneof="3" label="">
|
|
<docvars>
|
|
<docvar key="instr-class" value="mortlach2" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="BFMLAL" />
|
|
<docvar key="sme-multireg" value="sme-vgx4-double" />
|
|
</docvars>
|
|
<asmtemplate><text>BFMLAL ZA.S[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field "Rv")"><Wv></a><text>, </text><a link="sa_offsf_1" hover="Vector select offset, pointing to first of two consecutive vectors, encoded as "off2" field times 2 (field off2)"><offsf></a><text>:</text><a link="sa_offsl_1" hover="Vector select offset, pointing to last of two consecutive vectors, encoded as "off2" field times 2 plus 1 (field off2)"><offsl></a><a>{, VGx4}</a><text>], </text><text>{</text><text> </text><a link="sa_zn1" hover="First scalable vector register of a multi-vector sequence, encoded as "Zn" (field Zn)"><Zn1></a><text>.H-</text><a link="sa_zn4" hover="Fourth scalable vector register of a multi-vector sequence (field Zn)"><Zn4></a><text>.H </text><text>}</text><text>, </text><a link="sa_zm" hover="Second source scalable vector register Z0-Z15 (field "Zm")"><Zm></a><text>.H</text></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="BFMLAL-ZA.ZZV-4x1" mylink="BFMLAL-ZA.ZZV-4x1" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
|
|
integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
|
|
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
|
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
|
|
integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(off2:'0');
|
|
boolean sub_op = FALSE;
|
|
constant integer nreg = 4;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="bfmlal_za_zzv_1, bfmlal_za_zzv_2x1, bfmlal_za_zzv_4x1" symboldefcount="1">
|
|
<symbol link="sa_wv"><Wv></symbol>
|
|
<account encodedin="Rv">
|
|
<intro>
|
|
<para>Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="bfmlal_za_zzv_1" symboldefcount="1">
|
|
<symbol link="sa_offsf"><offsf></symbol>
|
|
<account encodedin="off3">
|
|
<docvars>
|
|
<docvar key="sme-multireg" value="sme-vgx1-double" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For the one ZA double-vector variant: is the vector select offset, pointing to first of two consecutive vectors, encoded as "off3" field times 2.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="bfmlal_za_zzv_2x1, bfmlal_za_zzv_4x1" symboldefcount="2">
|
|
<symbol link="sa_offsf_1"><offsf></symbol>
|
|
<account encodedin="off2">
|
|
<intro>
|
|
<para>For the four ZA double-vectors and two ZA double-vectors variant: is the vector select offset, pointing to first of two consecutive vectors, encoded as "off2" field times 2.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="bfmlal_za_zzv_1" symboldefcount="1">
|
|
<symbol link="sa_offsl"><offsl></symbol>
|
|
<account encodedin="off3">
|
|
<docvars>
|
|
<docvar key="sme-multireg" value="sme-vgx1-double" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For the one ZA double-vector variant: is the vector select offset, pointing to last of two consecutive vectors, encoded as "off3" field times 2 plus 1.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="bfmlal_za_zzv_2x1, bfmlal_za_zzv_4x1" symboldefcount="2">
|
|
<symbol link="sa_offsl_1"><offsl></symbol>
|
|
<account encodedin="off2">
|
|
<intro>
|
|
<para>For the four ZA double-vectors and two ZA double-vectors variant: is the vector select offset, pointing to last of two consecutive vectors, encoded as "off2" field times 2 plus 1.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="bfmlal_za_zzv_1" symboldefcount="1">
|
|
<symbol link="sa_zn"><Zn></symbol>
|
|
<account encodedin="Zn">
|
|
<intro>
|
|
<para>Is the name of the first source scalable vector register, encoded in the "Zn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="bfmlal_za_zzv_2x1, bfmlal_za_zzv_4x1" symboldefcount="1">
|
|
<symbol link="sa_zn1"><Zn1></symbol>
|
|
<account encodedin="Zn">
|
|
<intro>
|
|
<para>Is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zn".</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="bfmlal_za_zzv_4x1" symboldefcount="1">
|
|
<symbol link="sa_zn4"><Zn4></symbol>
|
|
<account encodedin="Zn">
|
|
<intro>
|
|
<para>Is the name of the fourth scalable vector register of a multi-vector sequence, encoded as "Zn" plus 3 modulo 32.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="bfmlal_za_zzv_2x1" symboldefcount="1">
|
|
<symbol link="sa_zn2"><Zn2></symbol>
|
|
<account encodedin="Zn">
|
|
<intro>
|
|
<para>Is the name of the second scalable vector register of a multi-vector sequence, encoded as "Zn" plus 1 modulo 32.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="bfmlal_za_zzv_1, bfmlal_za_zzv_2x1, bfmlal_za_zzv_4x1" symboldefcount="1">
|
|
<symbol link="sa_zm"><Zm></symbol>
|
|
<account encodedin="Zm">
|
|
<intro>
|
|
<para>Is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="BFMLAL-ZA.ZZV-1" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckStreamingSVEAndZAEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEAndZAEnabled()">CheckStreamingSVEAndZAEnabled</a>();
|
|
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
|
constant integer elements = VL DIV 32;
|
|
integer vectors = VL DIV 8;
|
|
integer vstride = vectors DIV nreg;
|
|
bits(32) vbase = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[v, 32];
|
|
integer vec = (<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(vbase) + offset) MOD vstride;
|
|
bits(VL) result;
|
|
vec = vec - (vec MOD 2);
|
|
|
|
for r = 0 to nreg-1
|
|
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[(n+r) MOD 32, VL];
|
|
bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
|
for i = 0 to 1
|
|
bits(VL) operand3 = <a link="impl-aarch64.ZAvector.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) ZAvector[integer index, integer width]">ZAvector</a>[vec + i, VL];
|
|
for e = 0 to elements-1
|
|
bits(16) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2 * e + i, 16];
|
|
bits(16) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2 * e + i, 16];
|
|
bits(32) element3 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 32];
|
|
if sub_op then element1 = <a link="impl-shared.BFNeg.1" file="shared_pseudocode.xml" hover="function: bits(16) BFNeg(bits(16) op)">BFNeg</a>(element1);
|
|
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 32] = <a link="impl-shared.BFMulAddH_ZA.4" file="shared_pseudocode.xml" hover="function: bits(N) BFMulAddH_ZA(bits(N) addend, bits(N DIV 2) op1, bits(N DIV 2) op2, FPCRType fpcr)">BFMulAddH_ZA</a>(element3, element1, element2, FPCR[]);
|
|
<a link="impl-aarch64.ZAvector.write.2" file="shared_pseudocode.xml" hover="accessor: ZAvector[integer index, integer width] = bits(width) value">ZAvector</a>[vec + i, VL] = result;
|
|
vec = vec + vstride;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|