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160 lines
9.8 KiB
XML
160 lines
9.8 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="BFMMLA_advsimd" title="BFMMLA -- A64" type="instruction">
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<docvars>
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<docvar key="advsimd-type" value="simd" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="BFMMLA" />
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</docvars>
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<heading>BFMMLA</heading>
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<desc>
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<brief>
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<para>BFloat16 floating-point matrix multiply-accumulate into 2x2 matrix</para>
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</brief>
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<authored>
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<para>BFloat16 floating-point matrix multiply-accumulate into 2x2 matrix.</para>
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<para>If FEAT_EBF16 is not implemented or <xref linkend="AArch64.fpcr">FPCR</xref>.EBF is 0, this instruction:</para>
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<list type="unordered">
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<listitem><content>Performs two unfused sums-of-products within each two pairs of adjacent BFloat16 elements while multiplying the 2x4 matrix of BFloat16 values in the first source vector with the 4x2 matrix of BFloat16 values in the second source vector. The intermediate single-precision products are rounded before they are summed and the intermediate sum is rounded before accumulation into the 2x2 single-precision matrix in the destination vector. This is equivalent to accumulating two 2-way unfused dot products per destination element.</content></listitem>
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<listitem><content>Uses the non-IEEE 754 Round-to-Odd rounding mode, which forces bit 0 of an inexact result to 1, and rounds an overflow to an appropriately signed Infinity.</content></listitem>
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<listitem><content>Flushes denormalized inputs and results to zero, as if <xref linkend="AArch64.fpcr">FPCR</xref>.{FZ, FIZ} is {1, 1}.</content></listitem>
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<listitem><content>Disables alternative floating point behaviors, as if <xref linkend="AArch64.fpcr">FPCR</xref>.AH is 0.</content></listitem>
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</list>
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<para>If FEAT_EBF16 is implemented and <xref linkend="AArch64.fpcr">FPCR</xref>.EBF is 1, then this instruction:</para>
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<list type="unordered">
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<listitem><content>Performs two fused sums-of-products within each two pairs of adjacent BFloat16 elements while multiplying the 2x4 matrix of BFloat16 values in the first source vector with the 4x2 matrix of BFloat16 values in the second source vector. The intermediate single-precision products are not rounded before they are summed, but the intermediate sum is rounded before accumulation into the 2x2 single-precision matrix in the destination vector. This is equivalent to accumulating two 2-way fused dot products per destination element.</content></listitem>
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<listitem><content>Follows all other floating-point behaviors that apply to single-precision arithmetic, as governed by <xref linkend="AArch64.fpcr">FPCR</xref>.RMode, <xref linkend="AArch64.fpcr">FPCR</xref>.FZ, <xref linkend="AArch64.fpcr">FPCR</xref>.AH, and <xref linkend="AArch64.fpcr">FPCR</xref>.FIZ.</content></listitem>
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</list>
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<para>Irrespective of FEAT_EBF16 and <xref linkend="AArch64.fpcr">FPCR</xref>.EBF, this instruction:</para>
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<list type="unordered">
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<listitem><content>Does not modify the cumulative <xref linkend="AArch64.fpsr">FPSR</xref> exception bits (IDC, IXC, UFC, OFC, DZC, and IOC).</content></listitem>
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<listitem><content>Disables trapped floating-point exceptions, as if the <xref linkend="AArch64.fpcr">FPCR</xref> trap enable bits (IDE, IXE, UFE, OFE, DZE, and IOE) are all zero.</content></listitem>
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<listitem><content>Generates only the default NaN, as if <xref linkend="AArch64.fpcr">FPCR</xref>.DN is 1.</content></listitem>
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</list>
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<para><xref linkend="AArch64.id_aa64isar1_el1">ID_AA64ISAR1_EL1</xref>.BF16 indicates whether this instruction is supported.</para>
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<note>
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<para>Arm expects that the BFMMLA instruction will deliver a peak BFloat16 multiply throughput that is at least as high as can be achieved using two BFDOT instructions, with a goal that it should have significantly higher throughput.</para>
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</note>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="Vector" oneof="1" id="iclass_simd" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="advsimd-type" value="simd" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="BFMMLA" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.6" feature="FEAT_BF16" />
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</arch_variants>
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<regdiagram form="32" psname="aarch64/instrs/vector/bfmmla">
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<box hibit="31" settings="1">
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<c>0</c>
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</box>
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<box hibit="30" name="Q" settings="1">
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<c>1</c>
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</box>
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<box hibit="29" name="U" settings="1">
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<c>1</c>
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</box>
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<box hibit="28" width="5" settings="5">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" width="2" name="size" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="21" settings="1">
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<c>0</c>
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</box>
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<box hibit="20" width="5" name="Rm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" settings="1">
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<c>1</c>
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</box>
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<box hibit="14" width="4" name="opcode" settings="4">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="10" settings="1">
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<c>1</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="BFMMLA_asimdsame2_E" oneofinclass="1" oneof="1" label="">
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<docvars>
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<docvar key="advsimd-type" value="simd" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="BFMMLA" />
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</docvars>
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<asmtemplate><text>BFMMLA </text><a link="sa_vd" hover="SIMD&FP third source and destination register (field "Rd")"><Vd></a><text>.4S, </text><a link="sa_vn" hover="First SIMD&FP source register (field "Rn")"><Vn></a><text>.8H, </text><a link="sa_vm" hover="Second SIMD&FP source register (field "Rm")"><Vm></a><text>.8H</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/bfmmla" mylink="aarch64.instrs.vector.bfmmla" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveBF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveBF16Ext()">HaveBF16Ext</a>() then UNDEFINED;
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="BFMMLA_asimdsame2_E" symboldefcount="1">
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<symbol link="sa_vd"><Vd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the name of the SIMD&FP third source and destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="BFMMLA_asimdsame2_E" symboldefcount="1">
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<symbol link="sa_vn"><Vn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the name of the first SIMD&FP source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="BFMMLA_asimdsame2_E" symboldefcount="1">
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<symbol link="sa_vm"><Vm></symbol>
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<account encodedin="Rm">
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<intro>
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<para>Is the name of the second SIMD&FP source register, encoded in the "Rm" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/bfmmla" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
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bits(128) op1 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, 128];
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bits(128) op2 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[m, 128];
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bits(128) acc = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[d, 128];
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<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = <a link="impl-shared.BFMatMulAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) BFMatMulAdd(bits(N) addend, bits(N) op1, bits(N) op2)">BFMatMulAdd</a>(acc, op1, op2);</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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