mirror of
https://github.com/pound-emu/ballistic.git
synced 2026-01-31 01:15:21 +01:00
381 lines
26 KiB
XML
381 lines
26 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
|
|
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
|
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
|
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
|
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
|
|
|
<instructionsection id="CASP" title="CASP, CASPA, CASPAL, CASPL -- A64" type="instruction">
|
|
<docvars>
|
|
<docvar key="address-form" value="base-register" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="A64" />
|
|
</docvars>
|
|
<heading>CASP, CASPA, CASPAL, CASPL</heading>
|
|
<desc>
|
|
<brief>
|
|
<para>Compare and Swap Pair of words or doublewords in memory</para>
|
|
</brief>
|
|
<authored>
|
|
<para>Compare and Swap Pair of words or doublewords in memory reads a pair of 32-bit words or 64-bit doublewords from memory, and compares them against the values held in the first pair of registers. If the comparison is equal, the values in the second pair of registers are written to memory. If the writes are performed, the reads and writes occur atomically such that no other modification of the memory location can take place between the reads and writes.</para>
|
|
<list type="unordered">
|
|
<listitem><content><instruction>CASPA</instruction> and <instruction>CASPAL</instruction> load from memory with acquire semantics.</content></listitem>
|
|
<listitem><content><instruction>CASPL</instruction> and <instruction>CASPAL</instruction> store to memory with release semantics.</content></listitem>
|
|
<listitem><content><instruction>CASP</instruction> has neither acquire nor release semantics.</content></listitem>
|
|
</list>
|
|
<para>For more information about memory ordering semantics, see <xref linkend="BEIHCHEF">Load-Acquire, Store-Release</xref>.</para>
|
|
<para>For information about memory accesses, see <xref linkend="CHDIIIBB">Load/Store addressing modes</xref>.</para>
|
|
<para>The architecture permits that the data read clears any exclusive monitors associated with that location, even if the compare subsequently fails.</para>
|
|
<para>If the instruction generates a synchronous Data Abort, the registers which are compared and loaded, that is <syntax><Ws></syntax> and <syntax><W(s+1)></syntax>, or <syntax><Xs></syntax> and <syntax><X(s+1)></syntax>, are restored to the values held in the registers before the instruction was executed.</para>
|
|
</authored>
|
|
</desc>
|
|
<alias_list howmany="0"></alias_list>
|
|
<classes>
|
|
<iclass name="No offset" oneof="1" id="iclass_base_register" no_encodings="8" isa="A64">
|
|
<docvars>
|
|
<docvar key="address-form" value="base-register" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="A64" />
|
|
</docvars>
|
|
<iclassintro count="8"></iclassintro>
|
|
<arch_variants>
|
|
<arch_variant name="ARMv8.1" feature="FEAT_LSE" />
|
|
</arch_variants>
|
|
<regdiagram form="32" psname="aarch64/instrs/memory/atomicops/cas/pair" tworows="1">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" name="o2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" name="o1" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rs" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" name="o0" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="5" name="Rt2" usename="1" settings="5" psbits="xxxxx">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="CASP_CP32_comswappr" oneofinclass="8" oneof="8" label="32-bit CASP" bitdiffs="sz == 0 && L == 0 && o0 == 0">
|
|
<docvars>
|
|
<docvar key="address-form" value="base-register" />
|
|
<docvar key="address-form-reg-type" value="base-register-pair-32" />
|
|
<docvar key="atomic-ops" value="CASP-pair-32" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="CASP" />
|
|
<docvar key="reg-type" value="pair-32" />
|
|
</docvars>
|
|
<box hibit="30" width="1" name="sz">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" width="1" name="L">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="o0">
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate><text>CASP </text><a link="sa_ws" hover="First 32-bit general-purpose register to be compared and loaded (field "Rs")"><Ws></a><text>, </text><a link="sa_w_s_plus_1" hover="Second 32-bit general-purpose register to be compared and loaded"><W(s+1)></a><text>, </text><a link="sa_wt" hover="First 32-bit general-purpose register to be conditionally stored (field "Rt")"><Wt></a><text>, </text><a link="sa_w_t_plus_1" hover="Second 32-bit general-purpose register to be conditionally stored"><W(t+1)></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{,#0}</text><text>]</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="CASPA_CP32_comswappr" oneofinclass="8" oneof="8" label="32-bit CASPA" bitdiffs="sz == 0 && L == 1 && o0 == 0">
|
|
<docvars>
|
|
<docvar key="address-form" value="base-register" />
|
|
<docvar key="address-form-reg-type" value="base-register-pair-32" />
|
|
<docvar key="atomic-ops" value="CASPA-pair-32" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="CASPA" />
|
|
<docvar key="reg-type" value="pair-32" />
|
|
</docvars>
|
|
<box hibit="30" width="1" name="sz">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" width="1" name="L">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="o0">
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate><text>CASPA </text><a link="sa_ws" hover="First 32-bit general-purpose register to be compared and loaded (field "Rs")"><Ws></a><text>, </text><a link="sa_w_s_plus_1" hover="Second 32-bit general-purpose register to be compared and loaded"><W(s+1)></a><text>, </text><a link="sa_wt" hover="First 32-bit general-purpose register to be conditionally stored (field "Rt")"><Wt></a><text>, </text><a link="sa_w_t_plus_1" hover="Second 32-bit general-purpose register to be conditionally stored"><W(t+1)></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{,#0}</text><text>]</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="CASPAL_CP32_comswappr" oneofinclass="8" oneof="8" label="32-bit CASPAL" bitdiffs="sz == 0 && L == 1 && o0 == 1">
|
|
<docvars>
|
|
<docvar key="address-form" value="base-register" />
|
|
<docvar key="address-form-reg-type" value="base-register-pair-32" />
|
|
<docvar key="atomic-ops" value="CASPAL-pair-32" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="CASPAL" />
|
|
<docvar key="reg-type" value="pair-32" />
|
|
</docvars>
|
|
<box hibit="30" width="1" name="sz">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" width="1" name="L">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="o0">
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>CASPAL </text><a link="sa_ws" hover="First 32-bit general-purpose register to be compared and loaded (field "Rs")"><Ws></a><text>, </text><a link="sa_w_s_plus_1" hover="Second 32-bit general-purpose register to be compared and loaded"><W(s+1)></a><text>, </text><a link="sa_wt" hover="First 32-bit general-purpose register to be conditionally stored (field "Rt")"><Wt></a><text>, </text><a link="sa_w_t_plus_1" hover="Second 32-bit general-purpose register to be conditionally stored"><W(t+1)></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{,#0}</text><text>]</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="CASPL_CP32_comswappr" oneofinclass="8" oneof="8" label="32-bit CASPL" bitdiffs="sz == 0 && L == 0 && o0 == 1">
|
|
<docvars>
|
|
<docvar key="address-form" value="base-register" />
|
|
<docvar key="address-form-reg-type" value="base-register-pair-32" />
|
|
<docvar key="atomic-ops" value="CASPL-pair-32" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="CASPL" />
|
|
<docvar key="reg-type" value="pair-32" />
|
|
</docvars>
|
|
<box hibit="30" width="1" name="sz">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" width="1" name="L">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="o0">
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>CASPL </text><a link="sa_ws" hover="First 32-bit general-purpose register to be compared and loaded (field "Rs")"><Ws></a><text>, </text><a link="sa_w_s_plus_1" hover="Second 32-bit general-purpose register to be compared and loaded"><W(s+1)></a><text>, </text><a link="sa_wt" hover="First 32-bit general-purpose register to be conditionally stored (field "Rt")"><Wt></a><text>, </text><a link="sa_w_t_plus_1" hover="Second 32-bit general-purpose register to be conditionally stored"><W(t+1)></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{,#0}</text><text>]</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="CASP_CP64_comswappr" oneofinclass="8" oneof="8" label="64-bit CASP" bitdiffs="sz == 1 && L == 0 && o0 == 0">
|
|
<docvars>
|
|
<docvar key="address-form" value="base-register" />
|
|
<docvar key="address-form-reg-type" value="base-register-pair-64" />
|
|
<docvar key="atomic-ops" value="CASP-pair-64" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="CASP" />
|
|
<docvar key="reg-type" value="pair-64" />
|
|
</docvars>
|
|
<box hibit="30" width="1" name="sz">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" width="1" name="L">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="o0">
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate><text>CASP </text><a link="sa_xs" hover="First 64-bit general-purpose register to be compared and loaded (field "Rs")"><Xs></a><text>, </text><a link="sa_x_s_plus_1" hover="Second 64-bit general-purpose register to be compared and loaded"><X(s+1)></a><text>, </text><a link="sa_xt" hover="First 64-bit general-purpose register to be conditionally stored (field "Rt")"><Xt></a><text>, </text><a link="sa_x_t_plus_1" hover="Second 64-bit general-purpose register to be conditionally stored"><X(t+1)></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{,#0}</text><text>]</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="CASPA_CP64_comswappr" oneofinclass="8" oneof="8" label="64-bit CASPA" bitdiffs="sz == 1 && L == 1 && o0 == 0">
|
|
<docvars>
|
|
<docvar key="address-form" value="base-register" />
|
|
<docvar key="address-form-reg-type" value="base-register-pair-64" />
|
|
<docvar key="atomic-ops" value="CASPA-pair-64" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="CASPA" />
|
|
<docvar key="reg-type" value="pair-64" />
|
|
</docvars>
|
|
<box hibit="30" width="1" name="sz">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" width="1" name="L">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="o0">
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate><text>CASPA </text><a link="sa_xs" hover="First 64-bit general-purpose register to be compared and loaded (field "Rs")"><Xs></a><text>, </text><a link="sa_x_s_plus_1" hover="Second 64-bit general-purpose register to be compared and loaded"><X(s+1)></a><text>, </text><a link="sa_xt" hover="First 64-bit general-purpose register to be conditionally stored (field "Rt")"><Xt></a><text>, </text><a link="sa_x_t_plus_1" hover="Second 64-bit general-purpose register to be conditionally stored"><X(t+1)></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{,#0}</text><text>]</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="CASPAL_CP64_comswappr" oneofinclass="8" oneof="8" label="64-bit CASPAL" bitdiffs="sz == 1 && L == 1 && o0 == 1">
|
|
<docvars>
|
|
<docvar key="address-form" value="base-register" />
|
|
<docvar key="address-form-reg-type" value="base-register-pair-64" />
|
|
<docvar key="atomic-ops" value="CASPAL-pair-64" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="CASPAL" />
|
|
<docvar key="reg-type" value="pair-64" />
|
|
</docvars>
|
|
<box hibit="30" width="1" name="sz">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" width="1" name="L">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="o0">
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>CASPAL </text><a link="sa_xs" hover="First 64-bit general-purpose register to be compared and loaded (field "Rs")"><Xs></a><text>, </text><a link="sa_x_s_plus_1" hover="Second 64-bit general-purpose register to be compared and loaded"><X(s+1)></a><text>, </text><a link="sa_xt" hover="First 64-bit general-purpose register to be conditionally stored (field "Rt")"><Xt></a><text>, </text><a link="sa_x_t_plus_1" hover="Second 64-bit general-purpose register to be conditionally stored"><X(t+1)></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{,#0}</text><text>]</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="CASPL_CP64_comswappr" oneofinclass="8" oneof="8" label="64-bit CASPL" bitdiffs="sz == 1 && L == 0 && o0 == 1">
|
|
<docvars>
|
|
<docvar key="address-form" value="base-register" />
|
|
<docvar key="address-form-reg-type" value="base-register-pair-64" />
|
|
<docvar key="atomic-ops" value="CASPL-pair-64" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="CASPL" />
|
|
<docvar key="reg-type" value="pair-64" />
|
|
</docvars>
|
|
<box hibit="30" width="1" name="sz">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" width="1" name="L">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="o0">
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>CASPL </text><a link="sa_xs" hover="First 64-bit general-purpose register to be compared and loaded (field "Rs")"><Xs></a><text>, </text><a link="sa_x_s_plus_1" hover="Second 64-bit general-purpose register to be compared and loaded"><X(s+1)></a><text>, </text><a link="sa_xt" hover="First 64-bit general-purpose register to be conditionally stored (field "Rt")"><Xt></a><text>, </text><a link="sa_x_t_plus_1" hover="Second 64-bit general-purpose register to be conditionally stored"><X(t+1)></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{,#0}</text><text>]</text></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/memory/atomicops/cas/pair" mylink="aarch64.instrs.memory.atomicops.cas.pair" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveAtomicExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAtomicExt()">HaveAtomicExt</a>() then UNDEFINED;
|
|
if Rs<0> == '1' then UNDEFINED;
|
|
if Rt<0> == '1' then UNDEFINED;
|
|
|
|
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
|
integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);
|
|
integer s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);
|
|
|
|
integer datasize = 32 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
|
|
integer regsize = datasize;
|
|
boolean acquire = L == '1';
|
|
boolean release = o0 == '1';
|
|
boolean tagchecked = n != 31;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="CASP_CP32_comswappr, CASPA_CP32_comswappr, CASPL_CP32_comswappr, CASPAL_CP32_comswappr" symboldefcount="1">
|
|
<symbol link="sa_ws"><Ws></symbol>
|
|
<account encodedin="Rs">
|
|
<intro>
|
|
<para>Is the 32-bit name of the first general-purpose register to be compared and loaded, encoded in the "Rs" field. <Ws> must be an even-numbered register.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="CASP_CP32_comswappr, CASPA_CP32_comswappr, CASPL_CP32_comswappr, CASPAL_CP32_comswappr" symboldefcount="1">
|
|
<symbol link="sa_w_s_plus_1"><W(s+1)></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>Is the 32-bit name of the second general-purpose register to be compared and loaded.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="CASP_CP32_comswappr, CASPA_CP32_comswappr, CASPL_CP32_comswappr, CASPAL_CP32_comswappr" symboldefcount="1">
|
|
<symbol link="sa_wt"><Wt></symbol>
|
|
<account encodedin="Rt">
|
|
<intro>
|
|
<para>Is the 32-bit name of the first general-purpose register to be conditionally stored, encoded in the "Rt" field. <Wt> must be an even-numbered register.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="CASP_CP32_comswappr, CASPA_CP32_comswappr, CASPL_CP32_comswappr, CASPAL_CP32_comswappr" symboldefcount="1">
|
|
<symbol link="sa_w_t_plus_1"><W(t+1)></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>Is the 32-bit name of the second general-purpose register to be conditionally stored.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="CASP_CP64_comswappr, CASPA_CP64_comswappr, CASPL_CP64_comswappr, CASPAL_CP64_comswappr" symboldefcount="1">
|
|
<symbol link="sa_xs"><Xs></symbol>
|
|
<account encodedin="Rs">
|
|
<intro>
|
|
<para>Is the 64-bit name of the first general-purpose register to be compared and loaded, encoded in the "Rs" field. <Xs> must be an even-numbered register.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="CASP_CP64_comswappr, CASPA_CP64_comswappr, CASPL_CP64_comswappr, CASPAL_CP64_comswappr" symboldefcount="1">
|
|
<symbol link="sa_x_s_plus_1"><X(s+1)></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>Is the 64-bit name of the second general-purpose register to be compared and loaded.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="CASP_CP64_comswappr, CASPA_CP64_comswappr, CASPL_CP64_comswappr, CASPAL_CP64_comswappr" symboldefcount="1">
|
|
<symbol link="sa_xt"><Xt></symbol>
|
|
<account encodedin="Rt">
|
|
<intro>
|
|
<para>Is the 64-bit name of the first general-purpose register to be conditionally stored, encoded in the "Rt" field. <Xt> must be an even-numbered register.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="CASP_CP64_comswappr, CASPA_CP64_comswappr, CASPL_CP64_comswappr, CASPAL_CP64_comswappr" symboldefcount="1">
|
|
<symbol link="sa_x_t_plus_1"><X(t+1)></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>Is the 64-bit name of the second general-purpose register to be conditionally stored.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="CASP_CP32_comswappr, CASP_CP64_comswappr, CASPA_CP32_comswappr, CASPA_CP64_comswappr, CASPL_CP32_comswappr, CASPL_CP64_comswappr, CASPAL_CP32_comswappr, CASPAL_CP64_comswappr" symboldefcount="1">
|
|
<symbol link="sa_xn_sp"><Xn|SP></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/memory/atomicops/cas/pair" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(64) address;
|
|
bits(2*datasize) comparevalue;
|
|
bits(2*datasize) newvalue;
|
|
bits(2*datasize) data;
|
|
|
|
bits(datasize) s1 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[s, datasize];
|
|
bits(datasize) s2 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[s+1, datasize];
|
|
bits(datasize) t1 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[t, datasize];
|
|
bits(datasize) t2 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[t+1, datasize];
|
|
|
|
<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescAtomicOp.4" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescAtomicOp(MemAtomicOp modop, boolean acquire, boolean release, boolean tagchecked)">CreateAccDescAtomicOp</a>(<a link="MemAtomicOp_CAS" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_CAS</a>, acquire, release, tagchecked);
|
|
|
|
comparevalue = if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(accdesc.acctype) then s1:s2 else s2:s1;
|
|
newvalue = if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(accdesc.acctype) then t1:t2 else t2:t1;
|
|
if n == 31 then
|
|
<a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
|
|
address = <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[];
|
|
else
|
|
address = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
|
|
|
|
data = <a link="impl-aarch64.MemAtomic.4" file="shared_pseudocode.xml" hover="function: bits(size) MemAtomic(bits(64) address, bits(size) cmpoperand, bits(size) operand, AccessDescriptor accdesc_in)">MemAtomic</a>(address, comparevalue, newvalue, accdesc);
|
|
|
|
if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(accdesc.acctype) then
|
|
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[s, datasize] = data<2*datasize-1:datasize>;
|
|
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[s+1, datasize] = data<datasize-1:0>;
|
|
else
|
|
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[s, datasize] = data<datasize-1:0>;
|
|
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[s+1, datasize] = data<2*datasize-1:datasize>;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|