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171 lines
8.9 KiB
XML
171 lines
8.9 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="CMP_SUBS_addsub_imm" title="CMP (immediate) -- A64" type="alias">
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<docvars>
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<docvar key="alias_mnemonic" value="CMP" />
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<docvar key="cond-setting" value="S" />
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<docvar key="immediate-type" value="imm12u" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SUBS" />
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</docvars>
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<heading>CMP (immediate)</heading>
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<desc>
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<brief>
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<para>Compare (immediate)</para>
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</brief>
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<authored>
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<para>Compare (immediate) subtracts an optionally-shifted immediate value from a register value. It updates the condition flags based on the result, and discards the result.</para>
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</authored>
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</desc>
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<operationalnotes>
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<para>If PSTATE.DIT is 1:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<aliasto refiform="subs_addsub_imm.xml" iformid="SUBS_addsub_imm">SUBS (immediate)</aliasto>
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<classes>
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<iclass name="Setting the condition flags" oneof="1" id="iclass_s" no_encodings="2" isa="A64">
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<docvars>
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<docvar key="cond-setting" value="S" />
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<docvar key="immediate-type" value="imm12u" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SUBS" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/integer/arithmetic/add-sub/immediate" tworows="1">
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<box hibit="31" name="sf" usename="1">
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<c></c>
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</box>
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<box hibit="30" name="op" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="29" name="S" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="28" width="6" settings="6">
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="22" name="sh" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="12" name="imm12" usename="1">
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<c colspan="12"></c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1" settings="5" psbits="xxxxx">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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</regdiagram>
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<encoding name="CMP_SUBS_32S_addsub_imm" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0">
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<docvars>
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<docvar key="alias_mnemonic" value="CMP" />
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<docvar key="cond-setting" value="S" />
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<docvar key="datatype" value="32" />
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<docvar key="immediate-type" value="imm12u" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SUBS" />
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</docvars>
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<box hibit="31" width="1" name="sf">
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<c>0</c>
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</box>
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<asmtemplate><text>CMP </text><a link="sa_wn_wsp" hover="32-bit source general-purpose register or WSP (field "Rn")"><Wn|WSP></a><text>, #</text><a link="sa_imm" hover="Unsigned immediate [0-4095] (field "imm12")"><imm></a><text>{</text><text>, </text><a link="sa_shift" hover="Optional left shift to apply to the immediate, default LSL #0 (field "sh") [LSL #0,LSL #12]"><shift></a><text>}</text></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="subs_addsub_imm.xml#SUBS_32S_addsub_imm">SUBS</a><text> WZR, </text><a link="sa_wn_wsp" hover="32-bit source general-purpose register or WSP (field "Rn")"><Wn|WSP></a><text>, #</text><a link="sa_imm" hover="Unsigned immediate [0-4095] (field "imm12")"><imm></a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Optional left shift to apply to the immediate, default LSL #0 (field "sh") [LSL #0,LSL #12]"><shift></a><text>}</text></asmtemplate>
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<aliascond>Unconditionally</aliascond>
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</equivalent_to>
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</encoding>
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<encoding name="CMP_SUBS_64S_addsub_imm" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
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<docvars>
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<docvar key="alias_mnemonic" value="CMP" />
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<docvar key="cond-setting" value="S" />
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<docvar key="datatype" value="64" />
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<docvar key="immediate-type" value="imm12u" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SUBS" />
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</docvars>
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<box hibit="31" width="1" name="sf">
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<c>1</c>
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</box>
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<asmtemplate><text>CMP </text><a link="sa_xn_sp" hover="64-bit source general-purpose register or SP (field "Rn")"><Xn|SP></a><text>, #</text><a link="sa_imm" hover="Unsigned immediate [0-4095] (field "imm12")"><imm></a><text>{</text><text>, </text><a link="sa_shift" hover="Optional left shift to apply to the immediate, default LSL #0 (field "sh") [LSL #0,LSL #12]"><shift></a><text>}</text></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="subs_addsub_imm.xml#SUBS_64S_addsub_imm">SUBS</a><text> XZR, </text><a link="sa_xn_sp" hover="64-bit source general-purpose register or SP (field "Rn")"><Xn|SP></a><text>, #</text><a link="sa_imm" hover="Unsigned immediate [0-4095] (field "imm12")"><imm></a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Optional left shift to apply to the immediate, default LSL #0 (field "sh") [LSL #0,LSL #12]"><shift></a><text>}</text></asmtemplate>
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<aliascond>Unconditionally</aliascond>
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</equivalent_to>
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</encoding>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="CMP_SUBS_32S_addsub_imm" symboldefcount="1">
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<symbol link="sa_wn_wsp"><Wn|WSP></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 32-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="CMP_SUBS_64S_addsub_imm" symboldefcount="1">
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<symbol link="sa_xn_sp"><Xn|SP></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="CMP_SUBS_32S_addsub_imm, CMP_SUBS_64S_addsub_imm" symboldefcount="1">
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<symbol link="sa_imm"><imm></symbol>
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<account encodedin="imm12">
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<intro>
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<para>Is an unsigned immediate, in the range 0 to 4095, encoded in the "imm12" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="CMP_SUBS_32S_addsub_imm, CMP_SUBS_64S_addsub_imm" symboldefcount="1">
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<symbol link="sa_shift"><shift></symbol>
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<definition encodedin="sh">
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<intro>Is the optional left shift to apply to the immediate, defaulting to LSL #0 and </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">sh</entry>
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<entry class="symbol"><shift></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="symbol">LSL #0</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="symbol">LSL #12</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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</explanations>
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</instructionsection>
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