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https://github.com/pound-emu/ballistic.git
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157 lines
8.4 KiB
XML
157 lines
8.4 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="CNEG_CSNEG" title="CNEG -- A64" type="alias">
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<docvars>
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<docvar key="alias_mnemonic" value="CNEG" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="CSNEG" />
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</docvars>
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<heading>CNEG</heading>
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<desc>
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<brief>
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<para>Conditional Negate</para>
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</brief>
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<authored>
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<para>Conditional Negate returns, in the destination register, the negated value of the source register if the condition is TRUE, and otherwise returns the value of the source register.</para>
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</authored>
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</desc>
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<operationalnotes>
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<para>If PSTATE.DIT is 1:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<aliasto refiform="csneg.xml" iformid="CSNEG">CSNEG</aliasto>
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<classes>
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<iclass name="Integer" oneof="1" id="iclass_general" no_encodings="2" isa="A64">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="CSNEG" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/integer/conditional/select" tworows="1">
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<box hibit="31" name="sf" usename="1">
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<c></c>
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</box>
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<box hibit="30" name="op" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="29" name="S" settings="1">
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<c>0</c>
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</box>
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<box hibit="28" width="8" settings="8">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="20" width="5" name="Rm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" width="4" name="cond" usename="1" settings="3" constraint="!= 111x" psbits="xxxx">
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<c colspan="4">!= 111x</c>
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</box>
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<box hibit="11" name="op2[1]" settings="1">
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<c>0</c>
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</box>
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<box hibit="10" name="o2" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="CNEG_CSNEG_32_condsel" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0">
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<docvars>
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<docvar key="alias_mnemonic" value="CNEG" />
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<docvar key="datatype" value="32" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="CSNEG" />
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</docvars>
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<box hibit="31" width="1" name="sf">
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<c>0</c>
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</box>
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<asmtemplate><text>CNEG </text><a link="sa_wd" hover="32-bit general-purpose destination register (field "Rd")"><Wd></a><text>, </text><a link="sa_wn_1" hover="32-bit general-purpose source register (field "Rn" and "Rm")"><Wn></a><text>, </text><a link="sa_cond_1" hover="Standard condition, excluding AL and NV (field "cond")"><cond></a></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="csneg.xml#CSNEG_32_condsel">CSNEG</a><text> </text><a link="sa_wd" hover="32-bit general-purpose destination register (field "Rd")"><Wd></a><text>, </text><a link="sa_wn_1" hover="32-bit general-purpose source register (field "Rn" and "Rm")"><Wn></a><text>, </text><a link="sa_wn_1" hover="32-bit general-purpose source register (field "Rn" and "Rm")"><Wn></a><text>, invert(</text><a link="sa_cond_1" hover="Standard condition, excluding AL and NV (field "cond")"><cond></a><text>)</text></asmtemplate>
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<aliascond>Rn == Rm</aliascond>
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</equivalent_to>
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</encoding>
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<encoding name="CNEG_CSNEG_64_condsel" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
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<docvars>
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<docvar key="alias_mnemonic" value="CNEG" />
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<docvar key="datatype" value="64" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="CSNEG" />
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</docvars>
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<box hibit="31" width="1" name="sf">
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<c>1</c>
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</box>
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<asmtemplate><text>CNEG </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_xn_1" hover="64-bit general-purpose source register (field "Rn" and "Rm")"><Xn></a><text>, </text><a link="sa_cond_1" hover="Standard condition, excluding AL and NV (field "cond")"><cond></a></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="csneg.xml#CSNEG_64_condsel">CSNEG</a><text> </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_xn_1" hover="64-bit general-purpose source register (field "Rn" and "Rm")"><Xn></a><text>, </text><a link="sa_xn_1" hover="64-bit general-purpose source register (field "Rn" and "Rm")"><Xn></a><text>, invert(</text><a link="sa_cond_1" hover="Standard condition, excluding AL and NV (field "cond")"><cond></a><text>)</text></asmtemplate>
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<aliascond>Rn == Rm</aliascond>
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</equivalent_to>
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</encoding>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="CNEG_CSNEG_32_condsel" symboldefcount="1">
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<symbol link="sa_wd"><Wd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="CNEG_CSNEG_32_condsel" symboldefcount="1">
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<symbol link="sa_wn_1"><Wn></symbol>
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<account encodedin="Rm:Rn">
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<intro>
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<para>Is the 32-bit name of the general-purpose source register, encoded in the "Rn" and "Rm" fields.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="CNEG_CSNEG_64_condsel" symboldefcount="1">
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<symbol link="sa_xd"><Xd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="CNEG_CSNEG_64_condsel" symboldefcount="1">
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<symbol link="sa_xn_1"><Xn></symbol>
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<account encodedin="Rm:Rn">
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<intro>
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<para>Is the 64-bit name of the general-purpose source register, encoded in the "Rn" and "Rm" fields.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="CNEG_CSNEG_32_condsel, CNEG_CSNEG_64_condsel" symboldefcount="1">
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<symbol link="sa_cond_1"><cond></symbol>
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<account encodedin="cond">
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<intro>
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<para>Is one of the standard conditions, excluding AL and NV, encoded in the "cond" field with its least significant bit inverted.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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</instructionsection>
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