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243 lines
11 KiB
XML
243 lines
11 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="DUP_advsimd_gen" title="DUP (general) -- A64" type="instruction">
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<docvars>
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="DUP" />
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<docvar key="vector-xfer-type" value="vector-from-general" />
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</docvars>
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<heading>DUP (general)</heading>
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<desc>
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<brief>
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<para>Duplicate general-purpose register to vector</para>
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</brief>
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<authored>
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<para>Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.</para>
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<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
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</authored>
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</desc>
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<operationalnotes>
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<para>If PSTATE.DIT is 1:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="Advanced SIMD" oneof="1" id="iclass_advsimd" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="DUP" />
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<docvar key="vector-xfer-type" value="vector-from-general" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/vector/transfer/integer/dup">
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<box hibit="31" settings="1">
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<c>0</c>
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</box>
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<box hibit="30" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="29" name="op" settings="1">
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<c>0</c>
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</box>
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<box hibit="28" width="8" settings="8">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="20" width="5" name="imm5" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" settings="1">
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<c>0</c>
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</box>
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<box hibit="14" width="4" name="imm4" settings="4">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="10" settings="1">
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<c>1</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="DUP_asimdins_DR_r" oneofinclass="1" oneof="1" label="">
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<docvars>
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="DUP" />
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<docvar key="vector-xfer-type" value="vector-from-general" />
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</docvars>
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<asmtemplate><text>DUP </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "imm5:Q") [2D,2S,4H,4S,8B,8H,16B]"><T></a><text>, </text><a link="sa_r" hover="Width specifier for general-purpose source register (field "imm5") [W,X]"><R></a><a link="sa_n" hover="General-purpose source register number [0-30] or ZR (31) (field "Rn")"><n></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/transfer/integer/dup" mylink="aarch64.instrs.vector.transfer.integer.dup" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer size = <a link="impl-shared.LowestSetBit.1" file="shared_pseudocode.xml" hover="function: integer LowestSetBit(bits(N) x)">LowestSetBit</a>(imm5);
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if size > 3 then UNDEFINED;
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// imm5<4:size+1> is IGNORED
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if size == 3 && Q == '0' then UNDEFINED;
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integer esize = 8 << size;
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integer datasize = if Q == '1' then 128 else 64;
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integer elements = datasize DIV esize;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="DUP_asimdins_DR_r" symboldefcount="1">
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<symbol link="sa_vd"><Vd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="DUP_asimdins_DR_r" symboldefcount="1">
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<symbol link="sa_t"><T></symbol>
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<definition encodedin="imm5:Q">
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<intro>Is an arrangement specifier, </intro>
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<table class="valuetable">
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<tgroup cols="3">
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<thead>
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<row>
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<entry class="bitfield">imm5</entry>
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<entry class="bitfield">Q</entry>
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<entry class="symbol"><T></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">x0000</entry>
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<entry class="bitfield">x</entry>
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<entry class="symbol">RESERVED</entry>
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</row>
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<row>
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<entry class="bitfield">xxxx1</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">8B</entry>
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</row>
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<row>
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<entry class="bitfield">xxxx1</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">16B</entry>
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</row>
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<row>
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<entry class="bitfield">xxx10</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">4H</entry>
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</row>
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<row>
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<entry class="bitfield">xxx10</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">8H</entry>
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</row>
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<row>
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<entry class="bitfield">xx100</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">2S</entry>
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</row>
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<row>
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<entry class="bitfield">xx100</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">4S</entry>
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</row>
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<row>
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<entry class="bitfield">x1000</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">RESERVED</entry>
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</row>
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<row>
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<entry class="bitfield">x1000</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">2D</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="DUP_asimdins_DR_r" symboldefcount="1">
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<symbol link="sa_r"><R></symbol>
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<definition encodedin="imm5">
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<intro>Is the width specifier for the general-purpose source register, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">imm5</entry>
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<entry class="symbol"><R></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">x0000</entry>
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<entry class="symbol">RESERVED</entry>
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</row>
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<row>
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<entry class="bitfield">xxxx1</entry>
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<entry class="symbol">W</entry>
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</row>
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<row>
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<entry class="bitfield">xxx10</entry>
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<entry class="symbol">W</entry>
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</row>
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<row>
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<entry class="bitfield">xx100</entry>
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<entry class="symbol">W</entry>
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</row>
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<row>
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<entry class="bitfield">x1000</entry>
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<entry class="symbol">X</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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<after> Unspecified bits in "imm5" are ignored but should be set to zero by an assembler.</after>
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</definition>
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</explanation>
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<explanation enclist="DUP_asimdins_DR_r" symboldefcount="1">
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<symbol link="sa_n"><n></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the number [0-30] of the general-purpose source register or ZR (31), encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/transfer/integer/dup" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
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bits(esize) element = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, esize];
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bits(datasize) result;
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for e = 0 to elements-1
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;
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<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, datasize] = result;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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