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archived-ballistic/spec/arm64_xml/dup_z_r.xml
Ronald Caesar 26a677f8b4 decoder: Add ARM specification docs
Signed-off-by: Ronald Caesar <github43132@proton.me>
2025-12-12 18:11:36 -04:00

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XML

<?xml version="1.0" encoding="utf-8"?>
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
<instructionsection id="dup_z_r" title="DUP (scalar)" type="instruction">
<docvars>
<docvar key="instr-class" value="sve" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="DUP" />
</docvars>
<heading>DUP (scalar)</heading>
<desc>
<brief>Broadcast general-purpose register to vector elements (unpredicated)</brief>
<description>
<para>Unconditionally broadcast the general-purpose scalar source register into each element of the destination vector. This instruction is unpredicated.</para>
</description>
<status>Green</status>
<predicated>False</predicated>
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
</desc>
<alias_list howmany="1">
<alias_list_intro>This instruction is used by the alias </alias_list_intro>
<aliasref aliaspageid="MOV_dup_z_r" aliasfile="mov_dup_z_r.xml" hover="Move general-purpose register to vector elements (unpredicated)" punct=".">
<text>MOV (scalar, unpredicated)</text>
<aliaspref>Unconditionally</aliaspref>
</aliasref>
<alias_list_outro> The alias is always the preferred disassembly.</alias_list_outro>
</alias_list>
<classes>
<iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
<docvars>
<docvar key="instr-class" value="sve" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="DUP" />
</docvars>
<iclassintro count="1"></iclassintro>
<regdiagram form="32" psname="DUP-Z.R-_">
<box hibit="31" width="8" settings="8">
<c>0</c>
<c>0</c>
<c>0</c>
<c>0</c>
<c>0</c>
<c>1</c>
<c>0</c>
<c>1</c>
</box>
<box hibit="23" width="2" name="size" usename="1">
<c colspan="2"></c>
</box>
<box hibit="21" width="12" settings="12">
<c>1</c>
<c>0</c>
<c>0</c>
<c>0</c>
<c>0</c>
<c>0</c>
<c>0</c>
<c>0</c>
<c>1</c>
<c>1</c>
<c>1</c>
<c>0</c>
</box>
<box hibit="9" width="5" name="Rn" usename="1">
<c colspan="5"></c>
</box>
<box hibit="4" width="5" name="Zd" usename="1">
<c colspan="5"></c>
</box>
</regdiagram>
<encoding name="dup_z_r_" oneofinclass="1" oneof="1" label="">
<docvars>
<docvar key="instr-class" value="sve" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="DUP" />
</docvars>
<asmtemplate><text>DUP </text><a link="sa_zd" hover="Destination scalable vector register (field &quot;Zd&quot;)">&lt;Zd&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;size&quot;) [B,D,H,S]">&lt;T&gt;</a><text>, </text><a link="sa_r" hover="Width specifier (field &quot;size&quot;) [W,X]">&lt;R&gt;</a><a link="sa_n_sp" hover="General-purpose source register number [0-30] or SP (31) (field &quot;Rn&quot;)">&lt;n|SP&gt;</a></asmtemplate>
</encoding>
<ps_section howmany="1">
<ps name="DUP-Z.R-_" mylink="DUP-Z.R-_" enclabels="" sections="1" secttype="noheading">
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() &amp;&amp; !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
constant integer esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);</pstext>
</ps>
</ps_section>
</iclass>
</classes>
<explanations scope="all">
<explanation enclist="dup_z_r_" symboldefcount="1">
<symbol link="sa_zd">&lt;Zd&gt;</symbol>
<account encodedin="Zd">
<intro>
<para>Is the name of the destination scalable vector register, encoded in the "Zd" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="dup_z_r_" symboldefcount="1">
<symbol link="sa_t">&lt;T&gt;</symbol>
<definition encodedin="size">
<intro>Is the size specifier, </intro>
<table class="valuetable">
<tgroup cols="2">
<thead>
<row>
<entry class="bitfield">size</entry>
<entry class="symbol">&lt;T&gt;</entry>
</row>
</thead>
<tbody>
<row>
<entry class="bitfield">00</entry>
<entry class="symbol">B</entry>
</row>
<row>
<entry class="bitfield">01</entry>
<entry class="symbol">H</entry>
</row>
<row>
<entry class="bitfield">10</entry>
<entry class="symbol">S</entry>
</row>
<row>
<entry class="bitfield">11</entry>
<entry class="symbol">D</entry>
</row>
</tbody>
</tgroup>
</table>
</definition>
</explanation>
<explanation enclist="dup_z_r_" symboldefcount="1">
<symbol link="sa_r">&lt;R&gt;</symbol>
<definition encodedin="size">
<intro>Is a width specifier, </intro>
<table class="valuetable">
<tgroup cols="2">
<thead>
<row>
<entry class="bitfield">size</entry>
<entry class="symbol">&lt;R&gt;</entry>
</row>
</thead>
<tbody>
<row>
<entry class="bitfield">01</entry>
<entry class="symbol">W</entry>
</row>
<row>
<entry class="bitfield">x0</entry>
<entry class="symbol">W</entry>
</row>
<row>
<entry class="bitfield">11</entry>
<entry class="symbol">X</entry>
</row>
</tbody>
</tgroup>
</table>
</definition>
</explanation>
<explanation enclist="dup_z_r_" symboldefcount="1">
<symbol link="sa_n_sp">&lt;n|SP&gt;</symbol>
<account encodedin="Rn">
<intro>
<para>Is the number [0-30] of the general-purpose source register or the name SP (31), encoded in the "Rn" field.</para>
</intro>
</account>
</explanation>
</explanations>
<ps_section howmany="1">
<ps name="DUP-Z.R-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
constant integer elements = VL DIV esize;
constant integer PL = VL DIV 8;
bits(64) operand;
if n == 31 then
operand = <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[];
else
operand = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
bits(VL) result;
for e = 0 to elements-1
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = operand&lt;esize-1:0&gt;;
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</pstext>
</ps>
</ps_section>
</instructionsection>