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archived-ballistic/spec/arm64_xml/fcvtlt_z_p_z.xml
Ronald Caesar 26a677f8b4 decoder: Add ARM specification docs
Signed-off-by: Ronald Caesar <github43132@proton.me>
2025-12-12 18:11:36 -04:00

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<?xml version="1.0" encoding="utf-8"?>
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
<instructionsection id="fcvtlt_z_p_z" title="FCVTLT" type="instruction">
<docvars>
<docvar key="instr-class" value="sve2" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="FCVTLT" />
</docvars>
<heading>FCVTLT</heading>
<desc>
<brief>Floating-point up convert long (top, predicated)</brief>
<description>
<para>Convert odd-numbered floating-point elements from the source vector to the next higher precision, and place the results in the active overlapping double-width elements of the destination vector. Inactive elements in the destination vector register remain unmodified.</para>
</description>
<status>Green</status>
<predicated>True</predicated>
</desc>
<alias_list howmany="0"></alias_list>
<classes>
<classesintro count="2">
<txt>It has encodings from 2 classes:</txt>
<a href="#iclass_half_to_single">Half-precision to single-precision</a>
<txt> and </txt>
<a href="#iclass_single_to_double">Single-precision to double-precision</a>
</classesintro>
<iclass name="Half-precision to single-precision" oneof="2" id="iclass_half_to_single" no_encodings="1" isa="A64">
<docvars>
<docvar key="convert-type" value="half-to-single" />
<docvar key="instr-class" value="sve2" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="FCVTLT" />
</docvars>
<iclassintro count="1"></iclassintro>
<regdiagram form="32" psname="FCVTLT-Z.P.Z-H2S">
<box hibit="31" width="8" settings="8">
<c>0</c>
<c>1</c>
<c>1</c>
<c>0</c>
<c>0</c>
<c>1</c>
<c>0</c>
<c>0</c>
</box>
<box hibit="23" name="opc&lt;1&gt;" settings="1">
<c>1</c>
</box>
<box hibit="22" name="opc&lt;0&gt;" settings="1">
<c>0</c>
</box>
<box hibit="21" width="4" settings="4">
<c>0</c>
<c>0</c>
<c>1</c>
<c>0</c>
</box>
<box hibit="17" name="opc2&lt;1&gt;" settings="1">
<c>0</c>
</box>
<box hibit="16" name="opc2&lt;0&gt;" settings="1">
<c>1</c>
</box>
<box hibit="15" width="3" settings="3">
<c>1</c>
<c>0</c>
<c>1</c>
</box>
<box hibit="12" width="3" name="Pg" usename="1">
<c colspan="3"></c>
</box>
<box hibit="9" width="5" name="Zn" usename="1">
<c colspan="5"></c>
</box>
<box hibit="4" width="5" name="Zd" usename="1">
<c colspan="5"></c>
</box>
</regdiagram>
<encoding name="fcvtlt_z_p_z_h2s" oneofinclass="1" oneof="2" label="">
<docvars>
<docvar key="convert-type" value="half-to-single" />
<docvar key="instr-class" value="sve2" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="FCVTLT" />
</docvars>
<asmtemplate><text>FCVTLT </text><a link="sa_zd" hover="Destination scalable vector register (field &quot;Zd&quot;)">&lt;Zd&gt;</a><text>.S, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field &quot;Pg&quot;)">&lt;Pg&gt;</a><text>/M, </text><a link="sa_zn" hover="Source scalable vector register (field &quot;Zn&quot;)">&lt;Zn&gt;</a><text>.H</text></asmtemplate>
</encoding>
<ps_section howmany="1">
<ps name="FCVTLT-Z.P.Z-H2S" mylink="FCVTLT-Z.P.Z-H2S" enclabels="" sections="1" secttype="noheading">
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2()">HaveSVE2</a>() &amp;&amp; !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
constant integer esize = 32;
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);</pstext>
</ps>
</ps_section>
</iclass>
<iclass name="Single-precision to double-precision" oneof="2" id="iclass_single_to_double" no_encodings="1" isa="A64">
<docvars>
<docvar key="convert-type" value="single-to-double" />
<docvar key="instr-class" value="sve2" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="FCVTLT" />
</docvars>
<iclassintro count="1"></iclassintro>
<regdiagram form="32" psname="FCVTLT-Z.P.Z-S2D">
<box hibit="31" width="8" settings="8">
<c>0</c>
<c>1</c>
<c>1</c>
<c>0</c>
<c>0</c>
<c>1</c>
<c>0</c>
<c>0</c>
</box>
<box hibit="23" name="opc&lt;1&gt;" settings="1">
<c>1</c>
</box>
<box hibit="22" name="opc&lt;0&gt;" settings="1">
<c>1</c>
</box>
<box hibit="21" width="4" settings="4">
<c>0</c>
<c>0</c>
<c>1</c>
<c>0</c>
</box>
<box hibit="17" name="opc2&lt;1&gt;" settings="1">
<c>1</c>
</box>
<box hibit="16" name="opc2&lt;0&gt;" settings="1">
<c>1</c>
</box>
<box hibit="15" width="3" settings="3">
<c>1</c>
<c>0</c>
<c>1</c>
</box>
<box hibit="12" width="3" name="Pg" usename="1">
<c colspan="3"></c>
</box>
<box hibit="9" width="5" name="Zn" usename="1">
<c colspan="5"></c>
</box>
<box hibit="4" width="5" name="Zd" usename="1">
<c colspan="5"></c>
</box>
</regdiagram>
<encoding name="fcvtlt_z_p_z_s2d" oneofinclass="1" oneof="2" label="">
<docvars>
<docvar key="convert-type" value="single-to-double" />
<docvar key="instr-class" value="sve2" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="FCVTLT" />
</docvars>
<asmtemplate><text>FCVTLT </text><a link="sa_zd" hover="Destination scalable vector register (field &quot;Zd&quot;)">&lt;Zd&gt;</a><text>.D, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field &quot;Pg&quot;)">&lt;Pg&gt;</a><text>/M, </text><a link="sa_zn" hover="Source scalable vector register (field &quot;Zn&quot;)">&lt;Zn&gt;</a><text>.S</text></asmtemplate>
</encoding>
<ps_section howmany="1">
<ps name="FCVTLT-Z.P.Z-S2D" mylink="FCVTLT-Z.P.Z-S2D" enclabels="" sections="1" secttype="noheading">
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2()">HaveSVE2</a>() &amp;&amp; !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
constant integer esize = 64;
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);</pstext>
</ps>
</ps_section>
</iclass>
</classes>
<explanations scope="all">
<explanation enclist="fcvtlt_z_p_z_h2s, fcvtlt_z_p_z_s2d" symboldefcount="1">
<symbol link="sa_zd">&lt;Zd&gt;</symbol>
<account encodedin="Zd">
<intro>
<para>Is the name of the destination scalable vector register, encoded in the "Zd" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="fcvtlt_z_p_z_h2s, fcvtlt_z_p_z_s2d" symboldefcount="1">
<symbol link="sa_pg">&lt;Pg&gt;</symbol>
<account encodedin="Pg">
<intro>
<para>Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="fcvtlt_z_p_z_h2s, fcvtlt_z_p_z_s2d" symboldefcount="1">
<symbol link="sa_zn">&lt;Zn&gt;</symbol>
<account encodedin="Zn">
<intro>
<para>Is the name of the source scalable vector register, encoded in the "Zn" field.</para>
</intro>
</account>
</explanation>
</explanations>
<ps_section howmany="1">
<ps name="FCVTLT-Z.P.Z-H2S" mylink="execute" enclabels="" sections="1" secttype="Operation">
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
bits(VL) operand = if <a link="impl-aarch64.AnyActiveElement.2" file="shared_pseudocode.xml" hover="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
bits(VL) result = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[d, VL];
for e = 0 to elements-1
if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
bits(esize DIV 2) element = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*e + 1, esize DIV 2];
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-aarch64.FPConvertSVE.3" file="shared_pseudocode.xml" hover="function: bits(M) FPConvertSVE(bits(N) op, FPCRType fpcr_in, integer M)">FPConvertSVE</a>(element, FPCR[], esize);
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</pstext>
</ps>
</ps_section>
</instructionsection>