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https://github.com/pound-emu/ballistic.git
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234 lines
12 KiB
XML
234 lines
12 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="FCVTN_advsimd" title="FCVTN, FCVTN2 -- A64" type="instruction">
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<docvars>
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<docvar key="advsimd-datatype" value="simd-single-and-double" />
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<docvar key="advsimd-type" value="simd" />
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<docvar key="datatype" value="single-and-double" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCVTN" />
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</docvars>
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<heading>FCVTN, FCVTN2</heading>
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<desc>
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<brief>
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<para>Floating-point Convert to lower precision Narrow (vector)</para>
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</brief>
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<authored>
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<para>Floating-point Convert to lower precision Narrow (vector). This instruction reads each vector element in the SIMD&FP source register, converts each result to half the precision of the source element, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The rounding mode is determined by the <xref linkend="AArch64.fpcr">FPCR</xref>.</para>
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<para>The <instruction>FCVTN</instruction> instruction writes the vector to the lower half of the destination register and clears the upper half, while the <instruction>FCVTN2</instruction> instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.</para>
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<para>A floating-point exception can be generated by this instruction. Depending on the settings in <xref linkend="AArch64.fpcr">FPCR</xref>, the exception results in either a flag being set in <xref linkend="AArch64.fpsr">FPSR</xref> or a synchronous exception being generated. For more information, see <xref linkend="BEIJDDAG">Floating-point exception traps</xref>.</para>
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<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.</para>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="Vector single-precision and double-precision" oneof="1" id="iclass_simd_single_and_double" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="advsimd-datatype" value="simd-single-and-double" />
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<docvar key="advsimd-type" value="simd" />
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<docvar key="datatype" value="single-and-double" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCVTN" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/unary/float/narrow">
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<box hibit="31" settings="1">
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<c>0</c>
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</box>
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<box hibit="30" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="29" name="U" settings="1">
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<c>0</c>
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</box>
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<box hibit="28" width="5" settings="5">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" name="size[1]" settings="1">
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<c>0</c>
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</box>
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<box hibit="22" name="sz" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="5" settings="5">
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="16" width="5" name="opcode" settings="5">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="FCVTN_asimdmisc_N" oneofinclass="1" oneof="1" label="">
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<docvars>
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<docvar key="advsimd-datatype" value="simd-single-and-double" />
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<docvar key="advsimd-type" value="simd" />
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<docvar key="datatype" value="single-and-double" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCVTN" />
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</docvars>
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<asmtemplate><text>FCVTN</text><a link="sa_2" hover="Second and upper half specifier (field "Q")">{2}</a><text> </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_tb" hover="Arrangement specifier (field "sz:Q") [2S,4H,4S,8H]"><Tb></a><text>, </text><a link="sa_vn" hover="SIMD&FP source register (field "Rn")"><Vn></a><text>.</text><a link="sa_ta" hover="Arrangement specifier (field "sz") [2D,4S]"><Ta></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/arithmetic/unary/float/narrow" mylink="aarch64.instrs.vector.arithmetic.unary.float.narrow" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer esize = 16 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
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integer datasize = 64;
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integer part = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Q);
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integer elements = datasize DIV esize;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="FCVTN_asimdmisc_N" symboldefcount="1">
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<symbol link="sa_2">2</symbol>
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<definition encodedin="Q">
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<intro>Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">Q</entry>
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<entry class="symbol">2</entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="symbol">[absent]</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="symbol">[present]</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="FCVTN_asimdmisc_N" symboldefcount="1">
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<symbol link="sa_vd"><Vd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="FCVTN_asimdmisc_N" symboldefcount="1">
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<symbol link="sa_tb"><Tb></symbol>
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<definition encodedin="sz:Q">
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<intro>Is an arrangement specifier, </intro>
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<table class="valuetable">
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<tgroup cols="3">
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<thead>
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<row>
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<entry class="bitfield">sz</entry>
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<entry class="bitfield">Q</entry>
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<entry class="symbol"><Tb></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">4H</entry>
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</row>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">8H</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">2S</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">4S</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="FCVTN_asimdmisc_N" symboldefcount="1">
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<symbol link="sa_vn"><Vn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the name of the SIMD&FP source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="FCVTN_asimdmisc_N" symboldefcount="1">
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<symbol link="sa_ta"><Ta></symbol>
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<definition encodedin="sz">
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<intro>Is an arrangement specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">sz</entry>
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<entry class="symbol"><Ta></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="symbol">4S</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="symbol">2D</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/arithmetic/unary/float/narrow" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
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bits(2*datasize) operand = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, 2*datasize];
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bits(datasize) result;
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for e = 0 to elements-1
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.FPConvert.3" file="shared_pseudocode.xml" hover="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr, integer M)">FPConvert</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], FPCR[], esize);
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<a link="impl-aarch64.Vpart.write.3" file="shared_pseudocode.xml" hover="accessor: Vpart[integer n, integer part, integer width] = bits(width) value">Vpart</a>[d, part, datasize] = result;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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