mirror of
https://github.com/pound-emu/ballistic.git
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629 lines
33 KiB
XML
629 lines
33 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="fcvtzu_z_p_z" title="FCVTZU" type="instruction">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCVTZU" />
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</docvars>
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<heading>FCVTZU</heading>
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<desc>
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<brief>Floating-point convert to unsigned integer, rounding toward zero (predicated)</brief>
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<description>
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<para>Convert to the unsigned integer nearer to zero from each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified.</para>
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<para>If the input and result types have a different size the smaller type is held unpacked in the least significant bits of elements of the larger size. When the input is the smaller type the upper bits of each source element are ignored. When the result is the smaller type the results are zero-extended to fill each destination element.</para>
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</description>
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<status>Green</status>
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<predicated>True</predicated>
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<takes_movprfx>True</takes_movprfx>
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<takes_pred_movprfx>True</takes_pred_movprfx>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="7">
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<txt>It has encodings from 7 classes:</txt>
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<a href="#iclass_half_to_16">Half-precision to 16-bit</a>
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<txt>, </txt>
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<a href="#iclass_half_to_32">Half-precision to 32-bit</a>
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<txt>, </txt>
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<a href="#iclass_half_to_64">Half-precision to 64-bit</a>
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<txt>, </txt>
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<a href="#iclass_single_to_32">Single-precision to 32-bit</a>
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<txt>, </txt>
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<a href="#iclass_single_to_64">Single-precision to 64-bit</a>
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<txt>, </txt>
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<a href="#iclass_double_to_32">Double-precision to 32-bit</a>
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<txt> and </txt>
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<a href="#iclass_double_to_64">Double-precision to 64-bit</a>
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</classesintro>
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<iclass name="Half-precision to 16-bit" oneof="7" id="iclass_half_to_16" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="convert-type" value="half-to-16" />
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCVTZU" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="FCVTZU-Z.P.Z-FP162H" tworows="1">
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<box hibit="31" width="8" settings="8">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="23" name="opc<1>" settings="1">
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<c>0</c>
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</box>
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<box hibit="22" name="opc<0>" settings="1">
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<c>1</c>
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</box>
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<box hibit="21" width="3" settings="3">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="18" name="opc2<1>" settings="1">
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<c>0</c>
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</box>
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<box hibit="17" name="opc2<0>" settings="1">
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<c>1</c>
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</box>
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<box hibit="16" name="int_U" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="15" width="3" settings="3">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="12" width="3" name="Pg" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="9" width="5" name="Zn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="fcvtzu_z_p_z_fp162h" oneofinclass="1" oneof="7" label="">
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<docvars>
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<docvar key="convert-type" value="half-to-16" />
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCVTZU" />
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</docvars>
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<asmtemplate><text>FCVTZU </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.H, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>/M, </text><a link="sa_zn" hover="Source scalable vector register (field "Zn")"><Zn></a><text>.H</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="FCVTZU-Z.P.Z-FP162H" mylink="FCVTZU-Z.P.Z-FP162H" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
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constant integer esize = 16;
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integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);
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constant integer s_esize = 16;
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constant integer d_esize = 16;
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boolean unsigned = TRUE;
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<a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF, FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF, FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a>;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Half-precision to 32-bit" oneof="7" id="iclass_half_to_32" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="convert-type" value="half-to-32" />
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCVTZU" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="FCVTZU-Z.P.Z-FP162W" tworows="1">
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<box hibit="31" width="8" settings="8">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="23" name="opc<1>" settings="1">
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<c>0</c>
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</box>
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<box hibit="22" name="opc<0>" settings="1">
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<c>1</c>
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</box>
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<box hibit="21" width="3" settings="3">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="18" name="opc2<1>" settings="1">
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<c>1</c>
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</box>
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<box hibit="17" name="opc2<0>" settings="1">
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<c>0</c>
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</box>
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<box hibit="16" name="int_U" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="15" width="3" settings="3">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="12" width="3" name="Pg" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="9" width="5" name="Zn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="fcvtzu_z_p_z_fp162w" oneofinclass="1" oneof="7" label="">
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<docvars>
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<docvar key="convert-type" value="half-to-32" />
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCVTZU" />
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</docvars>
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<asmtemplate><text>FCVTZU </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.S, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>/M, </text><a link="sa_zn" hover="Source scalable vector register (field "Zn")"><Zn></a><text>.H</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="FCVTZU-Z.P.Z-FP162W" mylink="FCVTZU-Z.P.Z-FP162W" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
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constant integer esize = 32;
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integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);
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constant integer s_esize = 16;
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constant integer d_esize = 32;
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boolean unsigned = TRUE;
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<a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF, FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF, FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a>;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Half-precision to 64-bit" oneof="7" id="iclass_half_to_64" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="convert-type" value="half-to-64" />
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCVTZU" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="FCVTZU-Z.P.Z-FP162X" tworows="1">
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<box hibit="31" width="8" settings="8">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="23" name="opc<1>" settings="1">
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<c>0</c>
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</box>
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<box hibit="22" name="opc<0>" settings="1">
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<c>1</c>
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</box>
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<box hibit="21" width="3" settings="3">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="18" name="opc2<1>" settings="1">
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<c>1</c>
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</box>
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<box hibit="17" name="opc2<0>" settings="1">
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<c>1</c>
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</box>
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<box hibit="16" name="int_U" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="15" width="3" settings="3">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="12" width="3" name="Pg" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="9" width="5" name="Zn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="fcvtzu_z_p_z_fp162x" oneofinclass="1" oneof="7" label="">
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<docvars>
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<docvar key="convert-type" value="half-to-64" />
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCVTZU" />
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</docvars>
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<asmtemplate><text>FCVTZU </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.D, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>/M, </text><a link="sa_zn" hover="Source scalable vector register (field "Zn")"><Zn></a><text>.H</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="FCVTZU-Z.P.Z-FP162X" mylink="FCVTZU-Z.P.Z-FP162X" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
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constant integer esize = 64;
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integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);
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constant integer s_esize = 16;
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constant integer d_esize = 64;
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boolean unsigned = TRUE;
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<a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF, FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF, FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a>;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Single-precision to 32-bit" oneof="7" id="iclass_single_to_32" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="convert-type" value="single-to-32" />
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<docvar key="instr-class" value="sve" />
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|
<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCVTZU" />
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</docvars>
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<iclassintro count="1"></iclassintro>
|
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<regdiagram form="32" psname="FCVTZU-Z.P.Z-S2W" tworows="1">
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|
<box hibit="31" width="8" settings="8">
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<c>0</c>
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|
<c>1</c>
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<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" name="opc<1>" settings="1">
|
|
<c>1</c>
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|
</box>
|
|
<box hibit="22" name="opc<0>" settings="1">
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|
<c>0</c>
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|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="18" name="opc2<1>" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="17" name="opc2<0>" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="16" name="int_U" usename="1" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
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|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
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|
<c colspan="3"></c>
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|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
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|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
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|
</box>
|
|
</regdiagram>
|
|
<encoding name="fcvtzu_z_p_z_s2w" oneofinclass="1" oneof="7" label="">
|
|
<docvars>
|
|
<docvar key="convert-type" value="single-to-32" />
|
|
<docvar key="instr-class" value="sve" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FCVTZU" />
|
|
</docvars>
|
|
<asmtemplate><text>FCVTZU </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.S, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>/M, </text><a link="sa_zn" hover="Source scalable vector register (field "Zn")"><Zn></a><text>.S</text></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="FCVTZU-Z.P.Z-S2W" mylink="FCVTZU-Z.P.Z-S2W" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
|
constant integer esize = 32;
|
|
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
|
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
|
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);
|
|
constant integer s_esize = 32;
|
|
constant integer d_esize = 32;
|
|
boolean unsigned = TRUE;
|
|
<a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF, FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF, FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a>;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="Single-precision to 64-bit" oneof="7" id="iclass_single_to_64" no_encodings="1" isa="A64">
|
|
<docvars>
|
|
<docvar key="convert-type" value="single-to-64" />
|
|
<docvar key="instr-class" value="sve" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FCVTZU" />
|
|
</docvars>
|
|
<iclassintro count="1"></iclassintro>
|
|
<regdiagram form="32" psname="FCVTZU-Z.P.Z-S2X" tworows="1">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" name="opc<1>" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="opc<0>" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="18" name="opc2<1>" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="17" name="opc2<0>" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="16" name="int_U" usename="1" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="fcvtzu_z_p_z_s2x" oneofinclass="1" oneof="7" label="">
|
|
<docvars>
|
|
<docvar key="convert-type" value="single-to-64" />
|
|
<docvar key="instr-class" value="sve" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FCVTZU" />
|
|
</docvars>
|
|
<asmtemplate><text>FCVTZU </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.D, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>/M, </text><a link="sa_zn" hover="Source scalable vector register (field "Zn")"><Zn></a><text>.S</text></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="FCVTZU-Z.P.Z-S2X" mylink="FCVTZU-Z.P.Z-S2X" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
|
constant integer esize = 64;
|
|
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
|
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
|
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);
|
|
constant integer s_esize = 32;
|
|
constant integer d_esize = 64;
|
|
boolean unsigned = TRUE;
|
|
<a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF, FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF, FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a>;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="Double-precision to 32-bit" oneof="7" id="iclass_double_to_32" no_encodings="1" isa="A64">
|
|
<docvars>
|
|
<docvar key="convert-type" value="double-to-32" />
|
|
<docvar key="instr-class" value="sve" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FCVTZU" />
|
|
</docvars>
|
|
<iclassintro count="1"></iclassintro>
|
|
<regdiagram form="32" psname="FCVTZU-Z.P.Z-D2W" tworows="1">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" name="opc<1>" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="opc<0>" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="18" name="opc2<1>" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="17" name="opc2<0>" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="16" name="int_U" usename="1" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="fcvtzu_z_p_z_d2w" oneofinclass="1" oneof="7" label="">
|
|
<docvars>
|
|
<docvar key="convert-type" value="double-to-32" />
|
|
<docvar key="instr-class" value="sve" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FCVTZU" />
|
|
</docvars>
|
|
<asmtemplate><text>FCVTZU </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.S, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>/M, </text><a link="sa_zn" hover="Source scalable vector register (field "Zn")"><Zn></a><text>.D</text></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="FCVTZU-Z.P.Z-D2W" mylink="FCVTZU-Z.P.Z-D2W" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
|
constant integer esize = 64;
|
|
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
|
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
|
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);
|
|
constant integer s_esize = 64;
|
|
constant integer d_esize = 32;
|
|
boolean unsigned = TRUE;
|
|
<a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF, FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF, FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a>;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="Double-precision to 64-bit" oneof="7" id="iclass_double_to_64" no_encodings="1" isa="A64">
|
|
<docvars>
|
|
<docvar key="convert-type" value="double-to-64" />
|
|
<docvar key="instr-class" value="sve" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FCVTZU" />
|
|
</docvars>
|
|
<iclassintro count="1"></iclassintro>
|
|
<regdiagram form="32" psname="FCVTZU-Z.P.Z-D2X" tworows="1">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" name="opc<1>" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="opc<0>" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="18" name="opc2<1>" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="17" name="opc2<0>" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="16" name="int_U" usename="1" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="fcvtzu_z_p_z_d2x" oneofinclass="1" oneof="7" label="">
|
|
<docvars>
|
|
<docvar key="convert-type" value="double-to-64" />
|
|
<docvar key="instr-class" value="sve" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FCVTZU" />
|
|
</docvars>
|
|
<asmtemplate><text>FCVTZU </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.D, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>/M, </text><a link="sa_zn" hover="Source scalable vector register (field "Zn")"><Zn></a><text>.D</text></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="FCVTZU-Z.P.Z-D2X" mylink="FCVTZU-Z.P.Z-D2X" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
|
constant integer esize = 64;
|
|
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
|
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
|
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);
|
|
constant integer s_esize = 64;
|
|
constant integer d_esize = 64;
|
|
boolean unsigned = TRUE;
|
|
<a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF, FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF, FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a>;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="fcvtzu_z_p_z_d2w, fcvtzu_z_p_z_d2x, fcvtzu_z_p_z_fp162h, fcvtzu_z_p_z_fp162w, fcvtzu_z_p_z_fp162x, fcvtzu_z_p_z_s2w, fcvtzu_z_p_z_s2x" symboldefcount="1">
|
|
<symbol link="sa_zd"><Zd></symbol>
|
|
<account encodedin="Zd">
|
|
<intro>
|
|
<para>Is the name of the destination scalable vector register, encoded in the "Zd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="fcvtzu_z_p_z_d2w, fcvtzu_z_p_z_d2x, fcvtzu_z_p_z_fp162h, fcvtzu_z_p_z_fp162w, fcvtzu_z_p_z_fp162x, fcvtzu_z_p_z_s2w, fcvtzu_z_p_z_s2x" symboldefcount="1">
|
|
<symbol link="sa_pg"><Pg></symbol>
|
|
<account encodedin="Pg">
|
|
<intro>
|
|
<para>Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="fcvtzu_z_p_z_d2w, fcvtzu_z_p_z_d2x, fcvtzu_z_p_z_fp162h, fcvtzu_z_p_z_fp162w, fcvtzu_z_p_z_fp162x, fcvtzu_z_p_z_s2w, fcvtzu_z_p_z_s2x" symboldefcount="1">
|
|
<symbol link="sa_zn"><Zn></symbol>
|
|
<account encodedin="Zn">
|
|
<intro>
|
|
<para>Is the name of the source scalable vector register, encoded in the "Zn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="FCVTZU-Z.P.Z-FP162H" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
|
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
|
constant integer PL = VL DIV 8;
|
|
constant integer elements = VL DIV esize;
|
|
bits(PL) mask = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
|
bits(VL) operand = if <a link="impl-aarch64.AnyActiveElement.2" file="shared_pseudocode.xml" hover="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
|
bits(VL) result = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[d, VL];
|
|
|
|
for e = 0 to elements-1
|
|
if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
|
bits(esize) element = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
|
|
bits(d_esize) res = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(element<s_esize-1:0>, 0, unsigned, FPCR[], rounding, d_esize);
|
|
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.Extend.3" file="shared_pseudocode.xml" hover="function: bits(N) Extend(bits(M) x, integer N, boolean unsigned)">Extend</a>(res, esize, unsigned);
|
|
|
|
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</pstext>
|
|
</ps>
|
|
</ps_section>
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|
</instructionsection>
|