mirror of
https://github.com/pound-emu/ballistic.git
synced 2026-01-31 01:15:21 +01:00
461 lines
25 KiB
XML
461 lines
25 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
|
|
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
|
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
|
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
|
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
|
|
|
<instructionsection id="fmla_za_zzv" title="FMLA (multiple and single vector)" type="instruction">
|
|
<docvars>
|
|
<docvar key="instr-class" value="mortlach2" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FMLA" />
|
|
</docvars>
|
|
<heading>FMLA (multiple and single vector)</heading>
|
|
<desc>
|
|
<brief>Multi-vector floating-point fused multiply-add by vector</brief>
|
|
<description>
|
|
<para>The instruction operates on two or four ZA single-vector groups.</para>
|
|
<para>Multiply the corresponding floating-point elements of the two or four first source vector with corresponding elements of the second source vector and destructively add without intermediate rounding to the corresponding elements of the two or four ZA single-vector groups. The vector numbers forming the single-vector group within each half or each quarter of the ZA array are selected by the sum of the vector select register and immediate offset, modulo half or quarter the number of ZA array vectors.</para>
|
|
<para>The <arm-defined-word>vector group</arm-defined-word> symbol, <syntax>VGx2</syntax> or <syntax>VGx4</syntax>, indicates that the ZA operand consists of two or four ZA single-vector groups respectively. The <arm-defined-word>vector group</arm-defined-word> symbol is preferred for disassembly, but optional in assembler source code.</para>
|
|
<para>This instruction follows SME ZA-targeting floating-point behaviors.</para>
|
|
<para>This instruction is unpredicated.</para>
|
|
<para>ID_AA64SMFR0_EL1.F64F64 indicates whether the double-precision variant is implemented, and ID_AA64SMFR0_EL1.F16F16 indicates whether the half-precision variant is implemented.</para>
|
|
</description>
|
|
<status>Green</status>
|
|
<predicated>False</predicated>
|
|
<sm_policy>SM_1_only</sm_policy>
|
|
</desc>
|
|
<alias_list howmany="0"></alias_list>
|
|
<classes>
|
|
<classesintro count="4">
|
|
<txt>It has encodings from 4 classes:</txt>
|
|
<a href="#iclass_sme_vgx2_single">Two ZA single-vectors</a>
|
|
<txt>, </txt>
|
|
<a href="#iclass_sme_vgx2hp_single">Two ZA single-vectors of half precision elements</a>
|
|
<txt>, </txt>
|
|
<a href="#iclass_sme_vgx4_single">Four ZA single-vectors</a>
|
|
<txt> and </txt>
|
|
<a href="#iclass_sme_vgx4hp_single">Four ZA single-vectors of half precision elements</a>
|
|
</classesintro>
|
|
<iclass name="Two ZA single-vectors" oneof="4" id="iclass_sme_vgx2_single" no_encodings="1" isa="A64">
|
|
<docvars>
|
|
<docvar key="instr-class" value="mortlach2" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FMLA" />
|
|
<docvar key="sme-multireg" value="sme-vgx2-single" />
|
|
</docvars>
|
|
<iclassintro count="1"></iclassintro>
|
|
<arch_variants>
|
|
<arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
|
|
</arch_variants>
|
|
<regdiagram form="32" psname="FMLA-ZA.ZZV-2x1" tworows="1">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="fmla_za_zzv_2x1" oneofinclass="1" oneof="4" label="">
|
|
<docvars>
|
|
<docvar key="instr-class" value="mortlach2" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FMLA" />
|
|
<docvar key="sme-multireg" value="sme-vgx2-single" />
|
|
</docvars>
|
|
<asmtemplate><text>FMLA ZA.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field "Rv")"><Wv></a><text>, </text><a link="sa_offs" hover="Vector select offset [0-7] (field "off3")"><offs></a><a>{, VGx2}</a><text>], </text><text>{</text><text> </text><a link="sa_zn1" hover="First scalable vector register of a multi-vector sequence, encoded as "Zn" (field Zn)"><Zn1></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>-</text><a link="sa_zn2" hover="Second scalable vector register of a multi-vector sequence (field Zn)"><Zn2></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text> </text><text>}</text><text>, </text><a link="sa_zm" hover="Second source scalable vector register Z0-Z15 (field "Zm")"><Zm></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="FMLA-ZA.ZZV-2x1" mylink="FMLA-ZA.ZZV-2x1" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
|
|
if sz == '1' && !<a link="impl-aarch64.HaveSMEF64F64.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEF64F64()">HaveSMEF64F64</a>() then UNDEFINED;
|
|
integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
|
|
constant integer esize = 32 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
|
|
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
|
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
|
|
integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(off3);
|
|
boolean sub_op = FALSE;
|
|
constant integer nreg = 2;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="Two ZA single-vectors of half precision elements" oneof="4" id="iclass_sme_vgx2hp_single" no_encodings="1" isa="A64">
|
|
<docvars>
|
|
<docvar key="instr-class" value="mortlach2" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FMLA" />
|
|
<docvar key="sme-multireg" value="sme-vgx2hp-single" />
|
|
</docvars>
|
|
<iclassintro count="1"></iclassintro>
|
|
<arch_variants>
|
|
<arch_variant name="FEAT_SME_F16F16" feature="FEAT_SME_F16F16" />
|
|
</arch_variants>
|
|
<regdiagram form="32" psname="FMLA-ZA.ZZV-2x1_16" tworows="1">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="fmla_za_zzv_2x1_16" oneofinclass="1" oneof="4" label="">
|
|
<docvars>
|
|
<docvar key="instr-class" value="mortlach2" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FMLA" />
|
|
<docvar key="sme-multireg" value="sme-vgx2hp-single" />
|
|
</docvars>
|
|
<asmtemplate><text>FMLA ZA.H[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field "Rv")"><Wv></a><text>, </text><a link="sa_offs" hover="Vector select offset [0-7] (field "off3")"><offs></a><a>{, VGx2}</a><text>], </text><text>{</text><text> </text><a link="sa_zn1" hover="First scalable vector register of a multi-vector sequence, encoded as "Zn" (field Zn)"><Zn1></a><text>.H-</text><a link="sa_zn2" hover="Second scalable vector register of a multi-vector sequence (field Zn)"><Zn2></a><text>.H </text><text>}</text><text>, </text><a link="sa_zm" hover="Second source scalable vector register Z0-Z15 (field "Zm")"><Zm></a><text>.H</text></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="FMLA-ZA.ZZV-2x1_16" mylink="FMLA-ZA.ZZV-2x1_16" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSMEF16F16.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEF16F16()">HaveSMEF16F16</a>() then UNDEFINED;
|
|
integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
|
|
constant integer esize = 16;
|
|
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
|
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
|
|
integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(off3);
|
|
boolean sub_op = FALSE;
|
|
constant integer nreg = 2;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="Four ZA single-vectors" oneof="4" id="iclass_sme_vgx4_single" no_encodings="1" isa="A64">
|
|
<docvars>
|
|
<docvar key="instr-class" value="mortlach2" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FMLA" />
|
|
<docvar key="sme-multireg" value="sme-vgx4-single" />
|
|
</docvars>
|
|
<iclassintro count="1"></iclassintro>
|
|
<arch_variants>
|
|
<arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
|
|
</arch_variants>
|
|
<regdiagram form="32" psname="FMLA-ZA.ZZV-4x1" tworows="1">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="fmla_za_zzv_4x1" oneofinclass="1" oneof="4" label="">
|
|
<docvars>
|
|
<docvar key="instr-class" value="mortlach2" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FMLA" />
|
|
<docvar key="sme-multireg" value="sme-vgx4-single" />
|
|
</docvars>
|
|
<asmtemplate><text>FMLA ZA.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field "Rv")"><Wv></a><text>, </text><a link="sa_offs" hover="Vector select offset [0-7] (field "off3")"><offs></a><a>{, VGx4}</a><text>], </text><text>{</text><text> </text><a link="sa_zn1" hover="First scalable vector register of a multi-vector sequence, encoded as "Zn" (field Zn)"><Zn1></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>-</text><a link="sa_zn4" hover="Fourth scalable vector register of a multi-vector sequence (field Zn)"><Zn4></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text> </text><text>}</text><text>, </text><a link="sa_zm" hover="Second source scalable vector register Z0-Z15 (field "Zm")"><Zm></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="FMLA-ZA.ZZV-4x1" mylink="FMLA-ZA.ZZV-4x1" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
|
|
if sz == '1' && !<a link="impl-aarch64.HaveSMEF64F64.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEF64F64()">HaveSMEF64F64</a>() then UNDEFINED;
|
|
integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
|
|
constant integer esize = 32 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
|
|
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
|
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
|
|
integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(off3);
|
|
boolean sub_op = FALSE;
|
|
constant integer nreg = 4;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="Four ZA single-vectors of half precision elements" oneof="4" id="iclass_sme_vgx4hp_single" no_encodings="1" isa="A64">
|
|
<docvars>
|
|
<docvar key="instr-class" value="mortlach2" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FMLA" />
|
|
<docvar key="sme-multireg" value="sme-vgx4hp-single" />
|
|
</docvars>
|
|
<iclassintro count="1"></iclassintro>
|
|
<arch_variants>
|
|
<arch_variant name="FEAT_SME_F16F16" feature="FEAT_SME_F16F16" />
|
|
</arch_variants>
|
|
<regdiagram form="32" psname="FMLA-ZA.ZZV-4x1_16" tworows="1">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="fmla_za_zzv_4x1_16" oneofinclass="1" oneof="4" label="">
|
|
<docvars>
|
|
<docvar key="instr-class" value="mortlach2" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FMLA" />
|
|
<docvar key="sme-multireg" value="sme-vgx4hp-single" />
|
|
</docvars>
|
|
<asmtemplate><text>FMLA ZA.H[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field "Rv")"><Wv></a><text>, </text><a link="sa_offs" hover="Vector select offset [0-7] (field "off3")"><offs></a><a>{, VGx4}</a><text>], </text><text>{</text><text> </text><a link="sa_zn1" hover="First scalable vector register of a multi-vector sequence, encoded as "Zn" (field Zn)"><Zn1></a><text>.H-</text><a link="sa_zn4" hover="Fourth scalable vector register of a multi-vector sequence (field Zn)"><Zn4></a><text>.H </text><text>}</text><text>, </text><a link="sa_zm" hover="Second source scalable vector register Z0-Z15 (field "Zm")"><Zm></a><text>.H</text></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="FMLA-ZA.ZZV-4x1_16" mylink="FMLA-ZA.ZZV-4x1_16" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSMEF16F16.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEF16F16()">HaveSMEF16F16</a>() then UNDEFINED;
|
|
integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
|
|
constant integer esize = 16;
|
|
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
|
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
|
|
integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(off3);
|
|
boolean sub_op = FALSE;
|
|
constant integer nreg = 4;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="fmla_za_zzv_2x1, fmla_za_zzv_4x1" symboldefcount="1">
|
|
<symbol link="sa_t"><T></symbol>
|
|
<definition encodedin="sz">
|
|
<intro>Is the size specifier, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">sz</entry>
|
|
<entry class="symbol"><T></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">S</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">D</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="fmla_za_zzv_2x1, fmla_za_zzv_2x1_16, fmla_za_zzv_4x1, fmla_za_zzv_4x1_16" symboldefcount="1">
|
|
<symbol link="sa_wv"><Wv></symbol>
|
|
<account encodedin="Rv">
|
|
<intro>
|
|
<para>Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="fmla_za_zzv_2x1, fmla_za_zzv_2x1_16, fmla_za_zzv_4x1, fmla_za_zzv_4x1_16" symboldefcount="1">
|
|
<symbol link="sa_offs"><offs></symbol>
|
|
<account encodedin="off3">
|
|
<intro>
|
|
<para>Is the vector select offset, in the range 0 to 7, encoded in the "off3" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="fmla_za_zzv_2x1, fmla_za_zzv_2x1_16, fmla_za_zzv_4x1, fmla_za_zzv_4x1_16" symboldefcount="1">
|
|
<symbol link="sa_zn1"><Zn1></symbol>
|
|
<account encodedin="Zn">
|
|
<intro>
|
|
<para>Is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zn".</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="fmla_za_zzv_4x1, fmla_za_zzv_4x1_16" symboldefcount="1">
|
|
<symbol link="sa_zn4"><Zn4></symbol>
|
|
<account encodedin="Zn">
|
|
<intro>
|
|
<para>Is the name of the fourth scalable vector register of a multi-vector sequence, encoded as "Zn" plus 3 modulo 32.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="fmla_za_zzv_2x1, fmla_za_zzv_2x1_16" symboldefcount="1">
|
|
<symbol link="sa_zn2"><Zn2></symbol>
|
|
<account encodedin="Zn">
|
|
<intro>
|
|
<para>Is the name of the second scalable vector register of a multi-vector sequence, encoded as "Zn" plus 1 modulo 32.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="fmla_za_zzv_2x1, fmla_za_zzv_2x1_16, fmla_za_zzv_4x1, fmla_za_zzv_4x1_16" symboldefcount="1">
|
|
<symbol link="sa_zm"><Zm></symbol>
|
|
<account encodedin="Zm">
|
|
<intro>
|
|
<para>Is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="FMLA-ZA.ZZV-2x1" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckStreamingSVEAndZAEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEAndZAEnabled()">CheckStreamingSVEAndZAEnabled</a>();
|
|
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
|
constant integer elements = VL DIV esize;
|
|
integer vectors = VL DIV 8;
|
|
integer vstride = vectors DIV nreg;
|
|
bits(32) vbase = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[v, 32];
|
|
integer vec = (<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(vbase) + offset) MOD vstride;
|
|
bits(VL) result;
|
|
|
|
for r = 0 to nreg-1
|
|
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[(n+r) MOD 32, VL];
|
|
bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
|
bits(VL) operand3 = <a link="impl-aarch64.ZAvector.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) ZAvector[integer index, integer width]">ZAvector</a>[vec, VL];
|
|
for e = 0 to elements-1
|
|
bits(esize) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
|
bits(esize) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
|
|
bits(esize) element3 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize];
|
|
if sub_op then element1 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
|
|
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.FPMulAdd_ZA.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd_ZA(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr_in)">FPMulAdd_ZA</a>(element3, element1, element2, FPCR[]);
|
|
<a link="impl-aarch64.ZAvector.write.2" file="shared_pseudocode.xml" hover="accessor: ZAvector[integer index, integer width] = bits(width) value">ZAvector</a>[vec, VL] = result;
|
|
vec = vec + vstride;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|