mirror of
https://github.com/pound-emu/ballistic.git
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223 lines
12 KiB
XML
223 lines
12 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="fmmla_z_zzz" title="FMMLA" type="instruction">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FMMLA" />
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</docvars>
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<heading>FMMLA</heading>
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<desc>
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<brief>Floating-point matrix multiply-accumulate</brief>
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<description>
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<para>The floating-point matrix multiply-accumulate instruction supports single-precision and double-precision data types in a 2×2 matrix contained in segments of 128 or 256 bits, respectively. It multiplies the 2×2 matrix in each segment of the first source vector by the 2×2 matrix in the corresponding segment of the second source vector. The resulting 2×2 matrix product is then destructively added to the matrix accumulator held in the corresponding segment of the addend and destination vector. This is equivalent to performing a 2-way dot product per destination element. This instruction is unpredicated. The single-precision variant is vector length agnostic. The double-precision variant requires that the current vector length is at least 256 bits, and if the current vector length is not an integer multiple of 256 bits then the trailing bits are set to zero.</para>
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<para>ID_AA64ZFR0_EL1.F32MM indicates whether the single-precision variant is implemented.</para>
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<para>ID_AA64ZFR0_EL1.F64MM indicates whether the double-precision variant is implemented.</para>
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<para>This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.</para>
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</description>
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<status>Green</status>
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<predicated>False</predicated>
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<takes_movprfx>True</takes_movprfx>
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<sm_policy>SM_0_only</sm_policy>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from 2 classes:</txt>
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<a href="#iclass_32_elem">32-bit element</a>
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<txt> and </txt>
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<a href="#iclass_64_elem">64-bit element</a>
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</classesintro>
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<iclass name="32-bit element" oneof="2" id="iclass_32_elem" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FMMLA" />
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<docvar key="sve-elem-type" value="32-elem" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.6" feature="FEAT_F32MM" />
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</arch_variants>
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<regdiagram form="32" psname="FMMLA-Z.ZZZ-S">
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<box hibit="31" width="8" settings="8">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="23" name="opc<1>" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" name="opc<0>" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" width="5" name="Zm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" width="6" settings="6">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="9" width="5" name="Zn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zda" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="fmmla_z_zzz_s" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FMMLA" />
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<docvar key="sve-elem-type" value="32-elem" />
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</docvars>
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<asmtemplate><text>FMMLA </text><a link="sa_zda" hover="Third source and destination scalable vector register (field "Zda")"><Zda></a><text>.S, </text><a link="sa_zn" hover="First source scalable vector register (field "Zn")"><Zn></a><text>.S, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.S</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="FMMLA-Z.ZZZ-S" mylink="FMMLA-Z.ZZZ-S" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() || !<a link="impl-aarch64.HaveSVEFP32MatMulExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVEFP32MatMulExt()">HaveSVEFP32MatMulExt</a>() then UNDEFINED;
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constant integer esize = 32;
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
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integer da = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zda);</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="64-bit element" oneof="2" id="iclass_64_elem" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FMMLA" />
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<docvar key="sve-elem-type" value="64-elem" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.6" feature="FEAT_F64MM" />
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</arch_variants>
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<regdiagram form="32" psname="FMMLA-Z.ZZZ-D">
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<box hibit="31" width="8" settings="8">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="23" name="opc<1>" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" name="opc<0>" settings="1">
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<c>1</c>
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</box>
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<box hibit="21" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" width="5" name="Zm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" width="6" settings="6">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="9" width="5" name="Zn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zda" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="fmmla_z_zzz_d" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FMMLA" />
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<docvar key="sve-elem-type" value="64-elem" />
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</docvars>
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<asmtemplate><text>FMMLA </text><a link="sa_zda" hover="Third source and destination scalable vector register (field "Zda")"><Zda></a><text>.D, </text><a link="sa_zn" hover="First source scalable vector register (field "Zn")"><Zn></a><text>.D, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.D</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="FMMLA-Z.ZZZ-D" mylink="FMMLA-Z.ZZZ-D" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() || !<a link="impl-aarch64.HaveSVEFP64MatMulExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVEFP64MatMulExt()">HaveSVEFP64MatMulExt</a>() then UNDEFINED;
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constant integer esize = 64;
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
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integer da = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zda);</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="fmmla_z_zzz_d, fmmla_z_zzz_s" symboldefcount="1">
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<symbol link="sa_zda"><Zda></symbol>
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<account encodedin="Zda">
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<intro>
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<para>Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="fmmla_z_zzz_d, fmmla_z_zzz_s" symboldefcount="1">
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<symbol link="sa_zn"><Zn></symbol>
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<account encodedin="Zn">
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<intro>
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<para>Is the name of the first source scalable vector register, encoded in the "Zn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="fmmla_z_zzz_d, fmmla_z_zzz_s" symboldefcount="1">
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<symbol link="sa_zm"><Zm></symbol>
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<account encodedin="Zm">
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<intro>
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<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="FMMLA-Z.ZZZ-S" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckNonStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
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constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
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constant integer PL = VL DIV 8;
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if VL < esize * 4 then UNDEFINED;
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constant integer segments = VL DIV (4 * esize);
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bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
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bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
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bits(VL) operand3 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[da, VL];
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bits(VL) result = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
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bits(4*esize) op1, op2;
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bits(4*esize) res, addend;
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for s = 0 to segments-1
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op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, s, 4*esize];
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op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, s, 4*esize];
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addend = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, s, 4*esize];
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res = <a link="impl-shared.FPMatMulAdd.5" file="shared_pseudocode.xml" hover="function: bits(N) FPMatMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, integer esize, FPCRType fpcr)">FPMatMulAdd</a>(addend, op1, op2, esize, FPCR[]);
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, s, 4*esize] = res;
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<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[da, VL] = result;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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