mirror of
https://github.com/pound-emu/ballistic.git
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665 lines
32 KiB
XML
665 lines
32 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="FMULX_advsimd_elt" title="FMULX (by element) -- A64" type="instruction">
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<docvars>
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FMULX" />
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</docvars>
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<heading>FMULX (by element)</heading>
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<desc>
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<brief>
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<para>Floating-point Multiply extended (by element)</para>
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</brief>
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<authored>
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<para>Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.</para>
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<para>If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.</para>
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<para>This instruction can generate a floating-point exception. Depending on the settings in <xref linkend="AArch64.fpcr">FPCR</xref>, the exception results in either a flag being set in <xref linkend="AArch64.fpsr">FPSR</xref> or a synchronous exception being generated. For more information, see <xref linkend="BEIJDDAG">Floating-point exception traps</xref>.</para>
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<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="4">
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<txt>It has encodings from 4 classes:</txt>
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<a href="#iclass_2reg_scalar_half">Scalar, half-precision</a>
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<txt>, </txt>
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<a href="#iclass_2reg_scalar_single_and_double">Scalar, single-precision and double-precision</a>
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<txt>, </txt>
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<a href="#iclass_2reg_element_half">Vector, half-precision</a>
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<txt> and </txt>
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<a href="#iclass_2reg_element_single_and_double">Vector, single-precision and double-precision</a>
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</classesintro>
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<iclass name="Scalar, half-precision" oneof="4" id="iclass_2reg_scalar_half" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="advsimd-datatype" value="sisd-half" />
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<docvar key="advsimd-reguse" value="2reg-scalar" />
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<docvar key="advsimd-type" value="sisd" />
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<docvar key="datatype" value="half" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FMULX" />
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<docvar key="reguse-datatype" value="2reg-scalar-half" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
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</arch_variants>
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<regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/binary/element/mul/fp16/sisd" tworows="1">
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<box hibit="31" width="2" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="29" name="U" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="28" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="23" width="2" name="size" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="21" name="L" usename="1">
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<c></c>
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</box>
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<box hibit="20" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="19" width="4" name="Rm" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="opcode" settings="4">
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="11" name="H" usename="1">
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<c></c>
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</box>
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<box hibit="10" settings="1">
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="FMULX_asisdelem_RH_H" oneofinclass="1" oneof="4" label="">
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<docvars>
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<docvar key="advsimd-datatype" value="sisd-half" />
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<docvar key="advsimd-reguse" value="2reg-scalar" />
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<docvar key="advsimd-type" value="sisd" />
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<docvar key="datatype" value="half" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FMULX" />
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<docvar key="reguse-datatype" value="2reg-scalar-half" />
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</docvars>
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<asmtemplate><text>FMULX </text><a link="sa_hd" hover="16-bit SIMD&FP destination register (field "Rd")"><Hd></a><text>, </text><a link="sa_hn" hover="First 16-bit SIMD&FP source register (field "Rn")"><Hn></a><text>, </text><a link="sa_vm" hover="Second SIMD&FP source register [V0-V15] (field "Rm")"><Vm></a><text>.H[</text><a link="sa_index" hover="Element index [0-7] (field "H:L:M")"><index></a><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/arithmetic/binary/element/mul/fp16/sisd" mylink="aarch64.instrs.vector.arithmetic.binary.element.mul.fp16.sisd" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;
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integer idxdsize = if H == '1' then 128 else 64;
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(H:L:M);
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integer esize = 16;
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integer datasize = esize;
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integer elements = 1;
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boolean mulx_op = (U == '1');</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Scalar, single-precision and double-precision" oneof="4" id="iclass_2reg_scalar_single_and_double" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="advsimd-datatype" value="sisd-single-and-double" />
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<docvar key="advsimd-reguse" value="2reg-scalar" />
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<docvar key="advsimd-type" value="sisd" />
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<docvar key="datatype" value="single-and-double" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FMULX" />
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<docvar key="reguse-datatype" value="2reg-scalar-single-and-double" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/binary/element/mul/fp/sisd" tworows="1">
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<box hibit="31" width="2" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="29" name="U" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="28" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="23" name="size[1]" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" name="sz" usename="1">
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<c></c>
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</box>
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<box hibit="21" name="L" usename="1">
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<c></c>
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</box>
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<box hibit="20" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="19" width="4" name="Rm" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="opcode" settings="4">
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="11" name="H" usename="1">
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<c></c>
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</box>
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<box hibit="10" settings="1">
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="FMULX_asisdelem_R_SD" oneofinclass="1" oneof="4" label="">
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<docvars>
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<docvar key="advsimd-datatype" value="sisd-single-and-double" />
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<docvar key="advsimd-reguse" value="2reg-scalar" />
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<docvar key="advsimd-type" value="sisd" />
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<docvar key="datatype" value="single-and-double" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FMULX" />
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<docvar key="reguse-datatype" value="2reg-scalar-single-and-double" />
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</docvars>
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<asmtemplate><text>FMULX </text><a link="sa_v" hover="Width specifier (field "sz") [D,S]"><V></a><a link="sa_d" hover="SIMD&FP destination register number (field "Rd")"><d></a><text>, </text><a link="sa_v" hover="Width specifier (field "sz") [D,S]"><V></a><a link="sa_n" hover="First SIMD&FP source register number (field "Rn")"><n></a><text>, </text><a link="sa_vm_1" hover="Second SIMD&FP source register (field "M:Rm")"><Vm></a><text>.</text><a link="sa_ts" hover="Element size specifier (field "sz") [D,S]"><Ts></a><text>[</text><a link="sa_index_1" hover="Element index (field "sz:L:H") [H,H:L]"><index></a><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/arithmetic/binary/element/mul/fp/sisd" mylink="aarch64.instrs.vector.arithmetic.binary.element.mul.fp.sisd" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer idxdsize = if H == '1' then 128 else 64;
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integer index;
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bit Rmhi = M;
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case sz:L of
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when '0x' index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(H:L);
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when '10' index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(H);
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when '11' UNDEFINED;
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rmhi:Rm);
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integer esize = 32 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
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integer datasize = esize;
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integer elements = 1;
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boolean mulx_op = (U == '1');</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Vector, half-precision" oneof="4" id="iclass_2reg_element_half" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="advsimd-reguse" value="2reg-element" />
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<docvar key="datatype" value="half" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FMULX" />
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<docvar key="reguse-datatype" value="2reg-element-half" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
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</arch_variants>
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<regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/binary/element/mul/fp16/simd" tworows="1">
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<box hibit="31" settings="1">
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<c>0</c>
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</box>
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<box hibit="30" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="29" name="U" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="28" width="5" settings="5">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="23" width="2" name="size" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="21" name="L" usename="1">
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<c></c>
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</box>
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<box hibit="20" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="19" width="4" name="Rm" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="opcode" settings="4">
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="11" name="H" usename="1">
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<c></c>
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</box>
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<box hibit="10" settings="1">
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="FMULX_asimdelem_RH_H" oneofinclass="1" oneof="4" label="">
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<docvars>
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<docvar key="advsimd-reguse" value="2reg-element" />
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<docvar key="datatype" value="half" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FMULX" />
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<docvar key="reguse-datatype" value="2reg-element-half" />
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</docvars>
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<asmtemplate><text>FMULX </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "Q")"><T></a><text>, </text><a link="sa_vn" hover="First SIMD&FP source register (field "Rn")"><Vn></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "Q")"><T></a><text>, </text><a link="sa_vm" hover="Second SIMD&FP source register [V0-V15] (field "Rm")"><Vm></a><text>.H[</text><a link="sa_index" hover="Element index [0-7] (field "H:L:M")"><index></a><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/arithmetic/binary/element/mul/fp16/simd" mylink="aarch64.instrs.vector.arithmetic.binary.element.mul.fp16.simd" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;
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integer idxdsize = if H == '1' then 128 else 64;
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(H:L:M);
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integer esize = 16;
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integer datasize = if Q == '1' then 128 else 64;
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integer elements = datasize DIV esize;
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boolean mulx_op = (U == '1');</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Vector, single-precision and double-precision" oneof="4" id="iclass_2reg_element_single_and_double" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="advsimd-reguse" value="2reg-element" />
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<docvar key="datatype" value="single-and-double" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FMULX" />
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<docvar key="reguse-datatype" value="2reg-element-single-and-double" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/binary/element/mul/fp/simd" tworows="1">
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<box hibit="31" settings="1">
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<c>0</c>
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</box>
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<box hibit="30" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="29" name="U" usename="1" settings="1" psbits="x">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" name="size[1]" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="20" name="M" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Rm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="opcode" settings="4">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="11" name="H" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="FMULX_asimdelem_R_SD" oneofinclass="1" oneof="4" label="">
|
|
<docvars>
|
|
<docvar key="advsimd-reguse" value="2reg-element" />
|
|
<docvar key="datatype" value="single-and-double" />
|
|
<docvar key="instr-class" value="advsimd" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FMULX" />
|
|
<docvar key="reguse-datatype" value="2reg-element-single-and-double" />
|
|
</docvars>
|
|
<asmtemplate><text>FMULX </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_t_1" hover="Arrangement specifier (field "Q:sz") [2D,2S,4S]"><T></a><text>, </text><a link="sa_vn" hover="First SIMD&FP source register (field "Rn")"><Vn></a><text>.</text><a link="sa_t_1" hover="Arrangement specifier (field "Q:sz") [2D,2S,4S]"><T></a><text>, </text><a link="sa_vm_1" hover="Second SIMD&FP source register (field "M:Rm")"><Vm></a><text>.</text><a link="sa_ts" hover="Element size specifier (field "sz") [D,S]"><Ts></a><text>[</text><a link="sa_index_1" hover="Element index (field "sz:L:H") [H,H:L]"><index></a><text>]</text></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/vector/arithmetic/binary/element/mul/fp/simd" mylink="aarch64.instrs.vector.arithmetic.binary.element.mul.fp.simd" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer idxdsize = if H == '1' then 128 else 64;
|
|
integer index;
|
|
bit Rmhi = M;
|
|
case sz:L of
|
|
when '0x' index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(H:L);
|
|
when '10' index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(H);
|
|
when '11' UNDEFINED;
|
|
|
|
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
|
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
|
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rmhi:Rm);
|
|
|
|
if sz:Q == '10' then UNDEFINED;
|
|
integer esize = 32 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
|
|
integer datasize = if Q == '1' then 128 else 64;
|
|
integer elements = datasize DIV esize;
|
|
boolean mulx_op = (U == '1');</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="FMULX_asisdelem_RH_H" symboldefcount="1">
|
|
<symbol link="sa_hd"><Hd></symbol>
|
|
<account encodedin="Rd">
|
|
<intro>
|
|
<para>Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FMULX_asisdelem_RH_H" symboldefcount="1">
|
|
<symbol link="sa_hn"><Hn></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>Is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FMULX_asisdelem_R_SD" symboldefcount="1">
|
|
<symbol link="sa_v"><V></symbol>
|
|
<definition encodedin="sz">
|
|
<intro>Is a width specifier, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">sz</entry>
|
|
<entry class="symbol"><V></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">S</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">D</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="FMULX_asisdelem_R_SD" symboldefcount="1">
|
|
<symbol link="sa_d"><d></symbol>
|
|
<account encodedin="Rd">
|
|
<intro>
|
|
<para>Is the number of the SIMD&FP destination register, encoded in the "Rd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FMULX_asisdelem_R_SD" symboldefcount="1">
|
|
<symbol link="sa_n"><n></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>Is the number of the first SIMD&FP source register, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FMULX_asimdelem_RH_H, FMULX_asimdelem_R_SD" symboldefcount="1">
|
|
<symbol link="sa_vd"><Vd></symbol>
|
|
<account encodedin="Rd">
|
|
<intro>
|
|
<para>Is the name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FMULX_asimdelem_RH_H" symboldefcount="1">
|
|
<symbol link="sa_t"><T></symbol>
|
|
<definition encodedin="Q">
|
|
<intro>For the half-precision variant: is an arrangement specifier, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">Q</entry>
|
|
<entry class="symbol"><T></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">4H</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">8H</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="FMULX_asimdelem_R_SD" symboldefcount="2">
|
|
<symbol link="sa_t_1"><T></symbol>
|
|
<definition encodedin="Q:sz">
|
|
<intro>For the single-precision and double-precision variant: is an arrangement specifier, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">Q</entry>
|
|
<entry class="bitfield">sz</entry>
|
|
<entry class="symbol"><T></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">2S</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">4S</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">2D</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="FMULX_asimdelem_RH_H, FMULX_asimdelem_R_SD" symboldefcount="1">
|
|
<symbol link="sa_vn"><Vn></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>Is the name of the first SIMD&FP source register, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FMULX_asimdelem_RH_H, FMULX_asisdelem_RH_H" symboldefcount="1">
|
|
<symbol link="sa_vm"><Vm></symbol>
|
|
<account encodedin="Rm">
|
|
<docvars>
|
|
<docvar key="datatype" value="half" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For the half-precision variant: is the name of the second SIMD&FP source register, in the range V0 to V15, encoded in the "Rm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FMULX_asimdelem_R_SD, FMULX_asisdelem_R_SD" symboldefcount="2">
|
|
<symbol link="sa_vm_1"><Vm></symbol>
|
|
<account encodedin="M:Rm">
|
|
<docvars>
|
|
<docvar key="datatype" value="single-and-double" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For the single-precision and double-precision variant: is the name of the second SIMD&FP source register, encoded in the "M:Rm" fields.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FMULX_asimdelem_R_SD, FMULX_asisdelem_R_SD" symboldefcount="1">
|
|
<symbol link="sa_ts"><Ts></symbol>
|
|
<definition encodedin="sz">
|
|
<intro>Is an element size specifier, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">sz</entry>
|
|
<entry class="symbol"><Ts></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">S</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">D</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="FMULX_asimdelem_RH_H, FMULX_asisdelem_RH_H" symboldefcount="1">
|
|
<symbol link="sa_index"><index></symbol>
|
|
<account encodedin="H:L:M">
|
|
<docvars>
|
|
<docvar key="datatype" value="half" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For the half-precision variant: is the element index, in the range 0 to 7, encoded in the "H:L:M" fields.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FMULX_asimdelem_R_SD, FMULX_asisdelem_R_SD" symboldefcount="2">
|
|
<symbol link="sa_index_1"><index></symbol>
|
|
<definition encodedin="sz:L:H">
|
|
<intro>For the single-precision and double-precision variant: is the element index, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">sz</entry>
|
|
<entry class="bitfield">L</entry>
|
|
<entry class="symbol"><index></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">x</entry>
|
|
<entry class="symbol">H:L</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">H</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/vector/arithmetic/binary/element/mul/fp16/sisd" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
|
|
bits(datasize) operand1 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, datasize];
|
|
bits(idxdsize) operand2 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[m, idxdsize];
|
|
bits(esize) element1;
|
|
bits(esize) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index, esize];
|
|
<a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = FPCR[];
|
|
boolean merge = elements == 1 && <a link="impl-shared.IsMerging.1" file="shared_pseudocode.xml" hover="function: boolean IsMerging(FPCRType fpcr)">IsMerging</a>(fpcr);
|
|
bits(128) result = if merge then <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, 128] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(128);
|
|
|
|
for e = 0 to elements-1
|
|
element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
|
if mulx_op then
|
|
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.FPMulX.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMulX(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulX</a>(element1, element2, fpcr);
|
|
else
|
|
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(element1, element2, fpcr);
|
|
|
|
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = result;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|