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archived-ballistic/spec/arm64_xml/ftsmul_z_zz.xml
Ronald Caesar 26a677f8b4 decoder: Add ARM specification docs
Signed-off-by: Ronald Caesar <github43132@proton.me>
2025-12-12 18:11:36 -04:00

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<?xml version="1.0" encoding="utf-8"?>
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
<instructionsection id="ftsmul_z_zz" title="FTSMUL" type="instruction">
<docvars>
<docvar key="instr-class" value="sve" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="FTSMUL" />
</docvars>
<heading>FTSMUL</heading>
<desc>
<brief>Floating-point trigonometric starting value</brief>
<description>
<para>The <instruction>FTSMUL</instruction> instruction calculates the initial value for the <instruction>FTMAD</instruction> instruction. The instruction squares each element in the first source vector and then sets the sign bit to a copy of bit 0 of the corresponding element in the second source register, and places the results in the destination vector. This instruction is unpredicated.</para>
<para>To compute <arm-defined-word>sin(x)</arm-defined-word> or <arm-defined-word>cos(x)</arm-defined-word> the instruction is executed with elements of the first source vector set to <arm-defined-word>x</arm-defined-word>, adjusted to be in the range -π/4 &lt; <arm-defined-word>x</arm-defined-word> ≤ π/4.</para>
<para>The elements of the second source vector hold the corresponding value of the quadrant <arm-defined-word>q</arm-defined-word> number as an integer not a floating-point value. The value <arm-defined-word>q</arm-defined-word> satisfies the relationship (2q-1) × π/4 &lt; <arm-defined-word>x</arm-defined-word> ≤ (2q+1) × π/4.</para>
<para>This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.</para>
</description>
<status>Green</status>
<predicated>False</predicated>
<sm_policy>SM_0_only</sm_policy>
</desc>
<alias_list howmany="0"></alias_list>
<classes>
<iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
<docvars>
<docvar key="instr-class" value="sve" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="FTSMUL" />
</docvars>
<iclassintro count="1"></iclassintro>
<regdiagram form="32" psname="FTSMUL-Z.ZZ-_">
<box hibit="31" width="8" settings="8">
<c>0</c>
<c>1</c>
<c>1</c>
<c>0</c>
<c>0</c>
<c>1</c>
<c>0</c>
<c>1</c>
</box>
<box hibit="23" width="2" name="size" usename="1">
<c colspan="2"></c>
</box>
<box hibit="21" settings="1">
<c>0</c>
</box>
<box hibit="20" width="5" name="Zm" usename="1">
<c colspan="5"></c>
</box>
<box hibit="15" width="3" settings="3">
<c>0</c>
<c>0</c>
<c>0</c>
</box>
<box hibit="12" width="2" name="opc&lt;2:1&gt;" settings="2">
<c>0</c>
<c>1</c>
</box>
<box hibit="10" name="opc&lt;0&gt;" settings="1">
<c>1</c>
</box>
<box hibit="9" width="5" name="Zn" usename="1">
<c colspan="5"></c>
</box>
<box hibit="4" width="5" name="Zd" usename="1">
<c colspan="5"></c>
</box>
</regdiagram>
<encoding name="ftsmul_z_zz_" oneofinclass="1" oneof="1" label="">
<docvars>
<docvar key="instr-class" value="sve" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="FTSMUL" />
</docvars>
<asmtemplate><text>FTSMUL </text><a link="sa_zd" hover="Destination scalable vector register (field &quot;Zd&quot;)">&lt;Zd&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;size&quot;) [D,H,S]">&lt;T&gt;</a><text>, </text><a link="sa_zn" hover="First source scalable vector register (field &quot;Zn&quot;)">&lt;Zn&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;size&quot;) [D,H,S]">&lt;T&gt;</a><text>, </text><a link="sa_zm" hover="Second source scalable vector register (field &quot;Zm&quot;)">&lt;Zm&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;size&quot;) [D,H,S]">&lt;T&gt;</a></asmtemplate>
</encoding>
<ps_section howmany="1">
<ps name="FTSMUL-Z.ZZ-_" mylink="FTSMUL-Z.ZZ-_" enclabels="" sections="1" secttype="noheading">
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() then UNDEFINED;
if size == '00' then UNDEFINED;
constant integer esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);</pstext>
</ps>
</ps_section>
</iclass>
</classes>
<explanations scope="all">
<explanation enclist="ftsmul_z_zz_" symboldefcount="1">
<symbol link="sa_zd">&lt;Zd&gt;</symbol>
<account encodedin="Zd">
<intro>
<para>Is the name of the destination scalable vector register, encoded in the "Zd" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="ftsmul_z_zz_" symboldefcount="1">
<symbol link="sa_t">&lt;T&gt;</symbol>
<definition encodedin="size">
<intro>Is the size specifier, </intro>
<table class="valuetable">
<tgroup cols="2">
<thead>
<row>
<entry class="bitfield">size</entry>
<entry class="symbol">&lt;T&gt;</entry>
</row>
</thead>
<tbody>
<row>
<entry class="bitfield">00</entry>
<entry class="symbol">RESERVED</entry>
</row>
<row>
<entry class="bitfield">01</entry>
<entry class="symbol">H</entry>
</row>
<row>
<entry class="bitfield">10</entry>
<entry class="symbol">S</entry>
</row>
<row>
<entry class="bitfield">11</entry>
<entry class="symbol">D</entry>
</row>
</tbody>
</tgroup>
</table>
</definition>
</explanation>
<explanation enclist="ftsmul_z_zz_" symboldefcount="1">
<symbol link="sa_zn">&lt;Zn&gt;</symbol>
<account encodedin="Zn">
<intro>
<para>Is the name of the first source scalable vector register, encoded in the "Zn" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="ftsmul_z_zz_" symboldefcount="1">
<symbol link="sa_zm">&lt;Zm&gt;</symbol>
<account encodedin="Zm">
<intro>
<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
</intro>
</account>
</explanation>
</explanations>
<ps_section howmany="1">
<ps name="FTSMUL-Z.ZZ-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckNonStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
bits(VL) result;
for e = 0 to elements-1
bits(esize) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
bits(esize) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-aarch64.FPTrigSMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPTrigSMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPTrigSMul</a>(element1, element2, FPCR[]);
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</pstext>
</ps>
</ps_section>
</instructionsection>