archived-ballistic/spec/arm64_xml/isb.xml

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<instructionsection id="ISB" title="ISB -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="system" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="ISB" />
  </docvars>
  <heading>ISB</heading>
  <desc>
    <brief>
      <para>Instruction Synchronization Barrier</para>
    </brief>
    <authored>
      <para>Instruction Synchronization Barrier flushes the pipeline in the PE and is a context synchronization event. For more information, see <xref linkend="BEIJADJC">Instruction Synchronization Barrier (ISB)</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="System" oneof="1" id="iclass_system" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="system" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="ISB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch64/instrs/system/barriers/isb" tworows="1">
        <box hibit="31" width="10" settings="10">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" width="2" name="op0" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="CRn" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="CRm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" name="op2[2]" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="opc" usename="1" settings="2" psbits="xx">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="4" width="5" name="Rt" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
      </regdiagram>
      <encoding name="ISB_BI_barriers" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="instr-class" value="system" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="ISB" />
        </docvars>
        <asmtemplate><text>ISB  </text><text>{</text><a link="sa_option" hover="Specifies an optional limitation on the barrier operation">&lt;option&gt;</a><text>|#</text><a link="sa_imm" hover="Optional 4-bit unsigned immediate [0-15], default 15 (field &quot;CRm&quot;)">&lt;imm&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/system/barriers/isb" mylink="aarch64.instrs.system.barriers.isb" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">// No additional decoding required</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ISB_BI_barriers" symboldefcount="1">
      <symbol link="sa_option">&lt;option&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies an optional limitation on the barrier operation. Values are:</para>
          <list type="param">
            <listitem>
              <param>SY</param><content>Full system barrier operation, encoded as <field>CRm</field> = <binarynumber>0b1111</binarynumber>. Can be omitted.</content>
            </listitem>
          </list>
          <para>All other encodings of <field>CRm</field> are reserved. The corresponding instructions execute as full system barrier operations, but must not be relied upon by software.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ISB_BI_barriers" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="CRm">
        <intro>
          <para>Is an optional 4-bit unsigned immediate, in the range 0 to 15, defaulting to 15 and encoded in the "CRm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/system/barriers/isb" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-shared.InstructionSynchronizationBarrier.0" file="shared_pseudocode.xml" hover="function: InstructionSynchronizationBarrier()">InstructionSynchronizationBarrier</a>();
if <a link="impl-shared.HaveBRBExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveBRBExt()">HaveBRBExt</a>() &amp;&amp; <a link="impl-aarch64.BRBEBranchOnISB.0" file="shared_pseudocode.xml" hover="function: boolean BRBEBranchOnISB()">BRBEBranchOnISB</a>() then
    <a link="impl-aarch64.BRBEISB.0" file="shared_pseudocode.xml" hover="function: BRBEISB()">BRBEISB</a>();</pstext>
    </ps>
  </ps_section>
</instructionsection>