mirror of
https://github.com/pound-emu/ballistic.git
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313 lines
20 KiB
XML
313 lines
20 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="ld1w_z_p_bi" title="LD1W (scalar plus immediate, single register)" type="instruction">
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<docvars>
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LD1W" />
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</docvars>
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<heading>LD1W (scalar plus immediate, single register)</heading>
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<desc>
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<brief>Contiguous load unsigned words to vector (immediate index)</brief>
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<description>
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<para>Contiguous load of unsigned words to elements of a vector register from the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.</para>
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</description>
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<status>Green</status>
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<predicated>True</predicated>
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<sm_policy>SM_0_only</sm_policy>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="3">
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<txt>It has encodings from 3 classes:</txt>
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<a href="#iclass_32_elem">32-bit element</a>
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<txt>, </txt>
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<a href="#iclass_64_elem">64-bit element</a>
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<txt> and </txt>
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<a href="#iclass_128_elem">128-bit element</a>
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</classesintro>
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<iclass name="32-bit element" oneof="3" id="iclass_32_elem" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LD1W" />
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<docvar key="sve-elem-type" value="32-elem" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="LD1W-Z.P.BI-U32" tworows="1">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" width="3" name="dtype<3:1>" usename="1" settings="3">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="21" name="dtype<0>" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="20" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="imm4" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="3" settings="3">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="12" width="3" name="Pg" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="ld1w_z_p_bi_u32" oneofinclass="1" oneof="3" label="">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LD1W" />
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<docvar key="sve-elem-type" value="32-elem" />
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</docvars>
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<asmtemplate><text>LD1W </text><text>{</text><text> </text><a link="sa_zt" hover="Scalable vector register to be transferred (field "Zt")"><Zt></a><text>.S </text><text>}</text><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>/Z, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{</text><text>, #</text><a link="sa_imm" hover="Optional signed immediate vector offset [-8-7], default 0 (field "imm4")"><imm></a><text>, MUL VL</text><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="LD1W-Z.P.BI-U32" mylink="LD1W-Z.P.BI-U32" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
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integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zt);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
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constant integer esize = 32;
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constant integer msize = 32;
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boolean unsigned = TRUE;
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integer offset = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(imm4);</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="64-bit element" oneof="3" id="iclass_64_elem" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LD1W" />
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<docvar key="sve-elem-type" value="64-elem" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="LD1W-Z.P.BI-U64" tworows="1">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" width="3" name="dtype<3:1>" usename="1" settings="3">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="21" name="dtype<0>" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="imm4" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="3" settings="3">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="12" width="3" name="Pg" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="ld1w_z_p_bi_u64" oneofinclass="1" oneof="3" label="">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LD1W" />
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<docvar key="sve-elem-type" value="64-elem" />
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</docvars>
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<asmtemplate><text>LD1W </text><text>{</text><text> </text><a link="sa_zt" hover="Scalable vector register to be transferred (field "Zt")"><Zt></a><text>.D </text><text>}</text><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>/Z, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{</text><text>, #</text><a link="sa_imm" hover="Optional signed immediate vector offset [-8-7], default 0 (field "imm4")"><imm></a><text>, MUL VL</text><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="LD1W-Z.P.BI-U64" mylink="LD1W-Z.P.BI-U64" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
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integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zt);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
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constant integer esize = 64;
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constant integer msize = 32;
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boolean unsigned = TRUE;
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integer offset = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(imm4);</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="128-bit element" oneof="3" id="iclass_128_elem" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LD1W" />
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<docvar key="sve-elem-type" value="128-elem" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="FEAT_SVE2p1" feature="FEAT_SVE2p1" />
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</arch_variants>
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<regdiagram form="32" psname="LD1W-Z.P.BI-U128" tworows="1">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" name="dtype<1>" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="23" name="dtype<0>" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="22" width="3" settings="3">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="imm4" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="3" settings="3">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="12" width="3" name="Pg" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="ld1w_z_p_bi_u128" oneofinclass="1" oneof="3" label="">
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<docvars>
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<docvar key="instr-class" value="sve2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LD1W" />
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<docvar key="sve-elem-type" value="128-elem" />
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</docvars>
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<asmtemplate><text>LD1W </text><text>{</text><text> </text><a link="sa_zt" hover="Scalable vector register to be transferred (field "Zt")"><Zt></a><text>.Q </text><text>}</text><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>/Z, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{</text><text>, #</text><a link="sa_imm" hover="Optional signed immediate vector offset [-8-7], default 0 (field "imm4")"><imm></a><text>, MUL VL</text><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="LD1W-Z.P.BI-U128" mylink="LD1W-Z.P.BI-U128" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE2p1.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2p1()">HaveSVE2p1</a>() then UNDEFINED;
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integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zt);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
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constant integer esize = 128;
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constant integer msize = 32;
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boolean unsigned = TRUE;
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integer offset = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(imm4);</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="ld1w_z_p_bi_u128, ld1w_z_p_bi_u32, ld1w_z_p_bi_u64" symboldefcount="1">
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<symbol link="sa_zt"><Zt></symbol>
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<account encodedin="Zt">
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<intro>
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<para>Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ld1w_z_p_bi_u128, ld1w_z_p_bi_u32, ld1w_z_p_bi_u64" symboldefcount="1">
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<symbol link="sa_pg"><Pg></symbol>
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<account encodedin="Pg">
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<intro>
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<para>Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ld1w_z_p_bi_u128, ld1w_z_p_bi_u32, ld1w_z_p_bi_u64" symboldefcount="1">
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<symbol link="sa_xn_sp"><Xn|SP></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ld1w_z_p_bi_u128, ld1w_z_p_bi_u32, ld1w_z_p_bi_u64" symboldefcount="1">
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<symbol link="sa_imm"><imm></symbol>
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<account encodedin="imm4">
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<intro>
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<para>Is the optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="LD1W-Z.P.BI-U32" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">if esize < 128 then <a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>(); else <a link="impl-aarch64.CheckNonStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
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constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
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constant integer PL = VL DIV 8;
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constant integer elements = VL DIV esize;
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bits(64) base;
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bits(PL) mask = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
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bits(VL) result;
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bits(msize) data;
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constant integer mbytes = msize DIV 8;
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boolean contiguous = TRUE;
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boolean nontemporal = FALSE;
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boolean tagchecked = n != 31;
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<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescSVE.4" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescSVE(MemOp memop, boolean nontemporal, boolean contiguous, boolean tagchecked)">CreateAccDescSVE</a>(<a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>, nontemporal, contiguous, tagchecked);
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if !<a link="impl-aarch64.AnyActiveElement.2" file="shared_pseudocode.xml" hover="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then
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if n == 31 && <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_CHECKSPNONEACTIVE" file="shared_pseudocode.xml" hover="enumeration Unpredictable { Unpredictable_VMSR, Unpredictable_WBOVERLAPLD, Unpredictable_WBOVERLAPST, Unpredictable_LDPOVERLAP, Unpredictable_BASEOVERLAP, Unpredictable_DATAOVERLAP, Unpredictable_DEVPAGE2, Unpredictable_INSTRDEVICE, Unpredictable_RESCPACR, Unpredictable_RESMAIR, Unpredictable_S1CTAGGED, Unpredictable_S2RESMEMATTR, Unpredictable_RESTEXCB, Unpredictable_RESPRRR, Unpredictable_RESDACR, Unpredictable_RESVTCRS, Unpredictable_RESTnSZ, Unpredictable_RESTCF, Unpredictable_DEVICETAGSTORE, Unpredictable_OORTnSZ, Unpredictable_LARGEIPA, Unpredictable_ESRCONDPASS, Unpredictable_ILZEROIT, Unpredictable_ILZEROT, Unpredictable_BPVECTORCATCHPRI, Unpredictable_VCMATCHHALF, Unpredictable_VCMATCHDAPA, Unpredictable_WPMASKANDBAS, Unpredictable_WPBASCONTIGUOUS, Unpredictable_RESWPMASK, Unpredictable_WPMASKEDBITS, Unpredictable_RESBPWPCTRL, Unpredictable_BPNOTIMPL, Unpredictable_RESBPTYPE, Unpredictable_BPNOTCTXCMP, Unpredictable_BPMATCHHALF, Unpredictable_BPMISMATCHHALF, Unpredictable_RESTARTALIGNPC, Unpredictable_RESTARTZEROUPPERPC, Unpredictable_ZEROUPPER, Unpredictable_ERETZEROUPPERPC, Unpredictable_A32FORCEALIGNPC, Unpredictable_SMD, Unpredictable_NONFAULT, Unpredictable_SVEZEROUPPER, Unpredictable_SVELDNFDATA, Unpredictable_SVELDNFZERO, Unpredictable_CHECKSPNONEACTIVE, Unpredictable_SMEZEROUPPER, Unpredictable_NVNV1, Unpredictable_Shareability, Unpredictable_AFUPDATE, Unpredictable_DBUPDATE, Unpredictable_IESBinDebug, Unpredictable_BADPMSFCR, Unpredictable_ZEROBTYPE, Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP, Unpredictable_RESERVEDNSxB, Unpredictable_WFxTDEBUG, Unpredictable_LS64UNSUPPORTED, Unpredictable_MISALIGNEDATOMIC, Unpredictable_CLEARERRITEZERO, Unpredictable_ALUEXCEPTIONRETURN, Unpredictable_IGNORETRAPINDEBUG, Unpredictable_DBGxVR_RESS, Unpredictable_PMUEVENTCOUNTER, Unpredictable_PMSCR_PCT, Unpredictable_CounterReservedForEL2, Unpredictable_BRBFILTRATE, Unpredictable_MOPSOVERLAP31, Unpredictable_STOREONLYTAGCHECKEDCAS, Unpredictable_RESTC }">Unpredictable_CHECKSPNONEACTIVE</a>) then
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<a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
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else
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if n == 31 then <a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
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base = if n == 31 then <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[] else <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
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for e = 0 to elements-1
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if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
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integer eoff = (offset * elements) + e;
|
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bits(64) addr = base + eoff * mbytes;
|
|
data = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[addr, mbytes, accdesc];
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.Extend.3" file="shared_pseudocode.xml" hover="function: bits(N) Extend(bits(M) x, integer N, boolean unsigned)">Extend</a>(data, esize, unsigned);
|
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else
|
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(esize);
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|
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<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[t, VL] = result;</pstext>
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</ps>
|
|
</ps_section>
|
|
</instructionsection>
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