mirror of
https://github.com/pound-emu/ballistic.git
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280 lines
19 KiB
XML
280 lines
19 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="ldnt1h_mz_p_br" title="LDNT1H (scalar plus scalar, consecutive registers)" type="instruction">
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<docvars>
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<docvar key="instr-class" value="sve2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LDNT1H" />
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</docvars>
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<heading>LDNT1H (scalar plus scalar, consecutive registers)</heading>
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<desc>
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<brief>Contiguous load non-temporal of halfwords to multiple consecutive vectors (scalar index)</brief>
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<description>
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<para>Contiguous load non-temporal of halfwords to elements of two or four consecutive vector registers from the memory address generated by a 64-bit scalar base and scalar index which is added to the base address. After each element access the index value is incremented, but the index register is not updated.</para>
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<para>Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.</para>
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<para>A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon.</para>
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</description>
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<status>Green</status>
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<predicated>True</predicated>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from 2 classes:</txt>
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<a href="#iclass_to_2reg">Two registers</a>
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<txt> and </txt>
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<a href="#iclass_to_4reg">Four registers</a>
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</classesintro>
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<iclass name="Two registers" oneof="2" id="iclass_to_2reg" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve2" />
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<docvar key="isa" value="A64" />
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<docvar key="ldstruct-regcount" value="to-2reg" />
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<docvar key="mnemonic" value="LDNT1H" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="FEAT_SVE2p1" feature="FEAT_SVE2p1" />
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</arch_variants>
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<regdiagram form="32" psname="LDNT1H-MZ.P.BR-2" tworows="1">
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<box hibit="31" width="11" settings="11">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="20" width="5" name="Rm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" settings="1">
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<c>0</c>
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</box>
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<box hibit="14" name="msz<1>" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="13" name="msz<0>" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="12" width="3" name="PNg" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="4" name="Zt" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="0" name="N" usename="1" settings="1">
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<c>1</c>
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</box>
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</regdiagram>
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<encoding name="ldnt1h_mz_p_br_2" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="instr-class" value="sve2" />
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<docvar key="isa" value="A64" />
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<docvar key="ldstruct-regcount" value="to-2reg" />
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<docvar key="mnemonic" value="LDNT1H" />
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</docvars>
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<asmtemplate><text>LDNT1H </text><text>{</text><text> </text><a link="sa_zt1" hover="First scalable vector register to be transferred (field Zt)"><Zt1></a><text>.H-</text><a link="sa_zt2" hover="Second scalable vector register to be transferred (field Zt)"><Zt2></a><text>.H </text><text>}</text><text>, </text><a link="sa_png" hover="Governing scalable predicate register PN8-PN15 (field "PNg")"><PNg></a><text>/Z, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>, </text><a link="sa_xm" hover="64-bit general-purpose offset register (field "Rm")"><Xm></a><text>, LSL #1]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="LDNT1H-MZ.P.BR-2" mylink="LDNT1H-MZ.P.BR-2" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() && !<a link="impl-aarch64.HaveSVE2p1.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2p1()">HaveSVE2p1</a>() then UNDEFINED;
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
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integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('1':PNg);
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constant integer nreg = 2;
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integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zt:'0');
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constant integer esize = 16;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Four registers" oneof="2" id="iclass_to_4reg" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve2" />
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<docvar key="isa" value="A64" />
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<docvar key="ldstruct-regcount" value="to-4reg" />
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<docvar key="mnemonic" value="LDNT1H" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="FEAT_SVE2p1" feature="FEAT_SVE2p1" />
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</arch_variants>
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<regdiagram form="32" psname="LDNT1H-MZ.P.BR-4" tworows="1">
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<box hibit="31" width="11" settings="11">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="20" width="5" name="Rm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" settings="1">
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<c>1</c>
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</box>
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<box hibit="14" name="msz<1>" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="13" name="msz<0>" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="12" width="3" name="PNg" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="3" name="Zt" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="0" name="N" usename="1" settings="1">
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<c>1</c>
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</box>
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</regdiagram>
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<encoding name="ldnt1h_mz_p_br_4" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="instr-class" value="sve2" />
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<docvar key="isa" value="A64" />
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<docvar key="ldstruct-regcount" value="to-4reg" />
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<docvar key="mnemonic" value="LDNT1H" />
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</docvars>
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<asmtemplate><text>LDNT1H </text><text>{</text><text> </text><a link="sa_zt1_1" hover="First scalable vector register to be transferred (field Zt)"><Zt1></a><text>.H-</text><a link="sa_zt4" hover="Fourth scalable vector register to be transferred (field Zt)"><Zt4></a><text>.H </text><text>}</text><text>, </text><a link="sa_png" hover="Governing scalable predicate register PN8-PN15 (field "PNg")"><PNg></a><text>/Z, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>, </text><a link="sa_xm" hover="64-bit general-purpose offset register (field "Rm")"><Xm></a><text>, LSL #1]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="LDNT1H-MZ.P.BR-4" mylink="LDNT1H-MZ.P.BR-4" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() && !<a link="impl-aarch64.HaveSVE2p1.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2p1()">HaveSVE2p1</a>() then UNDEFINED;
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
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integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('1':PNg);
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constant integer nreg = 4;
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integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zt:'00');
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constant integer esize = 16;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="ldnt1h_mz_p_br_2" symboldefcount="1">
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<symbol link="sa_zt1"><Zt1></symbol>
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<account encodedin="Zt">
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<docvars>
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<docvar key="ldstruct-regcount" value="to-2reg" />
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</docvars>
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<intro>
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<para>For the two registers variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ldnt1h_mz_p_br_4" symboldefcount="2">
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<symbol link="sa_zt1_1"><Zt1></symbol>
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<account encodedin="Zt">
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<docvars>
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<docvar key="ldstruct-regcount" value="to-4reg" />
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</docvars>
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<intro>
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<para>For the four registers variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ldnt1h_mz_p_br_4" symboldefcount="1">
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<symbol link="sa_zt4"><Zt4></symbol>
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<account encodedin="Zt">
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<intro>
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<para>Is the name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ldnt1h_mz_p_br_2" symboldefcount="1">
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<symbol link="sa_zt2"><Zt2></symbol>
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<account encodedin="Zt">
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<intro>
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<para>Is the name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ldnt1h_mz_p_br_2, ldnt1h_mz_p_br_4" symboldefcount="1">
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<symbol link="sa_png"><PNg></symbol>
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<account encodedin="PNg">
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<intro>
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<para>Is the name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ldnt1h_mz_p_br_2, ldnt1h_mz_p_br_4" symboldefcount="1">
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<symbol link="sa_xn_sp"><Xn|SP></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ldnt1h_mz_p_br_2, ldnt1h_mz_p_br_4" symboldefcount="1">
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<symbol link="sa_xm"><Xm></symbol>
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<account encodedin="Rm">
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<intro>
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<para>Is the 64-bit name of the general-purpose offset register, encoded in the "Rm" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="LDNT1H-MZ.P.BR-2" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch64.HaveSVE2p1.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2p1()">HaveSVE2p1</a>() then <a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>(); else <a link="impl-aarch64.CheckStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEEnabled()">CheckStreamingSVEEnabled</a>();
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constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
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constant integer PL = VL DIV 8;
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constant integer elements = VL DIV esize;
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constant integer mbytes = esize DIV 8;
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bits(64) offset;
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bits(64) base;
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bits(PL) pred = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
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bits(PL * nreg) mask = <a link="impl-aarch64.CounterToPredicate.2" file="shared_pseudocode.xml" hover="function: bits(width) CounterToPredicate(bits(16) pred, integer width)">CounterToPredicate</a>(pred<15:0>, PL * nreg);
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array [0..3] of bits(VL) values;
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boolean contiguous = TRUE;
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boolean nontemporal = TRUE;
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boolean tagchecked = TRUE;
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<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescSVE.4" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescSVE(MemOp memop, boolean nontemporal, boolean contiguous, boolean tagchecked)">CreateAccDescSVE</a>(<a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>, nontemporal, contiguous, tagchecked);
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if !<a link="impl-aarch64.AnyActiveElement.2" file="shared_pseudocode.xml" hover="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then
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if n == 31 && <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_CHECKSPNONEACTIVE" file="shared_pseudocode.xml" hover="enumeration Unpredictable { Unpredictable_VMSR, Unpredictable_WBOVERLAPLD, Unpredictable_WBOVERLAPST, Unpredictable_LDPOVERLAP, Unpredictable_BASEOVERLAP, Unpredictable_DATAOVERLAP, Unpredictable_DEVPAGE2, Unpredictable_INSTRDEVICE, Unpredictable_RESCPACR, Unpredictable_RESMAIR, Unpredictable_S1CTAGGED, Unpredictable_S2RESMEMATTR, Unpredictable_RESTEXCB, Unpredictable_RESPRRR, Unpredictable_RESDACR, Unpredictable_RESVTCRS, Unpredictable_RESTnSZ, Unpredictable_RESTCF, Unpredictable_DEVICETAGSTORE, Unpredictable_OORTnSZ, Unpredictable_LARGEIPA, Unpredictable_ESRCONDPASS, Unpredictable_ILZEROIT, Unpredictable_ILZEROT, Unpredictable_BPVECTORCATCHPRI, Unpredictable_VCMATCHHALF, Unpredictable_VCMATCHDAPA, Unpredictable_WPMASKANDBAS, Unpredictable_WPBASCONTIGUOUS, Unpredictable_RESWPMASK, Unpredictable_WPMASKEDBITS, Unpredictable_RESBPWPCTRL, Unpredictable_BPNOTIMPL, Unpredictable_RESBPTYPE, Unpredictable_BPNOTCTXCMP, Unpredictable_BPMATCHHALF, Unpredictable_BPMISMATCHHALF, Unpredictable_RESTARTALIGNPC, Unpredictable_RESTARTZEROUPPERPC, Unpredictable_ZEROUPPER, Unpredictable_ERETZEROUPPERPC, Unpredictable_A32FORCEALIGNPC, Unpredictable_SMD, Unpredictable_NONFAULT, Unpredictable_SVEZEROUPPER, Unpredictable_SVELDNFDATA, Unpredictable_SVELDNFZERO, Unpredictable_CHECKSPNONEACTIVE, Unpredictable_SMEZEROUPPER, Unpredictable_NVNV1, Unpredictable_Shareability, Unpredictable_AFUPDATE, Unpredictable_DBUPDATE, Unpredictable_IESBinDebug, Unpredictable_BADPMSFCR, Unpredictable_ZEROBTYPE, Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP, Unpredictable_RESERVEDNSxB, Unpredictable_WFxTDEBUG, Unpredictable_LS64UNSUPPORTED, Unpredictable_MISALIGNEDATOMIC, Unpredictable_CLEARERRITEZERO, Unpredictable_ALUEXCEPTIONRETURN, Unpredictable_IGNORETRAPINDEBUG, Unpredictable_DBGxVR_RESS, Unpredictable_PMUEVENTCOUNTER, Unpredictable_PMSCR_PCT, Unpredictable_CounterReservedForEL2, Unpredictable_BRBFILTRATE, Unpredictable_MOPSOVERLAP31, Unpredictable_STOREONLYTAGCHECKEDCAS, Unpredictable_RESTC }">Unpredictable_CHECKSPNONEACTIVE</a>) then
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<a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
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else
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if n == 31 then <a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
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base = if n == 31 then <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[] else <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
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offset = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[m, 64];
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for r = 0 to nreg-1
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for e = 0 to elements-1
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if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, r * elements + e, esize) then
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bits(64) addr = base + (<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(offset) + r * elements + e) * mbytes;
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[values[r], e, esize] = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[addr, mbytes, accdesc];
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else
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[values[r], e, esize] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(esize);
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for r = 0 to nreg-1
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<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[t+r, VL] = values[r];</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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