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https://github.com/pound-emu/ballistic.git
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183 lines
10 KiB
XML
183 lines
10 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="LDR_lit_fpsimd" title="LDR (literal, SIMD&FP) -- A64" type="instruction">
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<docvars>
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<docvar key="address-form" value="literal" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LDR" />
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<docvar key="offset-type" value="off19s" />
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</docvars>
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<heading>LDR (literal, SIMD&FP)</heading>
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<desc>
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<brief>
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<para>Load SIMD&FP Register (PC-relative literal)</para>
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</brief>
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<authored>
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<para>Load SIMD&FP Register (PC-relative literal). This instruction loads a SIMD&FP register from memory. The address that is used for the load is calculated from the PC value and an immediate offset.</para>
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<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
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</authored>
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</desc>
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<operationalnotes>
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<para>If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="Literal" oneof="1" id="iclass_literal" no_encodings="3" isa="A64">
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<docvars>
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<docvar key="address-form" value="literal" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LDR" />
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<docvar key="offset-type" value="off19s" />
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</docvars>
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<iclassintro count="3"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/memory/literal/simdfp">
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<box hibit="31" width="2" name="opc" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="29" width="3" settings="3">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="26" name="V" settings="1">
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<c>1</c>
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</box>
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<box hibit="25" width="2" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="23" width="19" name="imm19" usename="1">
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<c colspan="19"></c>
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</box>
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<box hibit="4" width="5" name="Rt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="LDR_S_loadlit" oneofinclass="3" oneof="3" label="32-bit" bitdiffs="opc == 00">
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<docvars>
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<docvar key="address-form" value="literal" />
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<docvar key="address-form-reg-type" value="literal-32-fsreg" />
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<docvar key="atomic-ops" value="LDR-32-fsreg" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LDR" />
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<docvar key="offset-type" value="off19s" />
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<docvar key="reg-type" value="32-fsreg" />
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</docvars>
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<box hibit="31" width="2" name="opc">
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<c>0</c>
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<c>0</c>
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</box>
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<asmtemplate><text>LDR </text><a link="sa_st" hover="32-bit SIMD&FP register to be loaded (field "Rt")"><St></a><text>, </text><a link="sa_label" hover="Label from which the data is to be loaded (field imm19)"><label></a></asmtemplate>
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</encoding>
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<encoding name="LDR_D_loadlit" oneofinclass="3" oneof="3" label="64-bit" bitdiffs="opc == 01">
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<docvars>
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<docvar key="address-form" value="literal" />
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<docvar key="address-form-reg-type" value="literal-64-fsreg" />
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<docvar key="atomic-ops" value="LDR-64-fsreg" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LDR" />
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<docvar key="offset-type" value="off19s" />
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<docvar key="reg-type" value="64-fsreg" />
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</docvars>
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<box hibit="31" width="2" name="opc">
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<c>0</c>
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<c>1</c>
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</box>
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<asmtemplate><text>LDR </text><a link="sa_dt" hover="64-bit SIMD&FP register to be loaded (field "Rt")"><Dt></a><text>, </text><a link="sa_label" hover="Label from which the data is to be loaded (field imm19)"><label></a></asmtemplate>
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</encoding>
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<encoding name="LDR_Q_loadlit" oneofinclass="3" oneof="3" label="128-bit" bitdiffs="opc == 10">
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<docvars>
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<docvar key="address-form" value="literal" />
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<docvar key="address-form-reg-type" value="literal-128-fsreg" />
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<docvar key="atomic-ops" value="LDR-128-fsreg" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LDR" />
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<docvar key="offset-type" value="off19s" />
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<docvar key="reg-type" value="128-fsreg" />
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</docvars>
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<box hibit="31" width="2" name="opc">
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<c>1</c>
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<c>0</c>
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</box>
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<asmtemplate><text>LDR </text><a link="sa_qt" hover="128-bit SIMD&FP register to be loaded (field "Rt")"><Qt></a><text>, </text><a link="sa_label" hover="Label from which the data is to be loaded (field imm19)"><label></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/memory/literal/simdfp" mylink="aarch64.instrs.memory.literal.simdfp" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);
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boolean nontemporal = FALSE;
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integer size;
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bits(64) offset;
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case opc of
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when '00'
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size = 4;
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when '01'
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size = 8;
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when '10'
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size = 16;
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when '11'
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UNDEFINED;
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offset = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm19:'00', 64);
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boolean tagchecked = FALSE;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="LDR_D_loadlit" symboldefcount="1">
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<symbol link="sa_dt"><Dt></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the 64-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDR_Q_loadlit" symboldefcount="1">
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<symbol link="sa_qt"><Qt></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the 128-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDR_S_loadlit" symboldefcount="1">
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<symbol link="sa_st"><St></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the 32-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDR_D_loadlit, LDR_Q_loadlit, LDR_S_loadlit" symboldefcount="1">
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<symbol link="sa_label"><label></symbol>
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<account encodedin="imm19">
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<intro>
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<para>Is the program label from which the data is to be loaded. Its offset from the address of this instruction, in the range +/-1MB, is encoded as "imm19" times 4.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/memory/literal/simdfp" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(64) address = <a link="impl-aarch64.PC.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) PC[]">PC</a>[] + offset;
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bits(size*8) data;
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boolean privileged = PSTATE.EL != <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>;
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<a link="impl-aarch64.CheckFPEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPEnabled64()">CheckFPEnabled64</a>();
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<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescASIMD.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(<a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>, nontemporal, tagchecked);
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data = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[address, size, accdesc];
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<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[t, size*8] = data;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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