Files
archived-ballistic/spec/arm64_xml/luti2_z_ztz.xml
Ronald Caesar 26a677f8b4 decoder: Add ARM specification docs
Signed-off-by: Ronald Caesar <github43132@proton.me>
2025-12-12 18:11:36 -04:00

175 lines
8.7 KiB
XML

<?xml version="1.0" encoding="utf-8"?>
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
<instructionsection id="luti2_z_ztz" title="LUTI2 (single)" type="instruction">
<docvars>
<docvar key="instr-class" value="mortlach2" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="LUTI2" />
</docvars>
<heading>LUTI2 (single)</heading>
<desc>
<brief>Lookup table read with 2-bit indexes</brief>
<description>
<para>Copy 8-bit, 16-bit or 32-bit elements from ZT0 to one destination vector using packed 2-bit indices from a segment of the source vector register. A segment corresponds to a portion of the source vector that is consumed in order to fill the destination vector. The segment is selected by the vector segment index modulo the total number of segments.</para>
<para>This instruction is unpredicated.</para>
</description>
<status>Green</status>
<predicated>False</predicated>
<sm_policy>SM_1_only</sm_policy>
</desc>
<alias_list howmany="0"></alias_list>
<classes>
<iclass name="SME2" oneof="1" id="iclass_mortlach2" no_encodings="1" isa="A64">
<docvars>
<docvar key="instr-class" value="mortlach2" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="LUTI2" />
</docvars>
<iclassintro count="1"></iclassintro>
<arch_variants>
<arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
</arch_variants>
<regdiagram form="32" psname="LUTI2-Z.ZTZ-_">
<box hibit="31" width="13" settings="13">
<c>1</c>
<c>1</c>
<c>0</c>
<c>0</c>
<c>0</c>
<c>0</c>
<c>0</c>
<c>0</c>
<c>1</c>
<c>1</c>
<c>0</c>
<c>0</c>
<c>1</c>
</box>
<box hibit="18" settings="1">
<c>1</c>
</box>
<box hibit="17" width="4" name="i4" usename="1">
<c colspan="4"></c>
</box>
<box hibit="13" width="2" name="size" usename="1">
<c colspan="2"></c>
</box>
<box hibit="11" width="2" name="opc2" settings="2">
<c>0</c>
<c>0</c>
</box>
<box hibit="9" width="5" name="Zn" usename="1">
<c colspan="5"></c>
</box>
<box hibit="4" width="5" name="Zd" usename="1">
<c colspan="5"></c>
</box>
</regdiagram>
<encoding name="luti2_z_ztz_" oneofinclass="1" oneof="1" label="">
<docvars>
<docvar key="instr-class" value="mortlach2" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="LUTI2" />
</docvars>
<asmtemplate><text>LUTI2 </text><a link="sa_zd" hover="Destination scalable vector register (field &quot;Zd&quot;)">&lt;Zd&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;size&quot;) [B,H,S]">&lt;T&gt;</a><text>, ZT0, </text><a link="sa_zn" hover="Source scalable vector register (field &quot;Zn&quot;)">&lt;Zn&gt;</a><text>[</text><a link="sa_index" hover="Vector segment index [0-15] (field &quot;i4&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
</encoding>
<ps_section howmany="1">
<ps name="LUTI2-Z.ZTZ-_" mylink="LUTI2-Z.ZTZ-_" enclabels="" sections="1" secttype="noheading">
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
if size == '11' then UNDEFINED;
constant integer esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
integer isize = 2;
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);
integer imm = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(i4);
constant integer nreg = 1;</pstext>
</ps>
</ps_section>
</iclass>
</classes>
<explanations scope="all">
<explanation enclist="luti2_z_ztz_" symboldefcount="1">
<symbol link="sa_zd">&lt;Zd&gt;</symbol>
<account encodedin="Zd">
<intro>
<para>Is the name of the destination scalable vector register, encoded in the "Zd" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="luti2_z_ztz_" symboldefcount="1">
<symbol link="sa_t">&lt;T&gt;</symbol>
<definition encodedin="size">
<intro>Is the size specifier, </intro>
<table class="valuetable">
<tgroup cols="2">
<thead>
<row>
<entry class="bitfield">size</entry>
<entry class="symbol">&lt;T&gt;</entry>
</row>
</thead>
<tbody>
<row>
<entry class="bitfield">00</entry>
<entry class="symbol">B</entry>
</row>
<row>
<entry class="bitfield">01</entry>
<entry class="symbol">H</entry>
</row>
<row>
<entry class="bitfield">10</entry>
<entry class="symbol">S</entry>
</row>
<row>
<entry class="bitfield">11</entry>
<entry class="symbol">RESERVED</entry>
</row>
</tbody>
</tgroup>
</table>
</definition>
</explanation>
<explanation enclist="luti2_z_ztz_" symboldefcount="1">
<symbol link="sa_zn">&lt;Zn&gt;</symbol>
<account encodedin="Zn">
<intro>
<para>Is the name of the source scalable vector register, encoded in the "Zn" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="luti2_z_ztz_" symboldefcount="1">
<symbol link="sa_index">&lt;index&gt;</symbol>
<account encodedin="i4">
<intro>
<para>Is the vector segment index, in the range 0 to 15, encoded in the "i4" field.</para>
</intro>
</account>
</explanation>
</explanations>
<ps_section howmany="1">
<ps name="LUTI2-Z.ZTZ-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEEnabled()">CheckStreamingSVEEnabled</a>();
<a link="impl-aarch64.CheckSMEZT0Enabled.0" file="shared_pseudocode.xml" hover="function: CheckSMEZT0Enabled()">CheckSMEZT0Enabled</a>();
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
constant integer elements = VL DIV esize;
integer segments = esize DIV (isize * nreg);
integer segment = imm MOD segments;
bits(VL) indexes = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
bits(512) table = <a link="impl-aarch64.ZT0.read.1" file="shared_pseudocode.xml" hover="accessor: bits(width) ZT0[integer width]">ZT0</a>[512];
for r = 0 to nreg-1
integer base = (segment * nreg + r) * elements;
bits(VL) result = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[d+r, VL];
for e = 0 to elements-1
integer index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indexes, base+e, isize]);
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 32]&lt;esize-1:0&gt;;
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d+r, VL] = result;</pstext>
</ps>
</ps_section>
</instructionsection>