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archived-ballistic/spec/arm64_xml/mov_dupm_z_i.xml
Ronald Caesar 26a677f8b4 decoder: Add ARM specification docs
Signed-off-by: Ronald Caesar <github43132@proton.me>
2025-12-12 18:11:36 -04:00

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XML

<?xml version="1.0" encoding="utf-8"?>
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
<instructionsection id="MOV_dupm_z_i" title="MOV" type="alias">
<docvars>
<docvar key="alias_mnemonic" value="MOV" />
<docvar key="instr-class" value="sve" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="DUPM" />
</docvars>
<heading>MOV</heading>
<desc>
<brief>Move logical bitmask immediate to vector (unpredicated)</brief>
<description>
<para>Unconditionally broadcast the logical bitmask immediate into each element of the destination vector. This instruction is unpredicated. The immediate is a 64-bit value consisting of a single run of ones or zeros repeating every 2, 4, 8, 16, 32 or 64 bits.</para>
</description>
<status>Green</status>
<predicated>False</predicated>
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
</desc>
<aliasto refiform="dupm_z_i.xml" iformid="dupm_z_i">DUPM</aliasto>
<classes>
<iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
<docvars>
<docvar key="instr-class" value="sve" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="DUPM" />
</docvars>
<iclassintro count="1"></iclassintro>
<regdiagram form="32" psname="DUPM-Z.I-_">
<box hibit="31" width="14" settings="14">
<c>0</c>
<c>0</c>
<c>0</c>
<c>0</c>
<c>0</c>
<c>1</c>
<c>0</c>
<c>1</c>
<c>1</c>
<c>1</c>
<c>0</c>
<c>0</c>
<c>0</c>
<c>0</c>
</box>
<box hibit="17" width="13" name="imm13" usename="1">
<c colspan="13"></c>
</box>
<box hibit="4" width="5" name="Zd" usename="1">
<c colspan="5"></c>
</box>
</regdiagram>
<encoding name="MOV_dupm_z_i_" oneofinclass="1" oneof="1" label="">
<docvars>
<docvar key="alias_mnemonic" value="MOV" />
<docvar key="instr-class" value="sve" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="DUPM" />
</docvars>
<asmtemplate><text>MOV </text><a link="sa_zd" hover="Destination scalable vector register (field &quot;Zd&quot;)">&lt;Zd&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;imm13&lt;12&gt;:imm13&lt;5:0&gt;&quot;) [B,D,H,S]">&lt;T&gt;</a><text>, #</text><a link="sa_const" hover="64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits (field &quot;imm13&quot;)">&lt;const&gt;</a></asmtemplate>
<equivalent_to>
<asmtemplate><a href="dupm_z_i.xml#dupm_z_i_">DUPM</a><text> </text><a link="sa_zd" hover="Destination scalable vector register (field &quot;Zd&quot;)">&lt;Zd&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;imm13&lt;12&gt;:imm13&lt;5:0&gt;&quot;) [B,D,H,S]">&lt;T&gt;</a><text>, #</text><a link="sa_const" hover="64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits (field &quot;imm13&quot;)">&lt;const&gt;</a></asmtemplate>
<aliascond><a link="impl-aarch64.SVEMoveMaskPreferred.1" file="shared_pseudocode.xml" hover="function: boolean SVEMoveMaskPreferred(bits(13) imm13)">SVEMoveMaskPreferred</a>(imm13)</aliascond>
</equivalent_to>
</encoding>
</iclass>
</classes>
<explanations scope="all">
<explanation enclist="MOV_dupm_z_i_" symboldefcount="1">
<symbol link="sa_zd">&lt;Zd&gt;</symbol>
<account encodedin="Zd">
<intro>
<para>Is the name of the destination scalable vector register, encoded in the "Zd" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="MOV_dupm_z_i_" symboldefcount="1">
<symbol link="sa_t">&lt;T&gt;</symbol>
<definition encodedin="imm13&lt;12&gt;:imm13&lt;5:0&gt;">
<intro>Is the size specifier, </intro>
<table class="valuetable">
<tgroup cols="3">
<thead>
<row>
<entry class="bitfield">imm13&lt;12&gt;</entry>
<entry class="bitfield">imm13&lt;5:0&gt;</entry>
<entry class="symbol">&lt;T&gt;</entry>
</row>
</thead>
<tbody>
<row>
<entry class="bitfield">0</entry>
<entry class="bitfield">0xxxxx</entry>
<entry class="symbol">S</entry>
</row>
<row>
<entry class="bitfield">0</entry>
<entry class="bitfield">10xxxx</entry>
<entry class="symbol">H</entry>
</row>
<row>
<entry class="bitfield">0</entry>
<entry class="bitfield">110xxx</entry>
<entry class="symbol">B</entry>
</row>
<row>
<entry class="bitfield">0</entry>
<entry class="bitfield">1110xx</entry>
<entry class="symbol">B</entry>
</row>
<row>
<entry class="bitfield">0</entry>
<entry class="bitfield">11110x</entry>
<entry class="symbol">B</entry>
</row>
<row>
<entry class="bitfield">0</entry>
<entry class="bitfield">111110</entry>
<entry class="symbol">RESERVED</entry>
</row>
<row>
<entry class="bitfield">0</entry>
<entry class="bitfield">111111</entry>
<entry class="symbol">RESERVED</entry>
</row>
<row>
<entry class="bitfield">1</entry>
<entry class="bitfield">xxxxxx</entry>
<entry class="symbol">D</entry>
</row>
</tbody>
</tgroup>
</table>
</definition>
</explanation>
<explanation enclist="MOV_dupm_z_i_" symboldefcount="1">
<symbol link="sa_const">&lt;const&gt;</symbol>
<account encodedin="imm13">
<intro>
<para>Is a 64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits, encoded in the "imm13" field.</para>
</intro>
</account>
</explanation>
</explanations>
</instructionsection>